CN218938553U - Photoelectric co-packaging structure - Google Patents
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- CN218938553U CN218938553U CN202222760950.7U CN202222760950U CN218938553U CN 218938553 U CN218938553 U CN 218938553U CN 202222760950 U CN202222760950 U CN 202222760950U CN 218938553 U CN218938553 U CN 218938553U
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Abstract
The utility model discloses a photoelectric co-packaging structure, which comprises: circuit board, rewiring layer, a plurality of photoelectricity integrated chip. The rewiring layer is electrically connected with the circuit board, the plurality of photoelectric integrated chips are arranged on one side, far away from the circuit board, of the rewiring layer, each photoelectric integrated chip comprises a photoelectric integrated chip body, an electronic chip area and at least one photon chip area, the photon chip areas and the electronic chip areas are all arranged on the photoelectric integrated chip body, the electronic chip areas are electrically connected with the rewiring layer, and the photon chip areas of the two photoelectric integrated chips are communicated through the optical waveguide circuit. Therefore, the signal transmission rate inside the photoelectric co-packaging structure is improved, the design cost and development period of the photoelectric co-packaging structure and the loss of signal transmission between photoelectric integrated chips can be effectively reduced, the size of the photoelectric co-packaging structure can be determined according to the actual use scene, the universality is good, and the high-density packaging of the photoelectric integrated chips is realized.
Description
Technical Field
The utility model relates to the technical field of packaging, in particular to a photoelectric co-packaging structure.
Background
With the rising business of artificial intelligence, big data and the like, the demand of computing power of electronic products on chips is higher and higher, and the traditional integration of all functions on one chip cannot meet the demand, so that the core technology is developed, and the core technology is to assemble a plurality of special chips together through heterogeneous integration packaging technology, so that higher performance is realized at low cost.
However, in order to meet the high performance computing requirement in the prior art, a silicon interposer technology is currently available for heterogeneous integration of a plurality of chips, that is, a plurality of chips are flipped onto a large-size silicon interposer, and submicron-level high-density signal wires for interconnection between the chips are arranged on the silicon interposer, so that the cost of the silicon interposer used is high and the size is limited; or, the embedded silicon bridge technology is to flip a plurality of chips onto an adapter plate mixed by a rewiring layer and a silicon bridge, wherein high-density signal wires for interconnection between the chips are provided by the silicon bridge, and signal wires for fan-out of the chips to a circuit board are realized by the rewiring layer, but the embedding precision of the silicon bridge and the matching property among various materials are difficult, and the process is complex; or, in the rewiring layer interposer technology, a plurality of chips are flipped onto one large-size rewiring layer interposer, the rewiring layer provides high-density signal wires for interconnection among the chips and also provides signal wires for fan-out of the chips to a PCB, but the high-density signal wires are difficult to manufacture, and the dielectric properties of an organic insulating layer of the rewiring layer are difficult to meet the requirements of high-speed signal transmission among the chips.
Disclosure of Invention
The present utility model aims to solve at least one of the technical problems existing in the prior art. Therefore, an object of the present utility model is to provide a photoelectric co-packaging structure, which can realize rapid signal transmission between photoelectric integrated chips.
The photoelectric co-packaging structure according to the embodiment of the utility model comprises: the circuit board, rewiring layer, a plurality of photoelectricity integrated chip, rewiring layer with the circuit board electricity is connected, and a plurality of photoelectricity integrated chip is all located rewiring layer is kept away from one side of circuit board, every photoelectricity integrated chip includes photoelectricity integrated chip body, electron chip district and at least one photon chip district, photon chip district with electron chip district all locates photoelectricity integrated chip body, electron chip district with rewiring layer electricity is connected, two photoelectricity integrated chip's photon chip district passes through the optical waveguide circuit communication.
According to the photoelectric co-packaging structure, the photon chip area is arranged on the photoelectric integrated chip body, so that optical interconnection is realized between two adjacent photoelectric integrated chips through the photon chip area, the arrangement of high-density electric interconnection signal wires for transmission is reduced, the signal transmission rate inside the photoelectric co-packaging structure is improved, the optical interconnection structure between two adjacent photoelectric integrated chips is simple, the design cost and research and development period of the photoelectric co-packaging structure and the loss of signal transmission between the photoelectric integrated chips can be effectively reduced, the size of the photoelectric co-packaging structure can be determined according to the actual use scene, the universality is good, and the high-density packaging of the photoelectric integrated chips is realized.
In some embodiments, a plurality of the optoelectronic integrated chips comprises: the first photoelectric integrated chip comprises a first photoelectric integrated chip body, a first electronic chip area and a plurality of first photon chip areas, wherein the first electronic chip area and the plurality of first photon chip areas are arranged on the first photoelectric integrated chip body, and the first electronic chip area is electrically connected with the rewiring layer; each second optoelectronic integrated chip comprises a second optoelectronic integrated chip body, a second electronic chip area and a second photon chip area, wherein the second electronic chip area and the second photon chip area are both arranged on the second optoelectronic integrated chip body, the second electronic chip area is electrically connected with the rewiring layer, and the photon chip areas of a plurality of second optoelectronic integrated chips are respectively communicated with a plurality of first photon chip areas of the first optoelectronic integrated chips through a plurality of optical waveguide circuits.
In some embodiments, a plurality of the first photonic chip regions are disposed at intervals along a circumferential direction of the first optoelectronic integrated chip body, and a plurality of the second optoelectronic integrated chips are disposed at intervals along a circumferential direction of the first optoelectronic integrated chip.
In some embodiments, the number of the second optoelectronic integrated chips is equal to or less than the number of the plurality of photonic chip regions of the first optoelectronic integrated chip.
In some embodiments, the plurality of second optoelectronic integrated chips includes at least one first sub-optoelectronic integrated chip and at least one second sub-optoelectronic integrated chip, the second sub-optoelectronic integrated chip being located on a side of the first sub-optoelectronic integrated chip remote from the first optoelectronic integrated chip.
In some embodiments, the length of the optical waveguide circuit of the second photonic chip region of the second photonic optoelectronic integrated chip and the first photonic chip region of the first optoelectronic integrated chip is greater than the length of the optical waveguide circuit of the second photonic chip region of the first photonic chip and the first photonic chip region of the first optoelectronic integrated chip.
In some embodiments, the plurality of second optoelectronic integrated chips includes at least one third sub-optoelectronic integrated chip and at least one fourth sub-optoelectronic integrated chip, the second photonic chip region and the second electronic chip region of the third sub-optoelectronic integrated chip are sequentially arranged in a direction away from the corresponding first photonic chip region, and the second photonic chip region and the second electronic chip region of the fourth sub-optoelectronic integrated chip are arranged side by side in a circumferential direction of the first optoelectronic integrated chip.
In some embodiments, the photonic chip region of each of the optoelectronic integrated chips has a light emitting end and a light receiving end, and the light emitting end and the light receiving end of the photonic chip region of one of the two optoelectronic integrated chips communicate with the light receiving end and the light emitting end of the other of the two optoelectronic integrated chips in one-to-one correspondence through the optical waveguide circuit.
In some embodiments, the optoelectronic co-package structure further comprises: the electronic chip area of the photon integrated chip and the rewiring layer are respectively electrically connected through the conductive connecting pieces.
In some embodiments, the rewiring layer comprises: the photoelectric integrated chip comprises an insulating layer and a conductive piece, wherein the insulating layer is arranged on one side, far away from the circuit board, of the photoelectric integrated chip, the conductive piece is arranged in the insulating layer and is provided with a first end and a second end, and the first end and the second end are respectively electrically connected with the electronic chip areas of the two photoelectric integrated chips through two conductive connecting pieces.
Additional aspects and advantages of the utility model will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model.
Drawings
The foregoing and/or additional aspects and advantages of the utility model will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic layout diagram of an optoelectronic integrated chip according to an embodiment of the present utility model.
Fig. 2 is a schematic layout diagram of an optoelectronic integrated chip according to another embodiment of the present utility model.
Fig. 3 is a schematic diagram of an optoelectronic integrated chip according to the present utility model.
Fig. 4 is a schematic cross-sectional view of an optoelectronic co-package structure according to an embodiment of the present utility model.
Reference numerals:
100. a photoelectric co-packaging structure;
20. a rewiring layer; 21. an insulating layer; 22. a conductive member; 221. a first end; 222. a second end;
30. an optoelectronic integrated chip; 31. a photoelectric integrated chip body; 32. an electronic chip region; 33. a photonic chip region;
34. a first optoelectronic integrated chip; 341. a first optoelectronic integrated chip body; 342. a first electronic chip region; 343. a first photonic chip region; 35. a second optoelectronic integrated chip; 351. the second photoelectric integrated chip body; 352. a second electronic chip region; 353. a second photonic chip region; 36. a first sub-optoelectronic integrated chip; 37. a second sub-optoelectronic integrated chip; 38. a third sub-optoelectronic integrated chip; 39. a fourth sub-optoelectronic integrated chip;
40. an optical waveguide circuit; 50. conductive connection.
Detailed Description
Embodiments of the present utility model are described in detail below, and the embodiments described with reference to the accompanying drawings are exemplary, and a photoelectric co-package structure 100 according to an embodiment of the present utility model is described below with reference to fig. 1 to 4, the photoelectric co-package structure 100 including: a circuit board, a rewiring layer 20, a plurality of optoelectronic integrated chips 30.
Specifically, as shown in fig. 1-4, the rewiring layer 20 is electrically connected to the circuit board, the plurality of optoelectronic integrated chips 30 are all disposed on a side of the rewiring layer 20 away from the circuit board, each optoelectronic integrated chip 30 includes an optoelectronic integrated chip body 31, an electronic chip region 32, and at least one photonic chip region 33, the photonic chip region 33 and the electronic chip region 32 are all disposed on the optoelectronic integrated chip body 31, the electronic chip region 32 is electrically connected to the rewiring layer 20, and the photonic chip regions 33 of the two optoelectronic integrated chips 30 communicate through the optical waveguide circuit 40. For example, here, taking a communication connection between two optoelectronic integrated chips 30 as an example, at least one photonic chip region 33 and an electronic chip region 32 are disposed on each optoelectronic integrated chip 30, two adjacent photonic chip regions 33 are connected by an optical waveguide circuit 40, one photonic chip region 33 converts an electrical signal on the optoelectronic integrated chip 30 into an optical signal and transmits the optical signal to the photonic chip region 33 of the other optoelectronic integrated chip 30, and the photonic chip region 33 on the other optoelectronic integrated chip 30 converts an accepted optical signal into an electrical signal and transmits the electrical signal to the electronic chip region 32, so as to realize communication between different optoelectronic integrated chips 30.
According to the photoelectric co-packaging structure 100 of the embodiment of the utility model, the photonic chip region 33 is arranged on the photoelectric integrated chip body 31, so that the optical interconnection between two adjacent photoelectric integrated chips 30 is realized through the photonic chip region 33, the arrangement of high-density electrical interconnection signal wires for transmission is reduced, the signal transmission rate inside the photoelectric co-packaging structure 100 is improved, the optical interconnection between two adjacent photoelectric integrated chips 30 is realized, the structure is simple, the design cost and development period of the photoelectric co-packaging structure 100 and the loss of signal transmission between the photoelectric integrated chips 30 can be effectively reduced, the size of the photoelectric co-packaging structure 100 can be determined according to the actual use scene, the universality is good, and the high-density packaging of the photoelectric integrated chips 30 is realized.
In some embodiments, as shown in fig. 1 and 2, the plurality of optoelectronic integrated chips 30 includes: the first optoelectronic integrated chip 34 and a plurality of second optoelectronic integrated chips 35, the first optoelectronic integrated chip 34 includes a first optoelectronic integrated chip body 341, a first electronic chip area 342 and a plurality of first photonic chip areas 343, the first electronic chip area 342 and the plurality of first photonic chip areas 343 are all disposed on the first optoelectronic integrated chip body 341, and the first electronic chip area 342 is electrically connected with the rewiring layer 20; each of the second optoelectronic integrated chips 35 includes a second optoelectronic integrated chip body 351, a second electronic chip area 352 and a second photonic chip area 353, the second electronic chip area 352 and the second photonic chip area 353 are both disposed on the second optoelectronic integrated chip body 351, the second electronic chip area 352 is electrically connected to the rewiring layer 20, and the photonic chip areas 3351 of the plurality of second optoelectronic integrated chips 35 are respectively in communication with the plurality of first photonic chip areas 343 of the first optoelectronic integrated chip 34 through the plurality of optical waveguide lines 40.
That is, the first photonic chip region 343 and the second photonic chip region 353 are connected through the optical waveguide circuit 40, the first optoelectronic integrated chip 34 may be provided with a plurality of first photonic chip regions 343, the second optoelectronic integrated chip 35 may be provided with a plurality of second photonic chip regions 353, and the plurality of first photonic chip regions 343 and the plurality of second photonic chip regions 353 are in one-to-one correspondence. Alternatively, the number of the first optoelectronic integrated chips 34 is one, the number of the first photonic chip regions 343 is set on the first optoelectronic integrated chips 34, the number of the second optoelectronic integrated chips 35 is set on the second optoelectronic integrated chips 35, at least one second photonic chip region 353 is set on each second optoelectronic integrated chip 35, and the second photonic chip region 353 on each second optoelectronic integrated chip 35 corresponds to the first photonic chip region 343. For example, the first photonic chip region 343 is electrically connected to the first electronic chip region 342 through the first optoelectronic integrated chip body 341, the first photonic chip region 343 converts the received optical signal into an electrical signal and transmits the electrical signal to the first electronic chip region 342, and the first electronic chip region 342 is electrically connected to the rewiring layer 20.
Therefore, the first photonic chip area 343 is disposed on the first optoelectronic integrated chip 34, the second photonic chip area 353 is disposed on the second optoelectronic integrated chip 35, and one first optoelectronic integrated chip 34 can be connected with a plurality of second optoelectronic integrated chips 35, so that optical interconnection communication between the plurality of second optoelectronic integrated chips 35 and the first optoelectronic integrated chip 34 can be synchronously realized, and the processing capability of the optoelectronic integrated chip 30 on signals and the transmission rate of signals among different optoelectronic integrated chips 30 are improved.
In some embodiments, referring to fig. 1, a plurality of first photonic chip regions 343 are disposed at intervals along the circumferential direction of the first optoelectronic integrated chip body 341, and a plurality of second optoelectronic integrated chips 35 are disposed at intervals along the circumferential direction of the first optoelectronic integrated chip 34. The plurality of second optoelectronic integrated chips 35 are interconnected with the first photonic chip region 343. Therefore, the plurality of first photonic chip regions 343 are arranged at intervals, the plurality of second optoelectronic integrated chips 35 are arranged at intervals, interference among the plurality of second optoelectronic integrated chips 35 when the second optoelectronic integrated chips 35 are interconnected with the first optoelectronic integrated chips 34 can be avoided, and the second optoelectronic integrated chips 35 are convenient to install. Meanwhile, the plurality of second optoelectronic integrated chips 35 are connected with the first optoelectronic integrated chip 34, which can increase the signal transmission rate.
In some embodiments, as shown in fig. 2, the number of second optoelectronic integrated chips 35 is equal to or less than the number of the plurality of first photonic chip regions 343 of the first optoelectronic integrated chip 34. For example, as shown in fig. 1, the number of the second optoelectronic integrated chips 35 is the same as that of the first photonic chip regions 343, and each second optoelectronic integrated chip 35 is provided with a second photonic chip region 353, and the first photonic chip regions 343 and the second photonic chip regions 353 are connected by the optical waveguide line 40. As shown in fig. 2, the number of the second optoelectronic integrated chips 35 is smaller than the number of the first photonic chip regions 343, and at least one of the first photonic chip regions 343 is in an idle state. Therefore, the number of the second optoelectronic integrated chips 35 is smaller than or equal to the number of the first photonic chip regions 343, so that the universality of the optoelectronic integrated chips 30 can be improved, the development period of the optoelectronic co-packaged product can be shortened, and the optoelectronic integrated chips 30 do not need to be specially designed according to the interconnection of the photonic chip regions 33 among different optoelectronic integrated chips 30, so that the design cost of the optoelectronic integrated chips 30 is reduced.
In some embodiments, as shown in fig. 1, the plurality of second optoelectronic integrated chips 35 includes at least one first sub-optoelectronic integrated chip 36 and at least one second sub-optoelectronic integrated chip 37, and the second sub-optoelectronic integrated chip 37 is located on a side of the first sub-optoelectronic integrated chip 36 away from the first optoelectronic integrated chip 34, so that the first sub-optoelectronic integrated chip 36 and the second sub-optoelectronic integrated chip 37 can be better spaced apart, and the high efficiency of the signal transmission of the optical waveguide circuit 40 is ensured. Therefore, the second sub-optoelectronic integrated chip 37 is located at one side of the first sub-optoelectronic integrated chip 36 away from the first optoelectronic integrated chip 34, so that interference between the mounting positions of the first sub-optoelectronic integrated chip 36 and the second sub-optoelectronic integrated chip 37 can be avoided, and the number of the second optoelectronic integrated chips 35 is increased, so that the optoelectronic package structure has high-density signal transmission.
Optionally, in conjunction with fig. 1, the length of the optical waveguide line 40 of the second photonic chip region 353 of the second sub-optoelectronic integrated chip 37 and the first photonic chip region 343 of the first optoelectronic integrated chip 34 is greater than the length of the optical waveguide line 40 of the second photonic chip region 353 of the first sub-optoelectronic integrated chip 36 and the first photonic chip region 343 of the first optoelectronic integrated chip 34. Therefore, when the first sub-optoelectronic integrated chip 36 and the second sub-optoelectronic integrated chip 37 are circumferentially spaced apart from each other on the first optoelectronic integrated chip 34, the first sub-optoelectronic integrated chip 36 and the second sub-optoelectronic integrated chip 37 are distributed in a staggered manner, so that interference between the first sub-optoelectronic integrated chip 36 and the second sub-optoelectronic integrated chip 37 can be effectively avoided, and convenience in connection between the second optoelectronic integrated chip 35 and the first optoelectronic integrated chip 34 is increased.
In some embodiments, as shown in fig. 2, the plurality of second optoelectronic integrated chips 35 includes at least one third sub-optoelectronic integrated chip 38 and at least one fourth sub-optoelectronic integrated chip 39, the second photonic chip region 353 and the second electronic chip region 352 of the third sub-optoelectronic integrated chip 38 are sequentially arranged in a direction away from the corresponding first optoelectronic integrated chip 34, and the second photonic chip region 353 and the second electronic chip region 352 of the fourth sub-optoelectronic integrated chip 39 are arranged side by side in a circumferential direction of the first optoelectronic integrated chip 34. That is, when the third sub-optoelectronic integrated chip 38 is connected to the first optoelectronic integrated chip 34, the second photonic chip region 353 and the second electronic chip region 352 disposed on the third sub-optoelectronic integrated chip 38 are sequentially disposed away from the first optoelectronic integrated chip 34; when the fourth sub-optoelectronic integrated chip 39 is connected to the first optoelectronic integrated chip 34, the second photonic chip region 353 and the second electronic chip region 352 disposed on the fourth sub-optoelectronic integrated chip 39 are disposed at intervals along the circumferential direction of the first optoelectronic integrated chip 34, and the third sub-optoelectronic integrated chip 38 and the fourth sub-optoelectronic integrated chip 39 are disposed at intervals along the circumferential direction of the first optoelectronic integrated chip 34.
Therefore, the arrangement of the second photonic chip area 353 and the second electronic chip area 352 on the third sub-optoelectronic integrated chip 38 and the fourth sub-optoelectronic integrated chip 39 makes the position and the connection angle of the optoelectronic integrated chip 30 more reasonable, can improve the universality of the optoelectronic integrated chip 30, and ensures the packaging density of the optoelectronic co-packaging structure 100.
In some embodiments, the optical waveguide circuit 40 is a linear structure. That is, the optical waveguide line 40 extends straight between the first optoelectronic integrated chip 34 and the second optoelectronic integrated chip 35. Therefore, the optical waveguide circuit 40 and the linear structural member can reduce the design difficulty of the optical waveguide circuit 40, improve the transmission of optical signals in the optical waveguide circuit 40, and improve the transmission efficiency of the optical signals.
In some embodiments, the optical waveguide circuit 40 is a single-channel fiber circuit or a multi-channel fiber circuit. For example, the optical waveguide circuit 40 is a single-channel optical fiber circuit, and the optical waveguide circuit 40 disposed between the first photonic chip region 343 and the second photonic chip region 353 that are connected to each other has only one optical signal transmission channel, and only one mode of optical signal can be transmitted; the optical waveguide circuit 40 is a multi-channel optical fiber circuit, and the optical waveguide circuit 40 disposed between the first photonic chip region 343 and the second photonic chip region 353, which are connected to each other, has a plurality of optical signal transmission channels, and can simultaneously transmit optical signals of a plurality of different modes. Here, an appropriate optical waveguide line 40 may be selected between the first optoelectronic integrated chip 34 and the second optoelectronic integrated chip 35 according to the need. Thus, the optical waveguide circuit 40 is a single-channel optical fiber circuit or a multi-channel optical fiber circuit, so that optical interconnection between the first optoelectronic integrated chip 34 and the second optoelectronic integrated chip 35 can be realized.
Further, the photonic chip region 33 of each optoelectronic integrated chip 30 has a light emitting end and a light receiving end (not shown), and the light emitting end and the light receiving end of the photonic chip region 33 of one of the two optoelectronic integrated chips 30 communicate with the light receiving end and the light emitting end of the other one of the other optoelectronic integrated chips 30 one by one through the optical waveguide circuit 40. For example, when the first optoelectronic integrated chip 34 is optically interconnected with the second optoelectronic integrated chip 35, the first photonic chip region 343 and the second photonic chip region 353 are both provided with a light emitting end and a light receiving end, and the light emitting end of the first photonic chip region 343 is connected with the light receiving end of the second photonic chip region 353 through the optical waveguide circuit 40, and the light receiving end of the first photonic chip region 343 is connected with the light emitting end of the second photonic chip region 353 through the optical waveguide circuit 40. Therefore, the photonic chip region 33 on each optoelectronic integrated chip 30 is provided with a light emitting end and a light receiving end, which is favorable for the optical waveguide circuit 40 to realize the optical interconnection of different optoelectronic integrated chips 30 between the light emitting ends and the light receiving ends of different optoelectronic integrated chips 30, and is favorable for the optoelectronic integrated chips 30 to convert the received optical signals into electrical signals.
In some embodiments, as shown in fig. 4, the optoelectronic co-package structure 100 further includes: the plurality of conductive connection members 50 are disposed between the plurality of photonic integrated chips and the rewiring layer 20, and the electronic chip regions 32 of the plurality of photonic integrated chips and the rewiring layer 20 are electrically connected through the plurality of conductive connection members 50, that is, the first electronic chip regions 342 and the second electronic chip regions 352 are electrically connected to the rewiring layer 20, respectively. The conductive connection 50 connects the electronic chip region 32 and the rewiring layer 20 to achieve an electrical connection between the optoelectronic integrated chip 30 and the rewiring layer 20. The conductive connection 50 is a bump or a solder ball, and the conductive connection 50 is soldered to the electronic chip area 32 and the rewiring layer 20 of the optoelectronic integrated chip 30. The rewiring layer 20 is also connected to a circuit board (not shown) on the side remote from the optoelectronic integrated chip 30 by conductive connections 50. Thus, the conductive connection member 50 may facilitate electrical connection between the electronic chip region 32 and the rewiring layer 20, and the conductive connection member 50 may be a bump or a solder ball, which may facilitate solder connection between the electronic chip region 32 and the rewiring layer 20, and the solder connection may increase reliability of connection between the optoelectronic integrated chip 30 and the rewiring layer 20, so that signals may be stably transmitted between the electronic chip region 32 and the rewiring layer 20. The optical receiving end and the optical transmitting end of the photonic chip region 33 on the different optoelectronic integrated chips 30 are ensured to be aligned with the optical waveguide circuit 40 accurately, which is beneficial to fan-out the electrical signals on the electronic chip region 32 onto the circuit board.
In some embodiments, as shown in fig. 4, rewiring layer 20 comprises: the insulating layer 21 and the conductive member 22, the insulating layer 21 is disposed between the plurality of optoelectronic integrated chips 30 and the circuit board, the conductive member 22 is disposed in the insulating layer 21, the conductive member 22 has a first end 221 and a second end 222, the first end 221 and the second end 222 are electrically connected with the electronic chip areas 32 of the two photonic integrated chips through the two conductive connecting members 50 respectively, and the first end 221 and the second end 222 are located on a surface of the insulating layer 21 adjacent to one side of the optoelectronic integrated chips 30. At least part of the conductive members 22 are located in the insulating layer 21, and the conductive members 22 for connecting different optoelectronic integrated chips 30 are disposed at intervals. Therefore, the insulation layer 21 can increase the protection of the conductive element 22, avoid the occurrence of short circuit, enable the conductive element 22 to realize the electrical connection between different photoelectric integrated chips 30, increase the stability of connection, facilitate the electrical connection between the photoelectric integrated chips 30 and the rewiring layer 20, and improve the assembly efficiency of the photoelectric integrated chips 30 and the rewiring layer 20.
In the description of the present utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present utility model and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present utility model.
In the description of the utility model, a "first feature" or "second feature" may include one or more of such features. In the description of the present utility model, "plurality" means two or more. In the description of the utility model, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, and may also include the first and second features not being in direct contact but being in contact with each other by another feature therebetween. In the description of the utility model, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.
While embodiments of the present utility model have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the utility model, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. An optoelectronic co-package structure, comprising:
a circuit board;
a rewiring layer electrically connected to the circuit board;
the photoelectric integrated chips are arranged on one side, far away from the circuit board, of the rewiring layer, each photoelectric integrated chip comprises a photoelectric integrated chip body, an electronic chip area and at least one photon chip area, the photon chip areas and the electronic chip areas are arranged on the photoelectric integrated chip body, the electronic chip areas are electrically connected with the rewiring layer, and the photon chip areas of the two photoelectric integrated chips are communicated through an optical waveguide circuit.
2. The optoelectronic co-package structure of claim 1, wherein a plurality of the optoelectronic integrated chips comprise:
the first photoelectric integrated chip comprises a first photoelectric integrated chip body, a first electronic chip area and a plurality of first photon chip areas, wherein the first electronic chip area and the plurality of first photon chip areas are arranged on the first photoelectric integrated chip body, and the first electronic chip area is electrically connected with the rewiring layer;
the second photoelectric integrated chips comprise a second photoelectric integrated chip body, a second electronic chip area and a second photon chip area, wherein the second electronic chip area and the second photon chip area are both arranged on the second photoelectric integrated chip body, the second electronic chip area is electrically connected with the rewiring layer, and the photon chip areas of the second photoelectric integrated chips are respectively communicated with the first photon chip areas of the first photoelectric integrated chips through a plurality of optical waveguide circuits.
3. The optoelectronic co-package structure of claim 2, wherein a plurality of the first photonic chip regions are disposed at intervals along a circumferential direction of the first optoelectronic integrated chip body and a plurality of the second optoelectronic integrated chips are disposed at intervals along the circumferential direction of the first optoelectronic integrated chip.
4. The optoelectronic co-package structure of claim 2, wherein the number of the second optoelectronic integrated chips is equal to or less than the number of the plurality of photonic chip regions of the first optoelectronic integrated chip.
5. The optoelectronic co-package structure of claim 2, wherein the plurality of second optoelectronic integrated chips includes at least one first sub-optoelectronic integrated chip and at least one second sub-optoelectronic integrated chip, the second sub-optoelectronic integrated chip being located on a side of the first sub-optoelectronic integrated chip remote from the first optoelectronic integrated chip.
6. The optoelectronic co-package structure of claim 5, wherein a length of the optical waveguide circuit of the second photonic chip region of the second optoelectronic integrated chip and the first photonic chip region of the first optoelectronic integrated chip is greater than a length of the optical waveguide circuit of the second photonic chip region of the first optoelectronic integrated chip and the first photonic chip region of the first optoelectronic integrated chip.
7. The optoelectronic co-package structure of claim 2, wherein the plurality of second optoelectronic integrated chips includes at least one third sub-optoelectronic integrated chip and at least one fourth sub-optoelectronic integrated chip, the second photonic chip region and the second electronic chip region of the third sub-optoelectronic integrated chip being sequentially arranged in a direction toward and away from the corresponding first photonic chip region, the second photonic chip region and the second electronic chip region of the fourth sub-optoelectronic integrated chip being arranged side by side along a circumferential direction of the first optoelectronic integrated chip.
8. The optoelectronic co-package structure of claim 1, wherein the photonic chip region of each of the optoelectronic integrated chips has a light emitting end and a light receiving end, the light emitting end and the light receiving end of the photonic chip region of one of the two optoelectronic integrated chips being in one-to-one correspondence with the light receiving end and the light emitting end of the other of the two optoelectronic integrated chips through the optical waveguide circuit.
9. The optoelectronic co-package of any one of claims 1-8, further comprising:
the electronic chip area of the photoelectric integrated chip and the rewiring layer are respectively electrically connected through the conductive connecting pieces.
10. The optoelectronic co-package of claim 9, wherein the rewiring layer comprises:
the insulating layers are arranged on one sides of the photoelectric integrated chips, which are far away from the circuit board;
the conductive piece is arranged in the insulating layer and is provided with a first end and a second end, and the first end and the second end are respectively and electrically connected with the electronic chip areas of the two photoelectric integrated chips through the two conductive connecting pieces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202222760950.7U CN218938553U (en) | 2022-10-19 | 2022-10-19 | Photoelectric co-packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202222760950.7U CN218938553U (en) | 2022-10-19 | 2022-10-19 | Photoelectric co-packaging structure |
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| CN117250702A (en) * | 2023-11-20 | 2023-12-19 | 之江实验室 | Photoelectric co-packaging module and photoelectric co-packaging method |
| CN117250702B (en) * | 2023-11-20 | 2024-02-23 | 之江实验室 | Photoelectric co-packaging module and photoelectric co-packaging method |
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