CN117240315A - DC offset cancellation circuit and system - Google Patents
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Abstract
The invention provides a direct current offset cancellation circuit and a direct current offset cancellation system, which can rapidly control the on or off of corresponding branch current as long as a corresponding branch switch of each current mirror unit receives a corresponding control signal, so as to adjust the current flowing through a first output end and a second output end, thereby realizing direct current offset cancellation and improving the efficiency of direct current offset cancellation; in addition, the circuit is composed of a first reference current source, a second reference current source, a first current mirror unit group, a second current mirror unit group, a third current mirror unit group, a fourth current mirror unit group, a first switch, a second switch, a third switch and a fourth switch, and resistance and capacitance are not required to be introduced, so that the complexity of the circuit is reduced.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a direct current offset cancellation circuit and a direct current offset cancellation system.
Background
In the zero intermediate frequency receiver architecture, the output of the mixer in front of the intermediate frequency circuit module has larger direct current offset, the intermediate frequency circuit has higher gain, and the amplified offset voltage can lead the post-stage circuit to deviate from a normal direct current working point, thereby seriously affecting the linearity and the dynamic range of the circuit. So (DCOC) (DC Offset Cancellation, dc offset cancellation circuit) is typically required for suppression. The most widely used DCOC circuit is a low-pass negative feedback structure at present, and the basic method is to add a low-pass filter with very low cut-off frequency in a feedback path of an analog baseband, the low-frequency and direct-current signals are fed back to an input end by the feedback path without attenuation, and the offset of direct-current offset is realized by an adder at the input end, so that the direct-current offset is eliminated. The DC offset cancellation circuit requires that the bandwidth of a low-pass filter in a feedback path is low enough to enable a low-frequency useful signal to be normally transmitted, but the low bandwidth leads to long establishment time of DC offset and influences the efficiency of DC offset cancellation; in addition, the low pass filter structure in the feedback path is typically made up of a resistor-capacitor network, introducing additional pole-zero, making the circuit more complex.
Disclosure of Invention
The invention aims to provide a direct current offset cancellation circuit and a direct current offset cancellation system, which are used for improving the efficiency of direct current offset cancellation and reducing the complexity of a circuit.
The invention provides a direct current offset cancellation circuit, which comprises: the first current mirror unit group comprises a first reference current source, a second reference current source, a first current mirror unit group, a second current mirror unit group, a third current mirror unit group, a fourth current mirror unit group, a first switch, a second switch, a third switch and a fourth switch; the first reference current source is configured to have a first end connected with an external SINK end and a second end connected with a power supply; the first current mirror unit group is configured to have a first end connected with a second end of the first reference current source, and the second end is connected with a first end of the third current mirror unit group through a first switch and a second switch in sequence; the connection point between the first switch and the second switch is connected with the first output end; a third current mirror unit group configured such that a second terminal is connected to a first terminal of a second reference current source; a designated current source is connected in parallel between the first end and the second end; a second reference current source configured such that the first terminal is grounded; the second end is connected with an external SOURCE end; the second current mirror unit group is configured to have a first end connected with a second end of the first reference current source, and the second end is connected with the first end of the fourth current mirror unit group through a third switch and a fourth switch in sequence; a designated current source is connected in parallel between the first end and the second end; the connection point between the third switch and the fourth switch is connected with the second output end; a fourth current mirror unit group configured such that the second terminal is connected to the first terminal of the second reference current source; each current mirror unit in the first current mirror unit group, the second current mirror unit group, the third current mirror unit group and the fourth current mirror unit group is connected in series with a corresponding branch switch; each branch switch is used for being turned on or turned off according to the received control signal so as to control the branch current of the current mirror unit of the corresponding branch to be turned on or turned off.
Further, the first reference current source is configured to provide a first bias signal to each current mirror cell in the first current mirror cell group and the second current mirror cell group; the second reference current source is used for providing a second bias signal for each current mirror unit in the third current mirror unit group and the fourth current mirror unit group.
Further, each current mirror unit in the first current mirror unit group and each current mirror unit in the second current mirror unit group are used for copying the current of the first reference current source according to a preset proportion to obtain respective corresponding branch current; and each current mirror unit in the third current mirror unit group and the fourth current mirror unit group is used for copying the current of the second reference current source according to a preset proportion to obtain the corresponding branch current.
Further, the number of current mirror units in the first current mirror unit group, the second current mirror unit group, the third current mirror unit group and the fourth current mirror unit group is the same.
Further, for the first current mirror unit group or the fourth current mirror unit group, determining a control code bit according to the number of the current mirror units in the first current mirror unit group or the fourth current mirror unit group; the highest bit of the control code bits is used for controlling the on or off of the first switch and the fourth switch, and the other code bits except the highest bit are used for respectively controlling the on or off of the branch switches of the current mirror units in the first current mirror unit group and respectively controlling the on or off of the branch switches of the current mirror units in the fourth current mirror unit group.
Further, the highest bit of the control code bit is inverted to control the on or off of the second switch and the third switch; the other code bits except the highest bit are inverted to respectively control the on or off of the branch switches of the current mirror units in the second current mirror unit group and the on or off of the branch switches of the current mirror units in the third current mirror unit group.
Further, the current value of the specified current source, the current value of the first reference current source, and the current value of the second reference current source are the same.
Further, the control code bits are in binary form.
The invention provides a direct current offset cancellation system which comprises an intermediate frequency circuit, a comparator, a digital control module and any direct current offset cancellation circuit.
Further, the intermediate frequency circuit is configured such that the first input end is connected with the first output end of the direct current offset cancellation circuit; the second input end is connected with the second output end of the direct current offset cancellation circuit; the first output end of the intermediate frequency circuit is connected with the first input end of the comparator, and the second output end of the intermediate frequency circuit is connected with the second input end of the comparator; the comparator is configured to have an output end connected with the input end of the digital control module; and the digital control module is configured that the output end is connected with the control end of the direct current offset cancellation circuit so as to send a control signal to the direct current offset cancellation circuit through the control end.
According to the direct current offset cancellation circuit and the direct current offset cancellation system, as long as the corresponding branch switch of each current mirror unit receives the corresponding control signal, the corresponding branch current can be rapidly controlled to be turned on or off, and then the current flowing through the first output end and the second output end is adjusted, so that the direct current offset cancellation is realized, and the direct current offset cancellation efficiency is improved; in addition, the circuit is composed of a first reference current source, a second reference current source, a first current mirror unit group, a second current mirror unit group, a third current mirror unit group, a fourth current mirror unit group, a first switch, a second switch, a third switch and a fourth switch, and resistance and capacitance are not required to be introduced, so that the complexity of the circuit is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of a dc offset cancellation circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a codeword versus differential current according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a codeword versus differential current according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a dc offset cancellation system according to an embodiment of the present invention.
Icon: CS 1-a first reference current source; CS 2-a second reference current source; P_SOURCE-first current mirror cell group; n_source-second current mirror cell group; p_sink-third current mirror cell group; N_SINK-fourth current mirror unit group; s1-a first switch; s2-a second switch; s3-a third switch; s4-a fourth switch; out_p-a first output; out_n-second output terminal.
Detailed Description
The technical solutions of the present invention will be clearly and completely described in connection with the embodiments, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
At present, in a zero intermediate frequency receiver architecture, the output of a mixer in front of an intermediate frequency circuit module has larger direct current offset, an intermediate frequency circuit has very high gain, and an amplified offset voltage can lead a later-stage circuit to deviate from a normal direct current working point, so that the linearity and the dynamic range of the circuit are seriously affected. In addition, mismatch caused by the circuit structure and the manufacturing process also causes offset of the differential mode, which cannot be eliminated by the common mode feedback circuit, so DCOC (DC Offset Cancellation, direct current offset cancellation circuit) is generally required for suppression. The dc offset cancellation method in the related art generally has the following drawbacks: (1) The bandwidth of the low-pass filter in the feedback path is low enough to enable the low-frequency useful signal to be normally transmitted, but the low bandwidth leads to longer establishment time of direct current offset and influences the efficiency and effect of direct current offset cancellation; (2) The low pass filter structure in the feedback path is typically made up of a resistor-capacitor network, introducing additional pole-zero, making the circuit more complex. (3) The DCOC structure can be added only in the feedback path of the module, and a plurality of DCOC modules are needed to be added in a plurality of modules, so that the circuit becomes complex and the circuit area is increased. (4) The low pass filter and Gm, adder modules deteriorate the noise of the circuit. Based on this, the embodiment of the invention provides a direct current offset cancellation circuit and a system, and the technique can be applied to direct current offset calibration of a receiver or other applications requiring direct current offset calibration.
For the sake of understanding the present embodiment, first, a dc offset cancellation circuit disclosed in the present embodiment is described, as shown in fig. 1, including: the current SOURCE circuit comprises a first reference current SOURCE CS1, a second reference current SOURCE CS2, a first current mirror unit group P_SOURCE, a second current mirror unit group N_SOURCE, a third current mirror unit group P_SINK, a fourth current mirror unit group N_SINK, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4.
The first current mirror unit group p_source, the second current mirror unit group n_source, the third current mirror unit group p_sink, and the fourth current mirror unit group n_sink each generally include a plurality of current mirror units, and the number of current mirror units in each current mirror unit group is generally the same.
The first reference current source CS1 is configured to have a first end connected with an external SINK end and a second end connected with a power supply; the first current mirror unit group p_source is configured such that a first end is connected to a second end of the first reference current SOURCE CS1, and the second end is connected to a first end of the third current mirror unit group p_sink sequentially through the first switch S1 and the second switch S2; the connection point between the first switch S1 and the second switch S2 is connected to the first output terminal out_p; a third current mirror unit group p_sink configured such that the second terminal is connected to the first terminal of the second reference current source; a specified current source is connected in parallel between the first end and the second end.
A second reference current source configured such that the first terminal is grounded; the second end is connected with an external SOURCE end; the second current mirror unit group n_source is configured such that a first end is connected to a second end of the first reference current SOURCE CS1, and the second end is connected to a first end of the fourth current mirror unit group n_sink sequentially through the third switch S3 and the fourth switch S4; a designated current source is connected in parallel between the first end and the second end; the connection point between the third switch S3 and the fourth switch S4 is connected with the second output end OUT_N; the fourth current mirror unit group n_sink is configured such that the second terminal is connected to the first terminal of the second reference current source.
The power supply VDD can supply power to the circuit, and ensure the normal operation of the circuit, and the power supply signal can be set according to the actual requirement of the circuit, for example, 5V. The first switch S1 and the second switch S2 may be used to control the current direction of the first output terminal out_p; the third switch S3 and the fourth switch S4 may be used to control the current direction of the second output terminal out_n; the size of the specified current source can be set according to actual requirements, preferably, the current value of the specified current source is generally the same as the current value of the first current source and the current value of the second reference current source, namely a fixed minimum current unit which is not controlled by a switch and is always in an on state, so that the output differential current of the direct current offset cancellation circuit presents strict monotonicity along with the change of a code word; as shown in fig. 1, the first reference current SOURCE CS1 is generated by an ib_sink current connected to the outside, the second reference current SOURCE CS2 is generated by an ib_source current connected to the outside, the second terminal of the first reference current SOURCE CS1 is connected to the power supply VDD, the first terminal of the first current mirror unit group p_source and the first terminal of the second current mirror unit group n_source are both connected to the power supply VDD, the second terminal of the first current mirror unit group p_source is connected to the first output terminal out_p through the first switch S1, and the second terminal of the second current mirror unit group n_source is connected to the second output terminal out_n through the third switch S3; the first end of the third current mirror unit group P_SINK is connected with the first output end OUT_P through a second switch S2, and the first end of the fourth current mirror unit group N_SINK is connected with the second output end OUT_N through a fourth switch S4; the second end of the third current mirror unit group p_sink and the second end of the fourth current mirror unit group n_sink are grounded.
Each current mirror unit in the first current mirror unit group P_SOURCE, the second current mirror unit group N_SOURCE, the third current mirror unit group P_SINK and the fourth current mirror unit group N_SINK is connected in series with a corresponding branch switch; each branch switch is used for being turned on or turned off according to the received control signal so as to control the branch current of the current mirror unit of the corresponding branch to be turned on or turned off.
As shown in fig. 1, each current mirror unit in each current mirror unit group is connected in series with a corresponding branch switch, each branch switch can receive an externally input control signal, and control the on or off of the branch switch according to the corresponding control signal, for example, if the control signal of one branch switch is valid at a high level, when the control signal sent for the branch switch is at a high level, the branch switch is turned on, at this time, the branch current of the current mirror unit corresponding to the branch switch can be turned on, otherwise, the branch switch is turned off; if the control signal of a branch switch is effective at a low level, when the control signal sent by the branch switch is at a low level, the branch switch is turned on, and at the moment, the branch current of the current mirror unit corresponding to the branch switch can be turned on, otherwise, the branch current of the current mirror unit corresponding to the branch switch is turned off; according to the on or off state of each branch switch, the current flowing through the first output end OUT_P and the second output end OUT_N can be adjusted, and further, the DC offset is eliminated.
According to the direct current offset cancellation circuit, as long as the corresponding branch switch of each current mirror unit receives the corresponding control signal, the corresponding branch current can be rapidly controlled to be turned on or off, and then the current flowing through the first output end and the second output end is adjusted, so that direct current offset cancellation is realized, and the direct current offset cancellation efficiency is improved; in addition, the circuit is composed of a first reference current source, a second reference current source, a first current mirror unit group, a second current mirror unit group, a third current mirror unit group, a fourth current mirror unit group, a first switch, a second switch, a third switch and a fourth switch, and resistance and capacitance are not required to be introduced, so that the complexity of the circuit is reduced.
Further, the first reference current SOURCE CS1 is configured to provide the first bias signal VBP for each current mirror cell in the first current mirror cell group p_source and the second current mirror cell group n_source; the second reference current source CS2 is configured to provide the second bias signal VBN for each current mirror cell of the third current mirror cell group p_sink and the fourth current mirror cell group n_sink.
The first bias signal VBP may be understood as a bias current provided by the first reference current SOURCE CS1 for each current mirror cell in the first current mirror cell group p_source and for each current mirror cell in the second current mirror cell group n_source; each current mirror unit in the first current mirror unit group p_source and the second current mirror unit group n_source is connected to the first reference current SOURCE CS1 through a respective first bias signal VBP.
The second bias signal VBN may be understood as a bias current provided by the second reference current source CS2 for each current mirror cell in the third current mirror cell group p_sink and for each current mirror cell in the fourth current mirror cell group n_sink; each current mirror unit in the third current mirror unit group p_sink and the fourth current mirror unit group n_sink is connected to the second reference current source CS2 through a respective second bias signal VBN.
Further, each current mirror unit in the first current mirror unit group p_source and each current mirror unit in the second current mirror unit group n_source are configured to replicate the current of the first reference current SOURCE CS1 according to a preset proportion, so as to obtain respective corresponding branch current; each current mirror unit in the third current mirror unit group p_sink and the fourth current mirror unit group n_sink is configured to replicate the current of the second reference current source CS2 according to a preset proportion, so as to obtain respective corresponding branch current.
The above-mentioned preset ratio may be set according to actual requirements, for example, as shown in fig. 1, the first current mirror unit group p_source includes 8 current mirror units connected in parallel, and may be set according to a parallel sequence of 8 current mirror units, where the corresponding ratio is 1:2:4:8:16:32:64:128, each ratio value corresponds to 1 current mirror unit, and each current mirror unit copies current from the first reference current SOURCE CS1 according to the corresponding ratio, for example, a branch current corresponding to the first current mirror unit is the same as a current corresponding to the first reference current SOURCE CS 1; the branch current corresponding to the second current mirror unit is 2 times of the current corresponding to the first reference current source CS1, and so on; in the second current mirror unit group n_source, the third current mirror unit group p_sink, and the fourth current mirror unit group n_sink, the corresponding branch current of each current mirror unit may refer to the related description of the first current mirror unit group p_source, which is not described herein.
Further, the number of current mirror units in the first current mirror unit group p_source, the second current mirror unit group n_source, the third current mirror unit group p_sink, and the fourth current mirror unit group n_sink are the same.
In actual implementation, the number of the current mirror units in each current mirror unit group can be set according to actual requirements, for example, 8 current mirror units, 10 current mirror units and the like; however, the number of current mirror units in each current mirror unit group is generally the same, for example, each of the first current mirror unit group p_source, the second current mirror unit group n_source, the third current mirror unit group p_sink, and the fourth current mirror unit group n_sink includes 8 current mirror units connected in parallel to each other, and each current mirror unit is connected in series to a respective branch switch, etc.
Further, for the first current mirror unit group p_source or the fourth current mirror unit group n_sink, determining a control code bit according to the number of current mirror units in the first current mirror unit group p_source or the fourth current mirror unit group n_sink; the most significant bit of the control code bits is used for controlling the on or off of the first switch S1 and the fourth switch S4, and the other code bits except the most significant bit are used for respectively controlling the on or off of the branch switches of the current mirror units in the first current mirror unit group p_source and respectively controlling the on or off of the branch switches of the current mirror units in the fourth current mirror unit group n_sink.
For example, as shown in fig. 1, each current mirror unit group includes 8 current mirror units, taking the first current mirror unit group p_source or the fourth current mirror unit group n_sink as an example, the control signals of the two current mirror unit groups are the same, and a structure of 9 bits of control code bits is determined, which is denoted by ctl <8:0>, wherein ctl <7:0> is used for controlling each current mirror unit in the first current mirror unit group p_source and the fourth current mirror unit group n_sink; namely, the branch switch of the first current mirror unit is controlled through ctl <0>, the branch switch of the second current mirror unit is controlled through ctl <1>, and the branch switch of the 8 th current mirror unit is controlled through ctl <7>, so that the on-off of the branch current of each current mirror unit is controlled; the first switch S1 and the second switch S2 are used for controlling the current direction of the first output terminal out_p, and are implemented by a control signal ctl <8> with the highest bit, when ctl <8> is high, the first current mirror unit group p_source is turned on, and when ctl <8> is low, the third current mirror unit group p_sink is turned on.
Further, the highest bit of the control code bit is inverted to control the on or off of the second switch S2 and the third switch S3; the other code bits except the most significant bit are inverted to respectively control the on or off of the branch switch of the current mirror unit in the second current mirror unit group n_source and the on or off of the branch switch of the current mirror unit in the third current mirror unit group p_sink.
As shown in fig. 1, the third switch S3 and the fourth switch S4 are used to control the second output terminal out_n to pump the current direction, and when ctl <8> is high, the fourth current mirror unit group n_sink is turned on, and when ctl <8> is low, the second current mirror unit group n_source is turned on, so that the absolute values of the inflow and outflow currents of the first output terminal out_p and the second output terminal out_n are equal in combination with the above description.
Further, the current value of the specified current source, the current value of the first reference current source CS1, and the current value of the second reference current source CS2 are the same.
The current value of the specified current source is not controlled by a switch and is always in an on state, so that the differential current output by the direct current offset cancellation circuit can be strictly monotonically changed along with the change of the code word (because monotonicity is a precondition that a digital logic module is optimized by a dichotomy), if the branch is not added, each current mirror unit group comprises 8 current mirror units which are mutually connected in parallel, and corresponding proportions are set to be 1:2:4:8:16:32:64:128 respectively, as shown in a relation diagram of a code word and the differential current in fig. 2, when the code word is changed from 255 to 256, the differential current output by the direct current offset cancellation circuit is 0, and the direct current offset cancellation circuit does not have monotonicity; as shown in fig. 3, a relation diagram of a codeword and a differential current is shown, the fixed designated current source is added, and when the codeword changes from 255 to 256, the differential current output by the dc offset cancellation circuit changes according to one LSB (Least Significant Bit ) and is perfectly monotonically changed; the first switch S1 and the second switch S2 are used for controlling the current direction of the first output terminal out_p, the third switch S3 and the fourth switch S4 are used for controlling the current direction of the second output terminal out_n, the current direction is achieved through a control signal ctl <8> with the highest bit, when ctl <8> is at a low level, the second current mirror unit group n_source and the third current mirror unit group p_sink are opened, and when ctl <8> is at a high level, the first current mirror unit group p_source and the fourth current mirror unit group n_sink are opened, so that the absolute values of the inflow and outflow currents of the first output terminal out_p and the second output terminal out_n are equal.
Further, the control code bits are in binary form.
As shown in fig. 1, the working principle of the dc offset cancellation circuit is specifically described below: the currents of the first reference current SOURCE CS1 and the second reference current SOURCE CS2 are denoted by I, the current mirror units in the first current mirror unit group p_source and the second current mirror unit group n_source obtain mirror currents from the first reference current SOURCE CS1 through VBP, the current mirror units in the third current mirror unit group p_sink and the fourth current mirror unit group n_sink obtain mirror currents from the second reference current SOURCE CS2 through VBN, the mirror current ratio is 1:2:4:8:16:32:64:128, the control signals ctl <0:7> control the current mirror units in the first current mirror unit group p_source and the fourth current mirror unit group n_sink, the signals after the ctl <0:7> are inverted control the current mirror units in the third current mirror unit group p_sink and the second current mirror unit group n_source, and the fix current signals in the third current mirror unit group p_sink and the second current mirror unit group n_source are not always controlled in any open state. The first switch S1 and the fourth switch S4 are controlled by a control signal with the highest bit ctl <8> so as to determine the on-off state of the current of the whole first current mirror unit group P_SOURCE and the fourth current mirror unit group N_SINK; the second switch S2 and the third switch S3 are controlled by signals inverted by ctl <8> to determine the on/off state of the currents of the whole second current mirror unit group n_source and the third current mirror unit group p_sink. So when code is less than 256 (highest bit ctl <8> is 0, first switch S1 and fourth switch S4 are off, second switch S2 and third switch S3 are on), third current mirror unit group p_sink and second current mirror unit group n_source are opened, first output terminal out_p is current inflow, second output terminal out_n is current outflow; when the code is greater than 256 (the highest bit ctl <8> is 1, the first switch S1 and the fourth switch S4 are on, the second switch S2 and the third switch S3 are off), the first current mirror unit group p_source and the fourth current mirror unit group n_sink are turned on, the first output terminal out_p is a current outflow, and the second output terminal out_n is a current inflow.
When code=0 (binary: 0_0000_0000), the first switch S1 and the fourth switch S4 are off (ctl <8> is low), the second switch S2 and the third switch S3 are on (ctl <8> is high), so the third current mirror unit group p_sink and the second current mirror unit group n_source are turned on, and the current mirror unit control signals (ctl <0:7> is inverted) in the third current mirror unit group p_sink and the second current mirror unit group n_source are all high, so the currents flowing into the first output terminal out_p and the second output terminal out_n are both 256×i of maximum current.
When code=255 (binary: 0_1111_1111), the first switch S1 and the fourth switch S4 are off (ctl <8> is low), the second switch S2 and the third switch S3 are on (ctl <8> is inverted to be high), so that the third current mirror unit group p_sink and the second current mirror unit group n_source are opened, and the current mirror unit control signals (ctl <0:7> in the third current mirror unit group p_sink and the second current mirror unit group n_source) are all low, so that only the branch of fix exists in the two modules, and thus the current flowing into the first output terminal out_p and the current flowing OUT of the second output terminal out_n terminal are I.
When code=256 (binary: 1_0000_0000), the first switch S1 and the fourth switch S4 are on (ctl <8> is high), the second switch S2 and the third switch S3 are off (ctl <8> is inverted to be low), so the first current mirror cell group p_source and the fourth current mirror cell group n_sink are opened, the current mirror cell control signals (ctl <0:7 >) in the first current mirror cell group p_source and the fourth current mirror cell group n_sink modules are all low, and thus the first output terminal out_p and the second output terminal out_n do not flow in and OUT.
When code=511 (binary: 1_1111_1111), the first switch S1 and the fourth switch S4 are on (ctl <8> is high), the second switch S2 and the third switch S3 are off (ctl <8> is low), so the first current mirror cell group p_source and the fourth current mirror cell group n_sink are turned on, the current mirror cell control signals (ctl <0:7 >) in the first current mirror cell group p_source and the fourth current mirror cell group n_sink are all high, and thus the current flowing from the first output terminal out_p and the current flowing from the second output terminal out_n terminal are 255×i.
The current of the first output terminal OUT_P has the expression of (code-256). Times.I, and the current of the second output terminal OUT_N is just opposite to the current of the first output terminal OUT_P, and the expression is: (256-code) ×i, differential current expression: (code-256). Times.2I, positive and negative of the result value indicate the outflow and inflow current direction; if a fixed current branch I is not designed in the second current mirror unit group N_SOURCE and the third current mirror unit group P_SINK, when the codes are 255 and 256, the currents of the first output end OUT_P end and the second output end OUT_N end are 0, and a non-monotonic phenomenon exists, as shown in FIG. 2; after a fixed current I is added, the current expression of the circuit is modified so that the code is monotonic in the whole code word range, as shown in fig. 3.
According to the direct current offset cancellation circuit, as long as the corresponding branch switch of each current mirror unit receives the corresponding control signal, the corresponding branch current can be rapidly controlled to be turned on or off, and then the current flowing through the first output end and the second output end is adjusted, so that direct current offset cancellation is realized, and the direct current offset cancellation efficiency is improved; in addition, the circuit is composed of a first reference current source, a second reference current source, a first current mirror unit group, a second current mirror unit group, a third current mirror unit group, a fourth current mirror unit group, a first switch, a second switch, a third switch and a fourth switch, and resistance and capacitance are not required to be introduced, so that the complexity of the circuit is reduced.
The dc offset cancellation system provided by the present invention, as shown in fig. 4, includes an intermediate frequency circuit 40, a comparator, a digital control module 41, and any one of the dc offset cancellation circuits 42.
Further, the intermediate frequency circuit is configured such that the first input end is connected to the first output end out_p of the dc offset cancellation circuit; the second input end is connected with a second output end OUT_N of the direct current offset cancellation circuit; the first output end of the intermediate frequency circuit is connected with the first input end of the comparator, and the second output end of the intermediate frequency circuit is connected with the second input end of the comparator; the comparator is configured to have an output end connected with the input end of the digital control module; and the digital control module is configured that the output end is connected with the control end of the direct current offset cancellation circuit so as to send a control signal to the direct current offset cancellation circuit through the control end.
The intermediate frequency circuit mainly converts the high-frequency signal into an intermediate frequency signal, so that the next processing and operation are facilitated. Meanwhile, the intermediate frequency circuit can also perform a series of processing such as filtering, amplifying, demodulating, frequency conversion and the like, so that signals are more stable and reliable. The first input end of the comparator is usually an anode input end, the second input end of the comparator is usually a cathode input end, the comparator can compare signals input by the two input ends, output corresponding output results according to the comparison results, the output results are sent to the digital control module, the digital control module outputs corresponding code words according to the output results, and the code words are used as control signals to be sent to the direct current offset cancellation circuit so as to control the current output by the direct current offset cancellation circuit.
The digital control module can receive the final code word through a bisection method, (one code word is obtained according to the bisection method for each time and is given to the direct current offset eliminating circuit, and then the direction given by the next code word is continued according to the result output by the comparator, for example, the range of the code word is 0-512, the code word 256 is given for the first time, whether the code word for the second time is given for 128 or 384 is continuously searched according to the result of the first code word, and the like, and specific reference can be made to the related technology, and details are not repeated here.
The digital control module can output code words to the direct current offset eliminating circuit, then the output end of the direct current offset eliminating circuit pumps corresponding current, the direct current offset eliminating circuit is then injected into the intermediate frequency circuit and then converted into voltage, the voltage at two ends of the difference is compared through the comparator, the comparator outputs a comparison result to the digital control module, the digital control module then gives the next code word according to the result of the comparator, and then the digital control module sequentially executes the steps until the target code word is received, and the target code word can enable the voltage at two ends of the difference of the comparator to be basically equal.
According to the DC Offset cancellation system, the DC voltage of the differential circuit is calibrated in a current pumping and filling mode, a comparison result is output to the digital control module through the comparator connected to the differential end, and code word optimization is performed in the digital domain through a dichotomy, so that the function of canceling the DC Offset of the circuit is achieved.
The circuit architecture has a simple structure, current is generated by using a current mirror, current extraction or pouring is controlled by a switch network, and then output current flows through a feedback resistor of a rear-stage intermediate frequency link module (such as TIA), so that offset voltage is compensated; the structure has high calibration precision and quick time response, can accurately eliminate DC Offset on a receiving path, and has less influence on noise degradation of a circuit.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. A dc offset cancellation circuit comprising: the first current mirror unit group comprises a first reference current source, a second reference current source, a first current mirror unit group, a second current mirror unit group, a third current mirror unit group, a fourth current mirror unit group, a first switch, a second switch, a third switch and a fourth switch;
the first reference current source is configured to have a first end connected with an external SINK end and a second end connected with a power supply;
the first current mirror unit group is configured to have a first end connected with a second end of the first reference current source, and the second end is connected with a first end of the third current mirror unit group through a first switch and a second switch in sequence; the connection point between the first switch and the second switch is connected with a first output end;
the third current mirror unit group is configured that a second end is connected with a first end of the second reference current source; a designated current source is connected in parallel between the first end and the second end;
the second reference current source is configured such that a first end is grounded; the second end is connected with an external SOURCE end;
the second current mirror unit group is configured to have a first end connected with a second end of the first reference current source, and the second end is connected with the first end of the fourth current mirror unit group through a third switch and a fourth switch in sequence; a designated current source is connected in parallel between the first end and the second end; the connection point between the third switch and the fourth switch is connected with a second output end;
the fourth current mirror unit group is configured that a second end is connected with a first end of the second reference current source;
each current mirror unit in the first current mirror unit group, the second current mirror unit group, the third current mirror unit group and the fourth current mirror unit group is connected in series with a corresponding branch switch; each branch switch is used for being switched on or off according to the received control signal so as to control the branch current of the current mirror unit of the corresponding branch to be switched on or off.
2. The dc offset cancellation circuit of claim 1, wherein the first reference current source is configured to provide a first bias signal for each current mirror cell in the first current mirror cell group and the second current mirror cell group;
the second reference current source is configured to provide a second bias signal for each current mirror cell of the third current mirror cell group and the fourth current mirror cell group.
3. The direct current offset cancellation circuit of claim 1, wherein each current mirror unit in the first current mirror unit group and each current mirror unit in the second current mirror unit group are configured to replicate the current of the first reference current source according to a preset ratio to obtain respective corresponding branch current;
and each current mirror unit in the third current mirror unit group and the fourth current mirror unit group is used for copying the current of the second reference current source according to a preset proportion to obtain the corresponding branch current.
4. The dc offset cancellation circuit of claim 1, wherein the number of current mirror cells in the first current mirror cell group, the second current mirror cell group, the third current mirror cell group, and the fourth current mirror cell group are all the same.
5. The DC offset cancellation circuit of claim 1, wherein,
determining control code bits according to the number of current mirror units in the first current mirror unit group or the fourth current mirror unit group aiming at the first current mirror unit group or the fourth current mirror unit group;
the highest bit of the control code bit is used for controlling the on or off of the first switch and the fourth switch, and the other code bits except the highest bit are used for respectively controlling the on or off of the branch switches of the current mirror units in the first current mirror unit group and respectively controlling the on or off of the branch switches of the current mirror units in the fourth current mirror unit group.
6. The dc offset cancellation circuit of claim 5, wherein a highest bit of the control code bits is inverted to control on or off of the second switch and the third switch;
and inverting other code bits except the highest bit to respectively control the on or off of the branch switches of the current mirror units in the second current mirror unit group and the on or off of the branch switches of the current mirror units in the third current mirror unit group.
7. The direct current offset canceling circuit according to claim 1, wherein a current value of the specified current source, a current value of the first reference current source, and a current value of the second reference current source are the same.
8. The dc offset cancellation circuit of claim 5, wherein the control code bits are in binary form.
9. A dc offset cancellation system comprising an intermediate frequency circuit, a comparator, a digital control module, and a dc offset cancellation circuit as claimed in any one of claims 1 to 8.
10. The system for removing DC offset as set forth in claim 9, wherein,
the intermediate frequency circuit is configured that a first input end is connected with a first output end of the direct current offset cancellation circuit; the second input end is connected with the second output end of the direct current offset cancellation circuit; the first output end of the intermediate frequency circuit is connected with the first input end of the comparator, and the second output end of the intermediate frequency circuit is connected with the second input end of the comparator;
the comparator is configured to have an output end connected with the input end of the digital control module;
the digital control module is configured that an output end is connected with a control end of the direct current offset cancellation circuit so as to send a control signal to the direct current offset cancellation circuit through the control end.
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