CN117239543A - VCSEL chip of integrated optical element and manufacturing method thereof - Google Patents
VCSEL chip of integrated optical element and manufacturing method thereof Download PDFInfo
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Abstract
The application relates to the technical field of vertical cavity surface emitting lasers, in particular to an integrated optical element VCSEL chip and a manufacturing method thereof, wherein the VCSEL chip sequentially comprises a double-electrode P electrode, a double-electrode N electrode, a P electrode, an N electrode, a passivation layer, a GaAs contact layer, an N-DBR, an N-limiting layer, a multiple quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR, a GaAs cover layer and an SiO from bottom to top 2 The transparent dielectric film layer, the transparent sapphire substrate, the adhesion promoting layer, the nano-imprinting resin layer and the optical element; the P electrode and the N electrode are positioned on the same side of the VCSEL chip, and the materials are Ti/Pd/Ge/Pt/Au metal materials in sequence. The application reduces intermediate links by optimizing the chip structure and the materials and directly manufacturing the optical element in the chip processing process, has high matching degree, improves the manufacturing efficiency and the yield, is easy for large-scale production and has low cost.
Description
Technical Field
The application relates to the technical field of vertical cavity surface emitting lasers, in particular to an integrated optical element VCSEL chip and a manufacturing method thereof.
Background
VCSEL (vertical cavity surface emitting laser) chip is a surface emitting semiconductor laser, and VCSEL has the advantages of high efficiency, good beam quality, high precision, low power consumption, high reliability, high modulation rate, mass production, low manufacturing cost and the like, and is widely applied. The VCSEL chip has wide application, and different application fields and scenes, so that the chip needs to meet various requirements in terms of structure and performance, and higher requirements are put forward on performances such as beam form, optical power, heat dissipation, and the like, and the VCSEL chip is especially applied in fields such as vehicle-mounted laser radar, virtual Reality (VR), augmented Reality (AR), and 3D consumer electronics.
In the application process of a VCSEL chip specific device, in order to obtain a required light spot and beam quality, an optical element such as an AR diffractive optical waveguide, a microlens array, a DOE (diffractive optical element), a Diffuser (diffusion plate), and the like are generally added to the chip. For the mode of externally adding the optical element, the problems of whether the optical element is matched, complex and unstable manufacturing process, high manufacturing cost and the like exist. Therefore, a solution is needed to be developed that is low in cost and easy for mass production, and can solve the problems of light spots, light beam quality, light power, heat dissipation and the like.
Disclosure of Invention
Aiming at the defects of the prior art, the application provides the VCSEL chip of the integrated optical element and the manufacturing method thereof, and the VCSEL chip integrates the optical element directly in the chip processing process through optimizing the chip structure and materials, and the manufacturing of the optical element is uniformly completed as one working procedure of chip processing, so that intermediate links are reduced, the matching degree is high, the manufacturing efficiency and the yield are improved, and meanwhile, the requirements of performances in all aspects can be met.
The application provides an integrated optical element VCSEL chip, which comprises a double-electrode P electrode, a double-electrode N electrode, a P electrode, an N electrode, a passivation layer, a GaAs contact layer, an N-DBR, an N-limiting layer, a multiple quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR, a GaAs cover layer and an SiO sequentially from bottom to top 2 The transparent dielectric film layer, the transparent sapphire substrate, the adhesion promoting layer, the nano-imprinting resin layer and the optical element;
the P electrode and the N electrode are positioned on the same side of the VCSEL chip, and the materials are Ti/Pd/Ge/Pt/Au metal materials in sequence;
the oxidation layer is provided with oxidation holes at positions corresponding to the N electrode in the vertical direction;
the P-DBR and the N-DBR are formed by overlapping and growing AlGaAs and GaAs.
The P electrode and the N electrode are arranged on the same side, so that the subsequent manufacturing of the double electrodes is facilitated, and the post-packaging heat dissipation performance is improved; meanwhile, as the P-surface (P-DBR) and N-surface (GaAs contact layer) epitaxial material systems are close, the same P electrode and N electrode metal materials can be directly matched, the P electrode and the N electrode can be directly formed at one time in the subsequent manufacturing process, and the operation is convenient; the oxidation holes are formed in the oxidation layer, so that the adjustment of the quality of the light beam can be realized, and the light emitting efficiency is improved; by SiO 2 The transparent dielectric film layer bonds the GaAs laser epitaxial wafer with the transparent sapphire substrate, and transfers the substrate, transfers the material to the transparent substrate, and enhances the emission of laser; the optical element is directly manufactured on the transparent sapphire substrate, so that not only can the back surface light emission be realized, but also the light spot, the light beam quality and the light power can be optimized.
Further, in the above technical solution, the pair number of the P-DBR is 20-22 pairs, preferably 22 pairs; the number of pairs of N-DBRs is 35-40 pairs, preferably 40 pairs.
Further, in the above technical solution, the composition of aluminum in the oxide layer is 0.97.
Further, in the above technical scheme, the thickness of the adhesion promoting layer is 10nm-20nm.
Further, in the above technical scheme, the refractive index of the material adopted by the nano-imprinting resin layer is 1.6-1.7, the viscosity is 400cps-500cps, the transmittance is more than 95%, and the haze is 0.4.
Further, in the above technical solution, the optical element is any one of an AR diffractive optical waveguide, a microlens array, a DOE, and a Diffuser.
The application also provides a manufacturing method of the integrated optical element VCSEL chip, which comprises the following steps:
s1, growing an AlGaAs laser epitaxial wafer on a GaAs substrate from bottom to top by MOCVD (metal organic chemical vapor deposition), wherein the AlGaAs laser epitaxial wafer sequentially comprises the GaAs substrate, a GaAs buffer layer, a corrosion stop layer, a GaAs contact layer, an N-DBR, an N-limiting layer, a multiple quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR and a GaAs cover layer;
s2, depositing SiO (plasma enhanced chemical vapor deposition) on the epitaxial wafer by adopting an acid-base cleaning mode and utilizing PECVD (plasma enhanced chemical vapor deposition) 2 A transparent dielectric film layer;
s3, providing a transparent sapphire substrate, and cleaning the surface of the transparent sapphire substrate for later use by adopting an organic solution;
s4, siO of the epitaxial wafer 2 The transparent dielectric film layer and the cleaned transparent sapphire substrate are aligned in a graphite jig and then bonded;
s5, removing the GaAs substrate, the GaAs buffer layer and the corrosion stop layer in a chemical solution corrosion mode to expose the GaAs contact layer;
s6, adopting positive photoresist sleeve to etch to manufacture a patterned table top graph, and etching a circular table post with a certain angle through ICP etching (inductively coupled plasma etching);
s7, oxidizing the oxide layer of the chip in a wet oxidation mode to form oxidation holes with a certain size;
s8, cleaning the wafer by using weak alkaline ammonia water solution, depositing a passivation layer by PECVD, then manufacturing a mask contact through hole pattern by using positive photoresist, displaying the contact through hole by using developing solution, and etching the passivation layer which is not covered by the photoresist by using ICP;
s9, cleaning a wafer by using an organic solution cleaning mode, manufacturing an electrode pattern by using negative photoresist, evaporating an electrode by using an electron beam evaporation mode, and stripping by matching with a lift-off (uncovering a stripping process) process to obtain a P electrode and an N electrode;
s10, cleaning a wafer by using an organic solution cleaning mode, manufacturing a double-electrode pattern by using negative photoresist, sputtering a double-electrode seed metal layer by using a spray evaporation mode, adsorbing metal ions in chemical plating liquid by using the double-electrode seed metal layer to form a metal stack, completing thick double-electrode manufacturing, and stripping by matching with a lift-off process to obtain a double-electrode P electrode and a double-electrode N electrode;
s11, polishing the surface of a transparent sapphire substrate by adopting a mechanical grinding wheel grinding mode and matching with a polishing material, cleaning the surface of the polishing substrate by utilizing an organic solution, then, firstly, coating a tackifying layer coating, then, repeatedly and circularly spin-coating a nano imprinting resin layer, then, imprinting the surface of the nano imprinting resin layer by adopting a para-nano imprinting template, and finally, curing by adopting UV light to obtain a micro-nano optical element structure pattern;
s12, finally, testing the VCSEL chip by using a testing machine, separating the chips at fixed intervals in a hidden cutting and splitting mode to form VCESL single chips, and carrying out AOI (automatic optical inspection) sorting.
In the technical scheme, the chip structure and the materials are optimized, and the optical elements are directly integrated in the chip processing process, so that intermediate links are reduced, and the working efficiency and the yield are improved; the electrode is arranged on the same side, so that the chip packaging device is convenient to evaporate, low in cost and capable of achieving rapid chip packaging, meanwhile, bonding wires can be omitted for the chip, conditions are provided for brushing soldering flux and a solder paste chip mounting mode, the problem of poor heat dissipation is solved, the heat dissipation performance of the chip is improved, and the reliability of the device is improved.
Further, in the above technical solution S6, the power of ICP etching is 500w, bcl 3 Flow rate is 10sccm, cl 2 Flow rate is 5sccm, N 2 The flow rate is 30sccm; etching until the 4 th pair of P-DBRs, wherein the inclination of the table column is 65-75 degrees; and S7, the size of the oxidation hole is less than or equal to the size of the pillar. In the technical scheme, the round table column is designed to be provided with the inclined plane with a certain angle, so that the subsequent coverage of the side wall metal is facilitated, and the reliability is good; at the same time by controlling the size of the oxidation holeThe adjustment of the beam quality is realized.
Further, in the above technical solution S10, the material of the double-electrode seed metal layer is Ti, pt, au, and the thickness is 2000 angstroms-3000 angstroms; the material of the double-electrode P pole and the double-electrode N pole is Au, and the thickness is 4-5 mu m; the electroless plating process comprises the following steps: preparing chemical plating liquid with a volume ratio of metal agent to ion supplement of 25:1, heating to 60 ℃ in water bath, keeping the temperature for 60min, immersing the chip in the chemical plating liquid, and controlling the immersion time to be 50-60 min according to the chemical plating speed and the required electrode thickness. In the technical scheme, the thick electrode is used, so that welding wires can be omitted, and quick chip packaging is realized; the chemical plating mode is adopted, so that the production can be carried out according to the requirement, the cost is low and controllable, and the investment of a large amount of noble metals is not needed.
Further, in the above technical solution S11, the cyclic spin coating is repeated 3 times, and each spin coating is divided into two stages, the first stage spin coating at 500rpm for 15S and the second stage spin coating at 2000rpm for 30S.
Compared with the prior art, the application has the beneficial effects that:
1. the P electrode and the N electrode are arranged on the same side of the VCSEL chip, and the P surface and the N surface are similar in epitaxial material system, so that the P electrode and the N electrode can be directly formed at one time, the operation is convenient, the subsequent manufacturing of thick double electrodes is also convenient, the chip is free from welding wires, and the cost is low; meanwhile, in the subsequent processing process, quick chip packaging can be realized by brushing soldering flux and solder paste patches, and the heat dissipation performance of the chip is improved;
2. the application uses SiO 2 The GaAs laser epitaxial wafer is bonded with the transparent sapphire substrate through the transparent dielectric film layer, and materials are transferred to the transparent sapphire substrate in a substrate transfer mode, so that the emission of laser can be enhanced; meanwhile, the transparent sapphire is not fragile, so that the transparent sapphire deviates from SiO (silicon oxide) on the sapphire substrate 2 One surface of the transparent dielectric film layer can be directly used for further manufacturing an optical element in a para-position nano imprinting mode to form a light emitting surface, so that light spots, light beam quality and light power are optimized;
3. the application directly manufactures the optical element in the chip processing process through the optimization of the chip structure and the materials, and the back surface emits light, so that the intermediate links are reduced, the manufacturing efficiency and the yield are improved, and the requirements of all performances can be met;
4. the manufacturing method is simple, and the obtained VCSEL chip has good heat dissipation and reliability, is easy for large-scale production and has low cost.
Drawings
FIG. 1 is a schematic diagram of the structure of an integrated optical element VCSEL chip epitaxial wafer of the present application;
FIG. 2 is a schematic diagram of the structure of an integrated optical element VCSEL chip after epitaxial wafer bonding;
fig. 3 is a schematic diagram of the structure of an integrated optical element VCSEL chip of the present application.
The reference numerals in the schematic drawings indicate:
1. a GaAs substrate; 2. a GaAs buffer layer; 3. etching the stop layer; 4. a GaAs contact layer; 5. an N-DBR; 6. an N-confinement layer; 7. a multi-quantum well active layer; 8. a P-confinement layer; 9. an oxide layer; 10. a P-DBR; 11. a GaAs cover layer; 12. SiO (SiO) 2 A transparent dielectric film layer; 13. a transparent sapphire substrate; 14. an oxidation hole; 15. a passivation layer; 16-1, P electrode; 16-2, N electrode; 17-1, double electrode P pole; 17-2, double electrode N pole; 18. an adhesion promoting layer; 19. nanoimprinting the resin layer; 20. an optical element.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the application, its application, or uses. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be understood that the terms "first," "second," and the like are used for defining the components, and are merely for convenience in distinguishing the corresponding components, and the terms are not meant to have any special meaning unless otherwise indicated, so that the scope of the present application is not to be construed as being limited.
In the description of the present application, it should be understood that the azimuth or positional relationships indicated by the azimuth terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal", and "top, bottom", etc., are generally based on the azimuth or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and these azimuth terms do not indicate and imply that the apparatus or elements referred to must have a specific azimuth or be constructed and operated in a specific azimuth, and thus should not be construed as limiting the scope of protection of the present application; the orientation word "inner and outer" refers to inner and outer relative to the contour of the respective component itself.
Referring to fig. 1 to 3, it should be noted that the illustrations provided in the present embodiment are only schematic illustrations of the basic concept of the present application, and only the components related to the present application are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Some embodiments of the present application provide an integrated optical element VCSEL chip having a structure schematically shown in FIG. 3, wherein the VCSEL chip is sequentially provided with a double electrode P electrode 17-1, a double electrode N electrode 17-2, a P electrode 16-1, an N electrode 16-2, a passivation layer 15, a GaAs contact layer 4, an N-DBR5, an N-confinement layer 6, a multiple quantum well active layer 7, a P-confinement layer 8, an oxide layer 9, a P-DBR10, a GaAs cover layer 11, and SiO from bottom to top 2 A transparent dielectric film layer 12, a transparent sapphire substrate 13, an adhesion promoting layer 18, a nano-imprinting resin layer 19 and an optical element 20;
specifically, the P electrode and the N electrode are positioned on the same side of the VCSEL chip, and the materials are Ti/Pd/Ge/Pt/Au metal materials in sequence; the P-DBR and the N-DBR are formed by overlapping and growing AlGaAs and GaAs. Because the P-surface (P-DBR) and N-surface (GaAs contact layer) epitaxial material systems are close, the same P electrode and N electrode metal materials can be directly matched, so that the P electrode and the N electrode can form good ohmic contact with the epitaxial material in the subsequent high-temperature fusion process, and meanwhile, the adhesion is enhanced.
Specifically, the oxidation layer is provided with an oxidation hole 14 at a position corresponding to the N electrode in the vertical direction, and the adjustment of the beam quality can be realized by the size of the oxidation hole.
Specifically, the optical element is a well-known optical element, and may be any one of AR diffractive optical waveguide, microlens array, DOE, and differ.
Still further embodiments of the present application provide methods of fabricating integrated optical element VCSEL chips, comprising the steps of:
s1, growing an AlGaAs laser epitaxial wafer on a GaAs substrate 1 by using MOCVD; specifically, a GaAs buffer layer 2, a corrosion stop layer 3, a GaAs contact layer 4, an N-DBR5,N-limiting layer 6, a multiple quantum well active layer 7, a P-limiting layer 8, an oxide layer 9,P-DBR10 and a GaAs cover layer 11 are sequentially grown on a GaAs substrate, wherein the number of pairs of P-DBRs is 22, the number of pairs of N-DBRs is 40, and the aluminum component in the oxide layer is 0.97; the structure schematic diagram of the epitaxial wafer is shown in fig. 1;
s2, depositing SiO on the epitaxial wafer by PECVD (plasma enhanced chemical vapor deposition) in an acid-base cleaning mode 2 A transparent dielectric film layer; specifically, the acid-base solution is diluted hydrochloric acid (mixed solution of hydrochloric acid and water in a ratio of 1:30), and SiO (silicon dioxide) 2 The thickness of the transparent dielectric film layer is 3+/-0.2 mu m, the film deposition power is 150W, and the temperature is 325 ℃;
s3, providing a transparent sapphire substrate, and cleaning the surface of the transparent sapphire substrate for later use by adopting an organic solution; specifically, the thickness of the transparent sapphire substrate is 650+/-20 mu m, and the adopted organic solution is acetone;
s4, siO of the epitaxial wafer 2 The transparent dielectric film layer and the cleaned transparent sapphire substrate are aligned in a graphite jig and then bonded; specifically, the bonding process parameters are: the bonding time is 60+/-5 min, the bonding temperature is 320+/-10 ℃, and the bonding pressure is 12000kg-15000kg; wherein, the structure schematic diagram after bonding is shown in fig. 2;
s5, removing the GaAs substrate, the GaAs buffer layer and the corrosion stop layer in a chemical solution corrosion mode to expose the GaAs contact layer; specifically, a chemical solution corrosion mode is used for sequentially corroding a GaAs substrate, a GaAs buffer layer and a corrosion stop layer, the GaAs substrate has longer corrosion time and releases a large amount of heat in the process, a cooling circulation temperature control solution tank is used for reacting the GaAs substrate and the GaAs buffer layer, the GaAs substrate and the GaAs buffer layer are removed, the corrosion stop layer is completely exposed, QDR (quick discharge flushing tank) flushing is carried out, and then an acid system mixed solution (hydrochloric acid to phosphoric acid volume ratio of 1:2) is used for removing the corrosion stop layer, and then the GaAs contact layer is exposed;
s6, adopting positive photoresist sleeve to etch to manufacture a patterned table top graph, and etching a circular table post with a certain angle through ICP etching; specifically, the power of ICP etching is 500W, BCl 3 Flow rate is 10sccm, cl 2 Flow rate is 5sccm, N 2 The flow rate is 30sccm; etching until the 4 th pair of P-DBRs, wherein the pillar slope is 65-75 degrees;
s7, oxidizing the oxide layer of the chip in a wet oxidation mode to form an oxidation hole with a certain radius; specifically, the oxide layer of the chip is oxidized in a wet oxidation mode, and the size of the formed oxidation holes (namely light emitting holes) is as follows: the size of the light emergent hole is less than or equal to the size of the pillar, and the oxidation temperature is 415 ℃ and N is controlled by time for about 30min 2 /H 2 Oxidizing at a flow rate of 8L/min and a water vapor of 40g/h and a pressure of 850 mbar;
s8, cleaning the wafer by using weak alkaline ammonia water solution, depositing a passivation layer by PECVD, then manufacturing a mask contact through hole pattern by using positive photoresist, displaying the contact through hole by using developing solution, and etching the passivation layer which is not covered by the photoresist by using ICP; specifically, the weak base ammonia water solution is mixed solution of ammonia water and water in a volume ratio of 1:25, the thickness of the passivation layer is 1-2 mu m, the passivation layer is a SiN film, and the deposition temperature is 260+/-5 ℃; etching the passivation layer in the contact via by ICP to stop the surface of the epitaxial layer, wherein the etching gas is CF 4 /BCl 3 ；
S9, cleaning a wafer by using an organic solution cleaning mode, manufacturing an electrode pattern by using negative photoresist, evaporating an electrode by using an electron beam evaporation mode, and stripping by matching with a lift-off process to obtain a P electrode and an N electrode; specifically, the thicknesses of the P electrode and the N electrode are 2000-4000 angstroms, the materials comprise Ti/Pd/Ge/Pt/Au metal materials, and high-temperature fusion at 320 ℃ is carried out to obtain good ohmic contact between the electrode materials and the epitaxial materials, and meanwhile, the adhesion is enhanced;
s10, cleaning a wafer by using an organic solution cleaning mode, manufacturing a double-electrode pattern by using negative photoresist, sputtering a double-electrode seed metal layer by using a spray evaporation mode, adsorbing metal ions in chemical plating liquid by using the double-electrode seed metal layer to form a metal stack, completing thick double-electrode manufacturing, and stripping by matching with a lift-off process to obtain a double-electrode P electrode and a double-electrode N electrode; specifically, the materials of the double-electrode seed metal layer are Ti, pt and Au in sequence, the thickness is 2000-3000 angstroms, and the double-electrode seed metal layer is used for adsorbing metal ions in electroless plating liquid medicine to form a metal stack to manufacture double electrodes; the thickness of the thick double electrode is 4-5 μm, and is Au material, wherein the electroless plating process is as follows: preparing chemical plating liquid, heating a water bath to 60 ℃ for 60min, immersing a chip to be subjected to chemical plating in the chemical plating liquid, controlling the immersion time according to the chemical plating speed and the required electrode thickness, generally controlling the immersion time to be 50-60 min, and heating the chip to be subjected to the chemical plating for 5-8 min at 50 ℃ after the chemical plating is finished;
s11, polishing the surface of a transparent sapphire substrate by adopting a mechanical grinding wheel grinding mode and matching with a polishing material, cleaning the surface of the polishing substrate by utilizing an organic solution, then, firstly, coating a tackifying layer coating, then, repeatedly and circularly spin-coating a nano imprinting resin layer, then, imprinting the surface of the nano imprinting resin layer by adopting a para-nano imprinting template, and finally, curing by adopting UV light to obtain a micro-nano optical element structure pattern;
specifically, spin coating is adopted to coat an adhesion-promoting layer coating, and the thickness is 10nm-20nm; then, a nano-imprinting resin layer is coated by adopting a spin coating or slit coating mode, and the cyclic coating is repeated for 3 times, wherein the refractive index of the material of the nano-imprinting resin layer is 1.6-1.7, the viscosity is 400cps-500cps, the transmittance is more than 95%, the haze is 0.4, each spin coating is divided into two stages, the first stage is 500rpm spin coating for 15s, the second stage is 2000rpm spin coating for 30s, and the thickness of the nano-imprinting resin layer is 20 mu m; then adopting an alignment nano imprinting template (the template is printed with micro-nano optical element patterns), imprinting is carried out on the surface of the nano imprinting resin layer, finally, adopting UV light for 30 seconds for curing, wherein the wavelength of the UV light is preferably 320nm-400nm, removing the imprinting template to obtain a micro-nano optical element structure pattern (only taking the figure as an example), and removing residual nano resin through plasma;
s12, finally, testing the VCSEL chip by using a testing machine, separating the chips at fixed intervals in a hidden cutting and splitting mode to form VCESL single chips, and carrying out AOI sorting.
In summary, the electrodes are arranged on the same side through the optimization of the chip structure and the materials, and meanwhile, the P surface of the epitaxial structure is similar to the N surface material system, so that the P electrode and the N electrode can be directly formed at one time, and the operation is convenient; the oxidation holes are formed in the oxidation layer, so that the adjustment of the quality of the light beam can be realized, and the light emitting efficiency is improved; by SiO 2 The transparent dielectric film layer bonds the GaAs laser epitaxial wafer with the transparent sapphire substrate, and transfers the substrate, transfers the material to the transparent substrate, and enhances the emission of laser; the optical element is directly manufactured on the transparent sapphire substrate, so that not only can the back surface light emission be realized, but also the light spot, the light beam quality and the light power can be optimized; the obtained VCSEL chip has good heat dissipation and reliability, is easy for large-scale production and has low cost.
Finally, it should be emphasized that the foregoing description is merely illustrative of the preferred embodiments of the application, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and principles of the application, and any such modifications, equivalents, improvements, etc. are intended to be included within the scope of the application.
Claims (10)
1. An integrated optical element VCSEL chip is characterized in that the VCSEL chip is sequentially provided with a double electrode P electrode, a double electrode N electrode, a P electrode, an N electrode, a passivation layer, a GaAs contact layer, an N-DBR, an N-limiting layer, a multiple quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR, a GaAs cover layer and an SiO from bottom to top 2 The transparent dielectric film layer, the transparent sapphire substrate, the adhesion promoting layer, the nano-imprinting resin layer and the optical element;
the P electrode and the N electrode are positioned on the same side of the VCSEL chip, and the materials are Ti/Pd/Ge/Pt/Au metal materials in sequence;
the oxidation layer is provided with oxidation holes at positions corresponding to the N electrode in the vertical direction;
the P-DBR and the N-DBR are formed by overlapping and growing AlGaAs and GaAs.
2. An integrated optical element VCSEL chip as claimed in claim 1, wherein the P-DBR has a pair number of 20-22 pairs and the N-DBR has a pair number of 35-40 pairs.
3. An integrated optical element VCSEL chip as claimed in claim 1, wherein the composition of aluminum in the oxide layer is 0.97; the thickness of the tackifying layer is 10nm-20nm.
4. An integrated optical element VCSEL chip as claimed in claim 1, wherein the nanoimprint resin layer is made of a material having a refractive index of 1.6-1.7, a viscosity of 400-500 cps, a transmittance of > 95% and a haze of 0.4.
5. An integrated optical element VCSEL chip as claimed in claim 1, wherein the optical element is any of AR diffractive optical waveguide, microlens array, DOE, diffuser.
6. A method of fabricating an integrated optical element VCSEL chip according to any of claims 1-5, comprising the steps of:
s1, growing an AlGaAs laser epitaxial wafer on a GaAs substrate by using MOCVD, wherein the AlGaAs laser epitaxial wafer sequentially comprises the GaAs substrate, a GaAs buffer layer, a corrosion stop layer, a GaAs contact layer, an N-DBR, an N-limiting layer, a multiple quantum well active layer, a P-limiting layer, an oxide layer, a P-DBR and a GaAs cover layer;
s2, depositing SiO on the epitaxial wafer by PECVD (plasma enhanced chemical vapor deposition) in an acid-base cleaning mode 2 A transparent dielectric film layer;
s3, providing a transparent sapphire substrate, and cleaning the surface of the transparent sapphire substrate for later use by adopting an organic solution;
s4, siO of the epitaxial wafer 2 The transparent dielectric film layer and the cleaned transparent sapphire substrate are aligned in a graphite jig and then bonded;
s5, removing the GaAs substrate, the GaAs buffer layer and the corrosion stop layer in a chemical solution corrosion mode to expose the GaAs contact layer;
s6, adopting positive photoresist sleeve to etch to manufacture a patterned table top graph, and etching a circular table post with a certain angle through ICP etching;
s7, oxidizing the chip oxide layer in a wet oxidation mode to form oxidation holes with a certain size;
s8, cleaning the wafer by using weak alkaline ammonia water solution, depositing a passivation layer by PECVD, then manufacturing a mask contact through hole pattern by using positive photoresist, displaying the contact through hole by using developing solution, and etching the passivation layer which is not covered by the photoresist by using ICP;
s9, cleaning a wafer by using an organic solution cleaning mode, manufacturing an electrode pattern by using negative photoresist, evaporating an electrode by using an electron beam evaporation mode, and stripping by matching with a lift-off process to obtain a P electrode and an N electrode;
s10, cleaning a wafer by using an organic solution cleaning mode, manufacturing a double-electrode pattern by using negative photoresist, sputtering a double-electrode seed metal layer by using a dispenser evaporation mode, adsorbing metal ions in chemical plating liquid by using the double-electrode seed metal layer to form a metal stack, completing thick double-electrode manufacturing, and stripping by matching with a lift-off process to obtain a double-electrode P electrode and a double-electrode N electrode;
s11, polishing the surface of a transparent sapphire substrate by adopting a mechanical grinding wheel grinding mode and matching with a polishing material, cleaning the surface of the polishing substrate by utilizing an organic solution, then, firstly, coating a tackifying layer coating, then, repeatedly and circularly spin-coating a nano imprinting resin layer, then, imprinting the surface of the nano imprinting resin layer by adopting a para-nano imprinting template, and finally, curing by adopting UV light to obtain a micro-nano optical element structure pattern;
s12, finally, testing the VCSEL chip by using a testing machine, separating the chips at fixed intervals in a hidden cutting and splitting mode to form VCESL single chips, and carrying out AOI sorting.
7. The method of fabricating an integrated optical element VCSEL chip as claimed in claim 6, wherein in S6, the ICP etching power is 500w, bcl 3 Flow rate is 10sccm, cl 2 Flow rate is 5sccm, N 2 The flow rate is 30sccm; etching until the 4 th pair of P-DBRs, wherein the inclination of the table pillar is 65-75 degrees.
8. The method of fabricating an integrated optical element VCSEL chip of claim 6, wherein in S7, the oxide hole size is less than or equal to the pillar size.
9. The method for fabricating an integrated optical element VCSEL chip according to claim 6, wherein in S10, the material of the dual-electrode seed metal layer is Ti, pt, au, in order, with a thickness of 2000-3000 angstroms; the materials of the double-electrode P pole and the double-electrode N pole are Au, and the thickness is 4-5 mu m; the electroless plating process comprises the following steps: preparing chemical plating liquid with a volume ratio of metal agent to ion supplement of 25:1, heating to 60 ℃ in water bath, keeping the temperature for 60min, immersing the chip in the chemical plating liquid, and controlling the immersion time to be 50-60 min according to the chemical plating speed and the required electrode thickness.
10. The method of fabricating an integrated optical element VCSEL chip according to claim 6, wherein in S11, the spin coating is repeated 3 times, each spin coating being divided into two stages, a first stage spin coating at 500rpm for 15S and a second stage spin coating at 2000rpm for 30S.
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