CN117221038A - Signal preprocessing hardware platform based on OpenVPX bus - Google Patents
Signal preprocessing hardware platform based on OpenVPX bus Download PDFInfo
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- 238000012545 processing Methods 0.000 claims abstract description 10
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Abstract
The application provides a signal preprocessing hardware platform based on an OpenVPX bus, which is constructed based on an OpenVPX bus architecture by taking an insertion box as a unit, wherein a general board card is used as a unit module in the insertion box. And high-throughput-oriented high-speed serial buses are adopted among all universal boards in the plug box, high-speed data exchange is realized by adopting 40G Ethernet or 10G Ethernet, a gigabit network is adopted as a control network, and an I2C bus is adopted as a health management network. And optical fibers are adopted for data transmission among the plug boxes and among the cabinets, and high-speed data exchange is realized through 100G Ethernet or 40G Ethernet. The universal board card comprises: the system comprises a preprocessing board, a network exchange board and an interface control board. The preprocessing hardware platform plug-in box backboard adopts an OpenVPX bus single-star topological structure and is used for carrying the universal board card. The application supports wide bandwidth data transmission processing and wide bandwidth data exchange, and can realize the signal preprocessing function of a plurality of applications.
Description
Technical Field
The application relates to the technical field of radar and electronic countermeasure signal preprocessing, in particular to a signal preprocessing hardware platform based on an OpenVPX bus.
Background
With the development of electronic information systems, conventional function-oriented dedicated electronic devices gradually disappear in hardware configuration, and the functions of these devices become a part of the processing capacity of general (multi-function) modules, and develop toward standardization, generalization, serialization, and digitization by adopting an open structure. In a new combat system, the array application puts high demands on the amplitude-phase consistency among a plurality of channels, and a tight coupling design of an antenna, a radio frequency front end and analog-to-digital conversion is generally adopted. The signal preprocessing part receives the antenna aperture and the digital signal downloaded after the analog-digital conversion of the radio frequency front end, and completes the signal preprocessing functions of multiple applications such as radar, communication, radar countermeasure, communication countermeasure and the like.
Therefore, in order to meet the requirement of generalized modularization, research on a general-purpose signal preprocessing hardware platform to realize the signal preprocessing functions of multiple applications becomes a problem that needs to be processed at present.
Disclosure of Invention
The application provides a signal preprocessing hardware platform based on an OpenVPX bus, which can be used for solving the technical problem that a generalized module is lacking in the prior art.
The application provides a signal preprocessing hardware platform based on an OpenVPX bus, which comprises:
the hardware platform is based on an OpenVPX bus architecture, an insertion box is used as a unit, and a universal board card is used as a unit module in the insertion box;
between all universal boards in the plug-in box, adopting 40G Ethernet or 10G Ethernet to exchange high-speed data, adopting gigabit network as control network, and I2C bus as health management network; and optical fibers are adopted for data transmission among the plug boxes and among the cabinets, and high-speed data exchange is carried out through 100G Ethernet or 40G Ethernet.
Optionally, the universal board card includes: the device comprises a pretreatment board, a network exchange board and an interface control board;
the pretreatment board is used for processing the wide-bandwidth low-delay signals, receiving and transmitting high-speed backboard data and receiving and transmitting optical fiber data;
the network switching board is used for performing 100G Ethernet data switching, 40G Ethernet data switching, 10G Ethernet data switching and gigabit Ethernet data switching, high-speed data switching and control network;
the interface control board completes the functions of synchronous clock generation and distribution, external interface, combination control, health management and optical fiber data receiving and sending.
Optionally, the preprocessing hardware platform jack box backboard adopts an OpenVPX bus single star topology structure and is used for carrying a preprocessing board, a network switching board and an interface control board.
The plug box backboard adopts a 6U-size 10-slot structure, accords with BKP6-CEN10-11.2.4-n standard of an OpenVPX bus single-star topological structure, and comprises 1 exchange slot position and 9 load slots;
the 1 network exchange board is arranged in the exchange slot, and the 8 pretreatment boards and the 1 interface control board are arranged in the load slot.
Preferably, the preprocessing board adopts a 6U VPX structure and comprises 2 large-scale FPGAs (field programmable gate arrays) for performing wide-bandwidth low-delay signal processing, wherein each large-scale FPGA comprises more than 3000 hardware multipliers; the J0 connector is used for power transmission, health management bus, test bus and homologous clock receiving; the J1 connector is used for at least 1-path 4X40G Ethernet data exchange or 4-path 1X10G Ethernet data exchange; the J2 and J6 connectors are used for receiving and transmitting at least 48X optical fibers; the J3 and J5 connectors are used for receiving and transmitting a 32X high-speed serial bus; the J4 connector is used for gigabit Ethernet signal transceiving.
Optionally, the network switching board adopts a 6U VPX structure, and comprises an Ethernet switching chip and a plurality of connectors;
the Ethernet exchange chip performs 100G Ethernet data exchange, 40G Ethernet data exchange, 10G Ethernet data exchange and gigabit Ethernet data exchange; the Ethernet exchange chip supports at least 96X high-speed data transceiving; the J0 connector is used for power transmission, health management bus and test bus; the network exchange board J1 connector is used for 80X Ethernet data exchange, and is respectively bound into a 4X40G Ethernet data exchange form, a 1X10G Ethernet data exchange form or a 1X gigabit Ethernet data exchange form; the network switch board J6 connector is used for at least 12X optical fiber transceiving and supports 1-path 10X 100G Ethernet data exchange or 3-path 4X40G Ethernet data exchange.
Optionally, the interface control board adopts a 6U VPX structure, and comprises a CPU chip, an FPGA chip, a clock distribution chip and a plurality of connectors;
the CPU chip is used for control, the FPGA chip is used for partial interface function, and the clock distribution chip is used for clock distribution; the J0 connector is used for power transmission, health management bus, test bus and homologous clock distribution; the interface control board J1 connector is used for at least 1 path of 4X40G Ethernet data exchange or 4 paths of 1X10G Ethernet data exchange; the interface control board J2 connector, the interface control board J3 connector and the interface control board J5 connector support at least 16X high-speed serial bus transceiving and 8X PCIE buses; the interface control board J6 connector is used for receiving and transmitting at least 12X optical fibers; the interface control board J4 connector is used for gigabit Ethernet signal transceiving.
Optionally, at least 16X high-speed serial buses are connected between the adjacent preprocessing boards and the interface control boards to transmit and receive high-speed data, and the transmission bandwidth reaches 10Gbps; each preprocessing board and the interface control board are respectively connected with the network switching board through 1 path of 4X40G Ethernet to complete high-speed data exchange; each pretreatment board and the interface control board are respectively connected with the network exchange board through a 1-path 1X gigabit Ethernet, and the interface control board completes combination control through the gigabit Ethernet; the interface control board is connected with all the preprocessing boards through a J0MLVDS bus to finish synchronous clock distribution; the interface control board is connected with all the preprocessing boards through a J0I 2C bus to complete the health management function.
The application has the beneficial effects that: the number of the general board card modules is few and is only 3; the data transmission processing of the wide bandwidth, each preprocessing board supports the optical fiber transceiving bandwidth to be 480Gbps, and the data transceiving bandwidth between boards is at least 160Gbps; the wide bandwidth data exchange, each universal board card supports 40G Ethernet data exchange, and the plug-in boxes support 100G Ethernet data exchange; meets the standard specification of OpenVPX.
Drawings
FIG. 1 is a schematic diagram of a preprocessing hardware platform architecture according to an embodiment of the present application;
FIG. 2 is a schematic diagram of signal connection of a backplane of a preprocessing hardware platform and an enclosure provided by an embodiment of the present application;
fig. 3 is a schematic diagram of a preprocessing hardware platform plug-in box according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.
A possible system architecture to which the embodiment of the present application is applicable will be described first with reference to fig. 1.
Referring to fig. 1, a schematic diagram of a system to which an embodiment of the present application is applicable is shown. The system 100 may include
The schematic diagram of the preprocessing hardware platform architecture is shown in fig. 1, and a signal preprocessing hardware platform based on an OpenVPX bus is provided.
The hardware platform is constructed based on an OpenVPX bus architecture and takes an insertion box as a unit, and a general board card is used as a unit module in the insertion box;
high-throughput-oriented high-speed serial buses are adopted among all universal boards in the plug box to realize high-speed, wide-bandwidth and low-delay data transmission, 40G Ethernet or 10G Ethernet is adopted to exchange high-speed data, gigabit network is adopted as a control network, and I2C buses are adopted as health management networks; and optical fibers are adopted between the plug boxes and between the cabinets to carry out high-speed, wide-bandwidth and low-delay data transmission, and high-speed data exchange is carried out through 100G Ethernet or 40G Ethernet.
The signal connection schematic diagram of the preprocessing hardware platform jack backboard is shown in fig. 2, and the schematic diagram of the preprocessing hardware platform jack is shown in fig. 3.
The universal board card comprises: the system comprises a preprocessing board, a network exchange board and an interface control board.
The pretreatment board is used for processing the wide-bandwidth low-delay signals, receiving and transmitting high-speed backboard data and receiving and transmitting optical fiber data.
The network switching board is used for performing 100G Ethernet data switching, 40G Ethernet data switching, 10G Ethernet data switching and gigabit Ethernet data switching, high-speed data switching and control network.
The interface control board completes the functions of synchronous clock generation and distribution, external interface, combination control, health management and optical fiber data receiving and sending.
The preprocessing hardware platform plug-in box backboard adopts an OpenVPX bus single-star topological structure and is used for carrying the preprocessing board, the network switching board and the interface control board.
Preferably, the backboard adopts a 6U-size 10-slot structure, accords with BKP6-CEN10-11.2.4-n standard of an OpenVPX bus single-star topological structure, and comprises 1 exchange slot position and 9 load slots.
Preferably, 1 network exchange board is arranged in the exchange slot, 8 pretreatment boards and 1 interface control board are arranged in the load slot.
Preferably, the preprocessing board adopts a 6U VPX structure and comprises 2 large-scale FPGAs (field programmable gate arrays) for performing wide-bandwidth low-delay signal processing, wherein each large-scale FPGA comprises more than 3000 hardware multipliers; the J0 connector is used for power transmission, health management bus, test bus and homologous clock receiving; the J1 connector is used for at least 1-path 4X40G Ethernet data exchange or 4-path 1X10G Ethernet data exchange; the J2 and J6 connectors are used for receiving and transmitting at least 48X optical fibers; the J3 and J5 connectors are used for receiving and transmitting a 32X high-speed serial bus; the J4 connector is used for gigabit Ethernet signal transceiving.
Preferably, the network switching board adopts a 6U VPX structure, and comprises an Ethernet switching chip and a plurality of connectors; the Ethernet exchange chip performs 100G Ethernet data exchange, 40G Ethernet data exchange, 10G Ethernet data exchange and gigabit Ethernet data exchange; the Ethernet exchange chip supports at least 96X high-speed data transceiving; the J0 connector is used for power transmission, health management bus and test bus; the network exchange board J1 connector is used for 80X Ethernet data exchange, and is respectively bound into a 4X40G Ethernet data exchange form, a 1X10G Ethernet data exchange form or a 1X gigabit Ethernet data exchange form; the network switch board J6 connector is used for at least 12X optical fiber transceiving and supports 1-path 10X 100G Ethernet data exchange or 3-path 4X40G Ethernet data exchange.
Preferably, the interface control board adopts a 6UVPX structure and comprises a CPU chip, an FPGA chip, a clock distribution chip and a plurality of connectors, wherein the CPU chip is used for controlling, the FPGA chip is used for partial interface functions, and the clock distribution chip is used for carrying out clock distribution; the J0 connector is used for power transmission, health management bus, test bus and homologous clock distribution; the interface control board J1 connector is used for at least 1 path of 4X40G Ethernet data exchange or 4 paths of 1X10G Ethernet data exchange; the interface control board J2 connector, the interface control board J3 connector and the interface control board J5 connector support at least 16X high-speed serial bus transceiving and 8X PCIE buses; the interface control board J6 connector is used for receiving and transmitting at least 12X optical fibers; the interface control board J4 connector is used for gigabit Ethernet signal transceiving.
Preferably, at least 16X high-speed serial buses are connected between the adjacent preprocessing boards and the interface control boards to transmit and receive high-speed data, and the transmission bandwidth reaches 10Gbps; each preprocessing board and the interface control board are respectively connected with the network switching board through 1 path of 4X40G Ethernet to complete high-speed data exchange; each pretreatment board and the interface control board are respectively connected with the network exchange board through a 1-path 1X gigabit Ethernet, and the interface control board completes combination control through the gigabit Ethernet; the interface control board is connected with all the preprocessing boards through a J0MLVDS bus to finish synchronous clock distribution; the interface control board is connected with all the preprocessing boards through a J0I 2C bus to complete the health management function.
The application has the beneficial effects that: the number of the general board card modules is few and is only 3; the data transmission processing of the wide bandwidth, each preprocessing board supports the optical fiber transceiving bandwidth to be 480Gbps, and the data transceiving bandwidth between boards is at least 160Gbps; the wide bandwidth data exchange, each universal board card supports 40G Ethernet data exchange, and the plug-in boxes support 100G Ethernet data exchange; meets the standard specification of OpenVPX.
The foregoing embodiments have shown and described only the basic principles and main features of the application and the advantages of the application. It will be understood by those skilled in the art that the present application is not limited to the embodiments described above, and that the above embodiments and the knowledge described in the specification illustrate the principles of the present application, and that various changes and modifications may be made therein without departing from the spirit and scope of the application as claimed. The scope of the application is to be determined by the appended claims and their equivalents.
The embodiments of the present application described above do not limit the scope of the present application.
Claims (6)
1. A signal preprocessing hardware platform based on an OpenVPX bus, wherein the preprocessing hardware platform comprises:
the hardware platform is based on an OpenVPX bus architecture, an insertion box is used as a unit, and a universal board card is used as a unit module in the insertion box;
between all universal boards in the plug-in box, adopting 40G Ethernet or 10G Ethernet to exchange high-speed data, adopting gigabit network as control network, and I2C bus as health management network; and optical fibers are adopted for data transmission among the plug boxes and among the cabinets, and high-speed data exchange is carried out through 100G Ethernet or 40G Ethernet.
2. The OpenVPX bus-based signal preprocessing hardware platform according to claim 1, wherein: the universal board card comprises: the device comprises a pretreatment board, a network exchange board and an interface control board;
the pretreatment board is used for processing the wide-bandwidth low-delay signals, receiving and transmitting high-speed backboard data and receiving and transmitting optical fiber data;
the network switching board is used for performing 100G Ethernet data switching, 40G Ethernet data switching, 10G Ethernet data switching and gigabit Ethernet data switching, high-speed data switching and control network;
the interface control board completes the functions of synchronous clock generation and distribution, external interface, combination control, health management and optical fiber data receiving and sending.
3. The OpenVPX bus-based signal preprocessing hardware platform according to claim 2, wherein: the preprocessing hardware platform plug-in box backboard adopts an OpenVPX bus single star topological structure and is used for carrying a preprocessing board, a network switching board and an interface control board.
The plug box backboard adopts a 6U-size 10-slot structure, accords with BKP6-CEN10-11.2.4-n standard of an OpenVPX bus single-star topological structure, and comprises 1 exchange slot position and 9 load slots;
the 1 network exchange board is arranged in the exchange slot, and the 8 pretreatment boards and the 1 interface control board are arranged in the load slot.
Preferably, the preprocessing board adopts a 6U VPX structure and comprises 2 large-scale FPGAs (field programmable gate arrays) for performing wide-bandwidth low-delay signal processing, wherein each large-scale FPGA comprises more than 3000 hardware multipliers; the J0 connector is used for power transmission, health management bus, test bus and homologous clock receiving; the J1 connector is used for at least 1-path 4X40G Ethernet data exchange or 4-path 1X10G Ethernet data exchange; the J2 and J6 connectors are used for receiving and transmitting at least 48X optical fibers; the J3 and J5 connectors are used for receiving and transmitting a 32X high-speed serial bus; the J4 connector is used for gigabit Ethernet signal transceiving.
4. The OpenVPX bus-based signal preprocessing hardware platform according to claim 2, wherein: the network exchange board adopts a 6U VPX structure and comprises an Ethernet exchange chip and a plurality of connectors;
the Ethernet exchange chip performs 100G Ethernet data exchange, 40G Ethernet data exchange, 10G Ethernet data exchange and gigabit Ethernet data exchange; the Ethernet exchange chip supports at least 96X high-speed data transceiving; the J0 connector is used for power transmission, health management bus and test bus; the network exchange board J1 connector is used for 80X Ethernet data exchange, and is respectively bound into a 4X40G Ethernet data exchange form, a 1X10G Ethernet data exchange form or a 1X gigabit Ethernet data exchange form; the network switch board J6 connector is used for at least 12X optical fiber transceiving and supports 1-path 10X 100G Ethernet data exchange or 3-path 4X40G Ethernet data exchange.
5. The OpenVPX bus-based signal preprocessing hardware platform according to claim 2, wherein: the interface control board adopts a 6U VPX structure and comprises a CPU chip, an FPGA chip, a clock distribution chip and a plurality of connectors;
the CPU chip is used for control, the FPGA chip is used for partial interface function, and the clock distribution chip is used for clock distribution; the J0 connector is used for power transmission, health management bus, test bus and homologous clock distribution; the interface control board J1 connector is used for at least 1 path of 4X40G Ethernet data exchange or 4 paths of 1X10G Ethernet data exchange; the interface control board J2 connector, the interface control board J3 connector and the interface control board J5 connector support at least 16X high-speed serial bus transceiving and 8X PCIE buses; the interface control board J6 connector is used for receiving and transmitting at least 12X optical fibers; the interface control board J4 connector is used for gigabit Ethernet signal transceiving.
6. The OpenVPX bus-based signal preprocessing hardware platform according to claim 2, wherein: at least 16X high-speed serial bus is connected between the adjacent pretreatment boards and the interface control board to transmit and receive data at high speed, and the transmission bandwidth reaches 10Gbps; each preprocessing board and the interface control board are respectively connected with the network switching board through 1 path of 4X40G Ethernet to complete high-speed data exchange; each pretreatment board and the interface control board are respectively connected with the network exchange board through a 1-path 1X gigabit Ethernet, and the interface control board completes combination control through the gigabit Ethernet; the interface control board is connected with all the preprocessing boards through a J0MLVDS bus to finish synchronous clock distribution; the interface control board is connected with all the preprocessing boards through a J0I 2C bus to complete the health management function.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311095319.2A CN117221038A (en) | 2023-08-29 | 2023-08-29 | Signal preprocessing hardware platform based on OpenVPX bus |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311095319.2A CN117221038A (en) | 2023-08-29 | 2023-08-29 | Signal preprocessing hardware platform based on OpenVPX bus |
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| CN117221038A true CN117221038A (en) | 2023-12-12 |
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| CN202311095319.2A Pending CN117221038A (en) | 2023-08-29 | 2023-08-29 | Signal preprocessing hardware platform based on OpenVPX bus |
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