CN117219675B - A kind of LDMOS device structure and preparation method thereof - Google Patents

Abstract

The invention provides an LDMOS device structure and a preparation method thereof. A substrate layer, a buried oxide layer and a device layer are stacked sequentially from bottom to top along a first direction. The device layer includes a device region and a dielectric region; the dielectric region is distributed along the second direction. On both sides of the device area, the source area in the device area is set in the concave area of the channel area and exposed on the surface of the device area, and a body area connected through the source area and the channel area is set; the drain area is set in the drift area In the concave area and exposed on the surface of the device area, the gate area is located above the surface of the channel area and close to the source area; the dielectric area includes a dielectric layer, a field plate layer and a field plate control end, and the field plate layer is located along the second The direction is symmetrically arranged on both sides of the drift region near the drain region. The field plate control end covers the field plate layer and fills the gap formed by the field plate layer in the dielectric layer. The dielectric layer wraps both sides of the channel area. By arranging the field plate layer on the side of the device drift region, the present invention achieves high withstand voltage and low on-resistance while reducing the gate-drain parasitic capacitance.

Description

A kind of LDMOS device structure and preparation method thereof

Technical field

The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to an LDMOS device structure and a preparation method thereof.

Background technique

LDMOS (Laterally Diffused Metal Oxide Semiconductor, laterally diffused metal oxide semiconductor) devices have been widely used and researched in BCD (Bipolar CMOS DMOS, monolithic integration process).

In order to modulate the uniform electric field distribution in the drift region in the LDMOS device and improve the performance of breakdown voltage and source-drain withstand voltage, in the LDMOS device structure between 12V and 40V regions, the design of setting up a field plate layer in the drift region is widely used. Currently, maturely applied LDMOS devices adopt the following structure: the field plate is laid flat on top of the device layer. For different withstand voltage requirements, the usual approach is to adjust the following dimensions: 1. Channel length a; 2. Overlapping distance between the field plate and the polysilicon gate b; 3. Extension distance of the field plate c. For example, for 16V LDMOS, the industry usually sets the size of a to be around 0.5 microns, the size of b to be around 0.7 microns, and the size of c to be around 0.8 microns.

However, as the source-drain withstand voltage requirements increase, the distances and sizes of the above a, b, and c cannot be increased infinitely. Therefore, the improvement of the withstand voltage is limited, and it is not in line with the current development trend of miniaturized devices. In addition, simply increasing the above distance will lead to a corresponding linear increase in the on-resistance between the source and drain, increasing the power consumption of the device, which is not conducive to the realization of low-power devices.

The field plate technologies currently widely used in integrated circuit manufacturing processes include mini-STI (shallow trench isolation) field plates, mini-LOCOS (Local Oxidation of Silicon, local oxidation of silicon) field plates and HTO (High Temperature Oxidation, high temperature oxidation). ) Field plates, these structures make the electric field uniformly distributed throughout the drift region, reduce the surface peak electric field, increase the lateral electric field in the middle of the drift region, and increase the breakdown voltage of the device. However, these structures require polysilicon to be placed between the low-voltage gate oxide layer and the high-voltage field plate oxide layer at the same time. Therefore, a high parasitic capacitance will be formed between the drain terminal and the gate terminal, resulting in low device switching efficiency and low specific conductance. The resistance increases.

Therefore, it is urgent to design an LDMOS that can improve the source-drain withstand voltage while maintaining a low source-drain on-resistance.

It should be noted that the above introduction to the technical background is only to facilitate a clear and complete description of the technical solutions of the present application and to facilitate the understanding of those skilled in the art. It cannot be explained simply because these solutions are described in the background technology section of the present application. Based on the description, it is believed that the above technical solutions are well known to those skilled in the art.

Contents of the invention

In view of the above shortcomings of the prior art, the purpose of the present invention is to provide an LDMOS device structure and a preparation method thereof to solve the problem in the prior art that LDMOS cannot maintain low on-resistance while maintaining high withstand voltage.

In order to achieve the above object, the present invention provides an LDMOS device structure, which includes: a substrate layer, a buried oxide layer and a device layer;

The substrate layer, the buried oxide layer and the device layer are stacked sequentially from bottom to top along the first direction, the buried oxide layer is located on the substrate layer, and the device layer is located on the buried oxide layer, The first direction is perpendicular to the substrate layer;

The device layer includes a device region and a dielectric region; the dielectric region is distributed on both sides of the device region along a second direction, and the second direction is parallel to the substrate layer;

The device region includes a source region of the first conductivity type, a body region of the second conductivity type, a channel region of the second conductivity type, a gate region, a drift region of the first conductivity type and a drain of the first conductivity type. region; the channel region is concave, the source region is disposed in the concave region of the channel region and is exposed on the surface of the device region, and the body region is disposed in the source region, The body region penetrates the source region and is connected to the channel region to lead the channel region to the surface of the device region; the drift region is concave, and the drain region is disposed on the within the concave area of the drift region and exposed on the surface of the device region; the drift region and the channel region are adjacently distributed along a third direction, and the third direction is perpendicular to the first direction and the third direction. In both directions, the top surfaces of the source region and the drain region are aligned and have the same thickness; the gate region is located above the surface of the channel region and close to the source region;

The dielectric area includes a dielectric layer, a field plate layer and a field plate control end; the dielectric layer is symmetrically arranged along the second direction on both sides of the device area close to the channel area and wraps the channel on both sides of the region; the field plate layer is symmetrically arranged on both sides of the drift region close to the drain region along the second direction; the field plate control end covers the field plate layer and is not connected to the The surface of the drift area contacts and fills the gap formed by the field plate layer in the dielectric area, so that the field plate control end and the field plate layer form a field plate structure, located on either side of the device area. The cross-sections of the field plate structures parallel to the substrate layer are all rectangular, and the field plate control terminal is used to apply voltage to the field plate layer.

Optionally, the field plate layer located on either side of the device region approaches from a position away from the device region along a section parallel to the substrate layer and along a length parallel to the third direction. The position of the device area is incremented.

Optionally, the field plate layer located on either side of the device region has a cross-sectional shape parallel to the substrate layer that is triangular, bell-shaped, parabolic, semi-elliptical or semi-circular; or is located on The cross-sectional shape of the field plate layer on either side of the device area parallel to the substrate layer is a triangle, a bell shape, a parabola shape, and a bottom section cut off by a line parallel to the third direction. Semi-oval or semi-circular.

Optionally, the field plate layer located on either side of the device region has a symmetrical shape along a cross-sectional shape parallel to the substrate layer, and the symmetry axis of the cross-sectional shape is parallel to the second direction.

Optionally, the field plate layer located on either side of the device region has a cross-sectional shape parallel to the substrate layer, which is a triangle or a triangle whose bottom is cut off by a section line parallel to the third direction. When the field plate layer is in contact with the field plate control end, the angle between the two side walls and the third direction is less than 30°.

Optionally, the length of the rectangular cross section of the field plate structure located on either side of the device area and parallel to the substrate layer along the third direction is 1 micrometer to 3 micrometer.

Optionally, the cross-sectional shape of the field plate layer located on either side of the device area parallel to the substrate layer is a plurality of triangles, bell shapes, parabolas, semi-ellipses, and semi-circles. Or a triangle, bell shape, parabola, semi-ellipse, semicircle whose bottom is cut off by a section line parallel to the third direction, a zigzag shape or a wave shape formed by repeated tiling along the third direction.

Optionally, the field plate layer has the same thickness as the drift region along the first direction, and a top surface of the field plate layer is flush with a top surface of the drift region.

Optionally, the length of the side of the field plate layer located on either side of the device region that is in contact with the drift region is 0.15 microns to 0.3 microns along the second direction, and the length of the device region along the The length of the second direction is 0.6 microns to 0.8 microns.

The present invention also provides a method for preparing an LDMOS device structure. The preparation method is used to prepare any of the above-mentioned LDMOS device structures. The preparation method includes:

Provide a substrate layer, and provide a buried oxide layer above the substrate layer along a first direction, the first direction being perpendicular to the substrate layer;

A device region is provided above the buried oxide layer along a first direction, and dielectric regions are provided on both sides of the device region along a second direction. The second direction is parallel to the substrate layer, and the dielectric region and the The device area constitutes the device layer;

A trench of a predetermined shape is provided in the dielectric region close to the predetermined drain region to form a field plate layer. The trench penetrates the dielectric region and one side of the field plate layer is in contact with the device region. , filling the trench with polysilicon material to form a field plate control end, the field plate control end and the field plate layer forming a field plate structure;

disposing a gate region above the device layer along the first direction;

The device region is doped to obtain a channel region of the second conductivity type and a drift region of the first conductivity type adjacently arranged along the third direction, and a source of the first conductivity type on the surface of the channel region. region, a drain region of the first conductivity type on the surface of the drift region, and a body region of the second conductivity type connected to the channel region through the source region, and the channel region is close to the gate area, the drift area is in contact with the field plate layer, and the dielectric area close to the channel area is a dielectric layer.

As above, the LDMOS device structure and preparation method of the present invention have the following beneficial effects:

By arranging the field plate layer on the side of the device drift region, the present invention achieves high withstand voltage and low on-resistance while reducing the gate-drain parasitic capacitance.

Description of the drawings

FIG. 1 shows a schematic top view of the LDMOS device structure in Embodiment 1 of the present invention.

FIG. 2 shows a schematic side cross-sectional view of the LDMOS device structure in the device area in Embodiment 1 of the present invention.

FIG. 3 shows a schematic side cross-sectional view of the LDMOS device structure in the dielectric region in Embodiment 1 of the present invention.

Component label description

100. Substrate layer; 200. Buried oxide layer;

310. Device region; 311. Source region; 312. Body region; 313. Channel region; 314. Gate region; 315. Drift region; 316. Drain region;

321. Dielectric layer; 322. Field plate structure; 3221. Field plate layer; 3222. Field plate control end.

Detailed ways

The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

When describing the embodiments of the present invention in detail, for convenience of explanation, the schematic diagram showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which shall not limit the scope of protection of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual production.

For convenience of description, spatial relationship words such as "below", "below", "below", "below", "above", "on", etc. may be used herein to describe an element or element shown in the drawings. The relationship of a feature to other components or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientations depicted in the figures.

In the context of this application, structures described as having a first feature "on" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features. Embodiments between two features such that the first and second features may not be in direct contact.

It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the illustrations only show the components related to the present invention and are not based on the number, shape and number of components during actual implementation. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be arbitrarily changed, and the component layout type may also be more complex.

Embodiment 1

As shown in Figures 1-3, the present invention provides an LDMOS device structure, wherein Figure 1 is a top view of the LDMOS device structure, Figure 2 is a side cross-sectional view of the LDMOS device structure in the device area, Figure 3 This is a side cross-sectional view of the LDMOS device structure taken in the dielectric region. The LDMOS device structure includes: a substrate layer 100, a buried oxide layer 200 and a device layer;

The substrate layer 100, the buried oxide layer 200 and the device layer are stacked sequentially from bottom to top along the first direction. The buried oxide layer 200 is located on the substrate layer 100, and the device layer is located on the buried oxide layer 100. On the oxygen layer 200, the first direction is perpendicular to the substrate layer 100;

The device layer includes a device region 310 and a dielectric region; the dielectric region is distributed on both sides of the device region 310 along a second direction, and the second direction is parallel to the substrate layer 100;

As shown in FIG. 2 , the device region 310 includes a first conductivity type source region 311 , a second conductivity type body region 312 , a second conductivity type channel region 313 , a gate region 314 , and a first conductivity type body region 312 . The drift region 315 and the drain region 316 of the first conductivity type; the channel region 313 is concave, and the source region 311 is disposed in the concave region of the channel region 313 and exposed to the device On the surface of the region 310, the body region 312 is provided in the source region 311. The body region 312 penetrates the source region 311 and is connected to the channel region 313 to lead the channel region 313 to the The surface of the device region 310; the drift region 315 is concave, and the drain region 316 is disposed in the concave region of the drift region 315 and exposed on the surface of the device region 310; the drift region 315 Distributed adjacent to the channel region 313 along a third direction perpendicular to the first direction and the second direction, the tops of the source region 311 and the drain region 316 face each other. Align and equal in thickness; the gate region 314 is located above the surface of the channel region 313 and close to the source region 311;

As shown in Figure 3, the dielectric area includes a dielectric layer 321, a field plate layer 3221 and a field plate control end 3222; the dielectric layer 321 is symmetrically arranged along the second direction on both sides of the device area 310 and close to the The position of the channel region 313 and wraps both sides of the channel region 313; the field plate layer 3221 is symmetrically arranged along the second direction at a position close to the drain region 316 on both sides of the drift region 315; The field plate control end 3222 covers the surface of the field plate layer 3221 that is not in contact with the drift area 315 and fills the gap formed by the field plate layer 3221 in the dielectric area, so that the field plate control end 3222 The field plate structure 322 is formed with the field plate layer 3221. The field plate structure 322 located on either side of the device area 310 has a rectangular cross section parallel to the substrate layer 100. The field plate control The terminal 3222 is used to apply voltage to the field plate layer 3221.

The field plate in the prior art is generally disposed inside the drift region 315 to make the electric field uniform, but it is easy to generate parasitic capacitance between the gate and the drain. At the same time, while increasing the breakdown voltage, the on-resistance will increase, making it impossible to achieve The simultaneous improvement of breakdown voltage and on-resistance limits performance improvement. By arranging the field plate structure 322 on both sides of the drift region 315, the present invention improves the spatial distribution flexibility of the field plate structure 322 in regulating the electric field in the drift region 315, and can form a very smooth electric field intensity distribution; at the same time, by placing the field plate structure 322 is set outside the device area 310 to avoid increasing the source-drain withstand voltage while causing a linear increase in the source-drain resistance, and can also reduce the specific on-resistance. When the source-drain withstand voltage reaches 300V-500V, the specific on-resistance is 40mΩ.mm. ² or less; in addition, through the distribution of the field plate structure 322 on both sides of the drift region 315, the gate-to-drain parasitic capacitance formed between the introduction and the gate is avoided, thereby improving the switching efficiency of the device.

In one embodiment, the field plate layer 3221 is made of a dielectric layer 321 . Preferably, the material of the field plate layer 3221 is oxide.

In one embodiment, as shown in FIG. 1 , the field plate layer 3221 located on either side of the device region 310 takes a cross-section parallel to the substrate layer 100 and along a cross-section parallel to the third direction. The length increases from a position away from the device region 310 to a position close to the device region 310 .

By arranging the length of the field plate layer 3221 to change uniformly in the third direction, the present invention makes the electric field distribution at the drain end more uniform and further reduces the on-resistance while maintaining the improvement in withstand voltage.

In one embodiment, the field plate layer 3221 located on either side of the device region 310 has a cross-sectional shape parallel to the substrate layer 100 that is triangular, bell-shaped, parabolic, semi-elliptical or semi-elliptical. Circular; or the cross-sectional shape of the field plate layer 3221 located on either side of the device region 310 along the cross-sectional shape parallel to the substrate layer 100 is the bottom cut off by a section line parallel to the third direction. A triangle, bell shape, parabola, semi-ellipse or semi-circle, as shown in Figures 1 and 3, is a triangle whose bottom is cut off by a section line parallel to the third direction, that is, a trapezoid.

In one embodiment, the field plate layer 3221 located on either side of the device region 310 has a symmetrical shape along a cross-sectional shape parallel to the substrate layer 100 , and the symmetry axis of the cross-sectional shape is consistent with the The second direction is parallel.

By setting the field plate layer 3221 to have a symmetrical pattern, the present invention further improves the uniform adjustment of the electric field distribution in the drift region 315 by the field plate layer 3221.

In one embodiment, the field plate layer 3221 located on either side of the device region 310 has a triangular cross-sectional shape parallel to the substrate layer 100 or has a bottom section parallel to the third direction. When a triangle is cut by a line, the angle between the two side walls in contact with the field plate control end 3222 of the field plate layer 3221 and the third direction is less than 30°.

In one embodiment, the length of the rectangular cross section of the field plate structure 322 located on either side of the device region 310 and parallel to the substrate layer 100 along the third direction is 1 micrometer to 3 micrometer.

In one embodiment, a length of the field plate layer 3221 parallel to the third direction at a position contacting the drift region 315 is equal to a length of the field plate structure 322 parallel to the third direction.

Specifically, the length of the field plate layer 3221 along the third direction is related to the source-drain withstand voltage value that needs to be achieved, and needs to be adjusted according to specific parameter requirements.

In one embodiment, the field plate layer 3221 and the field plate control end 3222 have the same thickness in the first direction.

In one embodiment, the lengths of the field plate layer 3221 and the field plate control end 3222 in the second direction are equal.

By setting the field plate control terminal 3222 to exactly cover the surface of the field plate layer 3221, the present invention improves the voltage control of the field plate layer 3221 by the field plate control terminal 3222, thereby achieving more precise and sensitive adjustment of the electric field intensity distribution in the drift region 315.

In one embodiment, the cross-sectional shape of the field plate layer 3221 located on either side of the device region 310 parallel to the substrate layer 100 is a plurality of triangles, bell shapes, parabolas, or semi-ellipses. A shape, a semicircle or a triangle with the bottom cut off by a line parallel to the third direction, a bell shape, a parabola, a semi-oval, a zigzag shape formed by repeated tiling of a semicircle along the third direction, or Wavy.

In one embodiment, the field plate layer 3221 has the same thickness as the drift region 315 along the first direction, and the top surface of the field plate layer 3221 is flush with the top surface of the drift region 315 .

In one embodiment, the length of the side of the field plate layer 3221 located on either side of the device region 310 that contacts the drift region 315 along the second direction is 0.15 microns to 0.3 microns, so The length of the device region 310 along the second direction is 0.6 microns to 0.8 microns.

Specifically, the length of the device region 310 along the second direction is the distance between the field plate layers 3221 on both sides. This distance is related to the source-drain withstand voltage value that needs to be achieved, and needs to be matched with other parameters of the field plate layer 3221 Make adjustments.

In one embodiment, the thickness of the device layer in the first direction is 1500 angstroms - 4000 angstroms.

In one embodiment, the thickness of the buried oxide layer 200 in the first direction is 500 angstroms to 1500 angstroms.

In one embodiment, the length of the gate region 314 along the third direction is 0.5 microns to 0.6 microns.

In one embodiment, the gate region 314 includes a gate oxide layer and a polysilicon layer, the gate oxide layer is in contact with the upper surface of the device layer, and the polysilicon layer is located on the gate oxide layer.

In one embodiment, the thickness of the gate oxide layer in the first direction is 120 angstroms - 140 angstroms, and the thickness of the polysilicon layer in the first direction is 1000 angstroms - 2500 angstroms.

Embodiment 2

The present invention also provides a method for preparing an LDMOS device structure. The preparation method is used to prepare the LDMOS device structure described in any one of the above embodiments. The preparation method includes:

Step 1: Provide a substrate layer 100, and provide a buried oxide layer 200 above the substrate layer 100 along a first direction, the first direction being perpendicular to the substrate layer 100;

Step 2: Set up a device layer above the buried oxide layer 200 along the first direction, and set up dielectric layers 321 on both sides of the device layer along the second direction. The second direction is parallel to the substrate layer 100. The dielectric area and the device area 310 constitute a device layer;

Step 3: Set a trench of a predetermined shape in the dielectric region close to the predetermined drain region 316 to form a field plate layer 3221. The trench penetrates the dielectric region and is on one side of the field plate layer 3221. In contact with the device area 310, polysilicon material is filled in the trench to form a field plate control terminal 3222. The field plate control terminal 3222 and the field plate layer 3221 form a field plate structure 322;

Step 4: Set a gate region 314 above the device layer along the first direction;

Step 5: Dope the device region 310 to obtain a channel region 313 of the second conductivity type and a drift region 315 of the first conductivity type adjacently arranged along the third direction. The source region 311 of the first conductivity type, the drain region 316 of the first conductivity type on the surface of the drift region 315 and the body of the second conductivity type connected to the channel region 313 through the source region 311 Region 312, the channel region 313 is close to the gate region 314, the drift region 315 is in contact with the field plate layer 3221, and the dielectric region close to the channel region 313 is the dielectric layer 321.

The preparation method of the LDMOS device structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the preparation method of the LDMOS device structure protected by the present invention. Those skilled in the art can make reference to the actual Preparation steps were changed.

First, step 1 is performed to provide a substrate layer 100 , and a buried oxide layer 200 is provided above the substrate layer 100 along a first direction, and the first direction is perpendicular to the substrate layer 100 .

Then, step 2 is performed, in which a device layer is disposed above the buried oxide layer 200 along the first direction, and dielectric layers 321 are disposed on both sides of the device layer along the second direction. The second direction is parallel to the liner. The bottom layer 100, the dielectric area and the device area 310 constitute a device layer.

Next, step 3 is performed to set a trench of a predetermined shape in the dielectric region close to the predetermined drain region 316 to form a field plate layer 3221. The trench penetrates the dielectric region and the field plate layer 3221 One side of the trench is in contact with the device region 310 , and polysilicon material is filled in the trench to form a field plate control terminal 3222 . The field plate control terminal 3222 and the field plate layer 3221 form a field plate structure 322 .

Then, step 4 is performed to set a gate region 314 above the device layer along the first direction.

Finally, step 5 is performed to dope the device region 310 to obtain a channel region 313 of the second conductivity type and a drift region 315 of the first conductivity type adjacently arranged along the third direction. In the channel region The source region 311 of the first conductivity type on the surface of the drift region 313, the drain region 316 of the first conductivity type on the surface of the drift region 315, and the second conductivity region 311 connected to the channel region 313 through the source region 311. type body region 312, the channel region 313 is close to the gate region 314, the drift region 315 is in contact with the field plate layer 3221, and the dielectric region close to the channel region 313 is the dielectric layer 321.

By arranging the field plate layer 3221 on both sides of the drift region 315, the present invention can achieve the performance of improving the withstand voltage while reducing the on-resistance by using a simple process without making significant adjustments to the original process. .

In summary, the LDMOS device structure and its preparation method of the present invention can achieve high withstand voltage and low on-resistance while reducing the gate-to-drain parasitic capacitance by arranging the field plate layer on the side of the device drift region.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (10)

1. An LDMOS device structure, the LDMOS device structure comprising: a substrate layer, a buried oxide layer and a device layer;

the substrate layer, the oxygen-buried layer and the device layer are sequentially stacked from bottom to top along a first direction, the oxygen-buried layer is positioned on the substrate layer, the device layer is positioned on the oxygen-buried layer, and the first direction is perpendicular to the substrate layer;

the device layer comprises a device region and a medium region; the dielectric regions are distributed on two sides of the device region along a second direction, and the second direction is parallel to the substrate layer;

the device region comprises a source region of a first conductivity type, a body region of a second conductivity type, a channel region of the second conductivity type, a gate region, a drift region of the first conductivity type and a drain region of the first conductivity type; the source region is arranged in the concave region of the channel region and exposed on the surface of the device region, the body region is arranged in the source region, and the body region penetrates through the source region and is connected with the channel region so as to lead out the channel region to the surface of the device region; the drift region is concave, and the drain region is arranged in the concave region of the drift region and is exposed on the surface of the device region; the drift regions and the channel regions are adjacently distributed along a third direction, the third direction is perpendicular to the first direction and the second direction, and the top surfaces of the source region and the drain region are aligned and have equal thickness; the gate region is located above the surface of the channel region near the source region;

the dielectric region comprises a dielectric layer, a field plate layer and a field plate control end; the dielectric layers are symmetrically arranged at positions, close to the channel region, on two sides of the device region along the second direction and wrap two sides of the channel region; the field plate layers are symmetrically arranged at positions, close to the drain electrode region, on two sides of the drift region along the second direction; the field plate control end covers the surface of the field plate layer which is not contacted with the drift region and fills a gap formed in the dielectric region by the field plate layer, so that the field plate control end and the field plate layer form a field plate structure, the section of the field plate structure, which is parallel to the substrate layer, of any one of two sides of the device region is rectangular, and the field plate control end is used for applying voltage to the field plate layer; the length of the field plate layer in the position of contacting the drift region, which is parallel to the third direction, is equal to the length of the field plate structure in the third direction, and the thickness of the field plate layer is equal to the thickness of the field plate control end in the first direction.

2. The LDMOS device structure of claim 1, wherein the field plate layer on either side of the device region increases in length along a cross-section parallel to the substrate layer along a direction parallel to the third direction from a position away from the device region to a position closer to the device region.

3. The LDMOS device structure of claim 2, wherein the field plate layer on either side of the device region is triangular, bell-shaped, parabolic, semi-elliptical, or semi-circular in cross-sectional shape parallel to the substrate layer; or the field plate layer located on either side of the device region has a triangular, bell-shaped, parabolic, semi-elliptical or semicircular cross-sectional shape parallel to the substrate layer with a bottom truncated by a cross-section line parallel to the third direction.

4. The LDMOS device structure of claim 3, wherein the field plate layer on either side of the device region is symmetrically patterned along a cross-sectional shape parallel to the substrate layer, the axis of symmetry of the cross-sectional shape being parallel to the second direction.

5. The LDMOS device structure of claim 3, wherein the field plate layer on either side of the device region has a triangular cross-sectional shape parallel to the substrate layer or a triangular shape with a bottom truncated by a cross-sectional line parallel to the third direction, wherein an angle between both sidewalls of the field plate layer in contact with the field plate control terminal and the third direction is less than 30 °.

6. The LDMOS device structure of claim 1, wherein the field plate structure on either side of the device region has a length of 1 micron to 3 microns in the third direction parallel to the rectangular cross-section of the substrate layer.

7. The LDMOS device structure of claim 1, wherein the field plate layer on either side of the device region has a cross-sectional shape parallel to the substrate layer of a plurality of triangles, bells, parabolas, semi-ellipses, semi-circles or triangles with bottoms truncated by a cross-sectional line parallel to the third direction, bells, parabolas, semi-ellipses, semi-circles repeatedly tiled along the third direction to form a zigzag or wave.

8. The LDMOS device structure of claim 1, wherein the thickness of the field plate layer is the same as the thickness of the drift region in the first direction, and wherein a top surface of the field plate layer is flush with a top surface of the drift region.

9. The LDMOS device structure of claim 1, wherein a length of a side of the field plate layer located on either side of the device region in contact with the drift region along the second direction is 0.15-0.3 microns, and a length of the device region along the second direction is 0.6-0.8 microns.

10. A method for manufacturing an LDMOS device structure according to any of claims 1-9, characterized in that the method is used for manufacturing an LDMOS device structure, the method comprising:

providing a substrate layer, and arranging an oxygen buried layer above the substrate layer along a first direction, wherein the first direction is perpendicular to the substrate layer;

a device region is arranged above the oxygen-buried layer along a first direction, medium regions are arranged on two sides of the device region along a second direction, the second direction is parallel to the substrate layer, and the medium regions and the device region form a device layer;

a groove with a preset shape is arranged at the position, close to the preset drain electrode region, of the medium region to form a field plate layer, the groove penetrates through the medium region, one side of the field plate layer is in contact with the device region, polysilicon materials are filled in the groove to form a field plate control end, and the field plate control end and the field plate layer form a field plate structure;

a grid electrode region is arranged above the device layer along the first direction;

doping the device region to obtain a channel region of a second conductivity type and a drift region of a first conductivity type, which are adjacently arranged along a third direction, a source region of the first conductivity type on the surface of the channel region, a drain region of the first conductivity type on the surface of the drift region, and a body region of the second conductivity type, which penetrates through the source region and is connected with the channel region, wherein the channel region is close to the gate region, the drift region is in contact with the field plate layer, and a dielectric region close to the channel region is a dielectric layer.