CN117219675B - LDMOS device structure and preparation method thereof - Google Patents
LDMOS device structure and preparation method thereof Download PDFInfo
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
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Abstract
The invention provides an LDMOS device structure and a preparation method thereof.A substrate layer, an oxygen-buried layer and a device layer are sequentially stacked from bottom to top along a first direction, and the device layer comprises a device region and a medium region; the medium regions are distributed on two sides of the device region along the second direction, the source region in the device region is arranged in the concave region of the channel region and exposed on the surface of the device region, and a body region penetrating through the source region and connected with the channel region is arranged; the drain electrode region is arranged in the concave region of the drift region and exposed on the surface of the device region, and the gate electrode region is positioned above the surface of the channel region and close to the source electrode region; the dielectric region comprises a dielectric layer, field plate layers and field plate control ends, the field plate layers are symmetrically arranged at positions, close to the drain electrode regions, on two sides of the drift region along the second direction, the field plate control ends cover the field plate layers and fill gaps formed in the dielectric layer by the field plate layers, and the dielectric layer wraps two sides of the channel region. According to the invention, the field plate layer is arranged on the side surface of the drift region of the device, so that high withstand voltage and low on-resistance are realized, and meanwhile, the parasitic capacitance of the gate drain is reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to an LDMOS device structure and a preparation method thereof.
Background
LDMOS (Laterally Diffused Metal Oxide Semiconductor ) devices have been widely used and studied in BCD (Bipolar CMOS DMOS, monolithic integrated process).
In order to modulate the electric field distribution of a drift region in an LDMOS device uniformly and improve the breakdown voltage and the source-drain voltage resistance, the design of arranging a field plate layer in the drift region is widely applied in an LDMOS device structure between 12V and 40V regions. The LDMOS devices which are mature at present adopt the following structures: the field plate is laid flat over the device layer. For different withstand voltage requirements, it is common practice to adjust the following dimensions: 1. channel length a;2. overlapping distance b between the field plate and the polysilicon gate; 3. the extension distance c of the field plate. For example, a 16V LDMOS, typically has a size of about 0.5 microns for a, about 0.7 microns for b, and about 0.8 microns for c.
However, with the increase of the requirements of source-drain voltage resistance, the distances and the sizes of a, b and c cannot be infinitely increased, so that the increase of the voltage resistance is limited and the current trend of miniaturized devices is not met. In addition, only the distance is increased, so that the on-resistance between the source and the drain is correspondingly increased linearly, the power consumption of the device is increased, and the realization of the low-power consumption device is not facilitated.
The field plate technology widely adopted in the integrated circuit manufacturing process at present comprises a mini-STI (shallow trench isolation) field plate, a mini-LOCOS (Local Oxidation of Silicon ) field plate and an HTO (High Temperature Oxidation, high-temperature oxidation) field plate, and the structures enable the electric field of the whole drift region to be uniformly distributed, reduce the surface peak electric field, improve the transverse electric field in the middle of the drift region and improve the breakdown voltage of the device. However, these structures require polysilicon to be simultaneously sandwiched between a low voltage gate oxide and a high voltage field plate oxide, thus creating a high parasitic capacitance between the drain and gate terminals, resulting in low device switching efficiency and higher specific on-resistance.
Therefore, it is desirable to design an LDMOS that can improve the source-drain withstand voltage while maintaining a low on-resistance.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art, and is not to be construed as merely illustrative of the background art section of the present application.
Disclosure of Invention
In view of the above drawbacks of the prior art, an objective of the present invention is to provide an LDMOS device structure and a method for manufacturing the same, which are used for solving the problem that the LDMOS device in the prior art cannot maintain low on-resistance while having high withstand voltage.
To achieve the above object, the present invention provides an LDMOS device structure, which includes: a substrate layer, a buried oxide layer and a device layer;
the substrate layer, the oxygen-buried layer and the device layer are sequentially stacked from bottom to top along a first direction, the oxygen-buried layer is positioned on the substrate layer, the device layer is positioned on the oxygen-buried layer, and the first direction is perpendicular to the substrate layer;
the device layer comprises a device region and a medium region; the dielectric regions are distributed on two sides of the device region along a second direction, and the second direction is parallel to the substrate layer;
the device region comprises a source region of a first conductivity type, a body region of a second conductivity type, a channel region of the second conductivity type, a gate region, a drift region of the first conductivity type and a drain region of the first conductivity type; the source region is arranged in the concave region of the channel region and exposed on the surface of the device region, the body region is arranged in the source region, and the body region penetrates through the source region and is connected with the channel region so as to lead out the channel region to the surface of the device region; the drift region is concave, and the drain region is arranged in the concave region of the drift region and is exposed on the surface of the device region; the drift regions and the channel regions are adjacently distributed along a third direction, the third direction is perpendicular to the first direction and the second direction, and the top surfaces of the source region and the drain region are aligned and have equal thickness; the gate region is located above the surface of the channel region near the source region;
the dielectric region comprises a dielectric layer, a field plate layer and a field plate control end; the dielectric layers are symmetrically arranged at positions, close to the channel region, on two sides of the device region along the second direction and wrap two sides of the channel region; the field plate layers are symmetrically arranged at positions, close to the drain electrode region, on two sides of the drift region along the second direction; the field plate control end covers the surface of the field plate layer which is not contacted with the drift region and fills a gap formed in the medium region by the field plate layer, so that the field plate control end and the field plate layer form a field plate structure, the section of the field plate structure, which is parallel to the substrate layer, of any one of two sides of the device region is rectangular, and the field plate control end is used for applying voltage to the field plate layer.
Optionally, the field plate layer located on either side of the device region increases in length along a section parallel to the substrate layer along a direction parallel to the third direction from a position away from the device region to a position close to the device region.
Optionally, the field plate layer located on either side of the device region has a triangular, bell-shaped, parabolic, semi-elliptical or semicircular cross-sectional shape along a direction parallel to the substrate layer; or the field plate layer located on either side of the device region has a triangular, bell-shaped, parabolic, semi-elliptical or semicircular cross-sectional shape parallel to the substrate layer with a bottom truncated by a cross-section line parallel to the third direction.
Optionally, the field plate layer located on any one of two sides of the device region is in a symmetrical pattern along a cross-sectional shape parallel to the substrate layer, and a symmetry axis of the cross-sectional shape is parallel to the second direction.
Optionally, when the cross-sectional shape of the field plate layer on any one of two sides of the device region along a direction parallel to the substrate layer is triangular or a triangle with the bottom cut by a section line parallel to the third direction, an included angle between two side walls of the field plate layer, which are in contact with the field plate control end, and the third direction is smaller than 30 °.
Optionally, the length of the rectangular cross section of the field plate structure located on either side of the device region parallel to the substrate layer along the third direction is 1 micron to 3 microns.
Optionally, the cross-sectional shape of the field plate layer on any one of two sides of the device region along a direction parallel to the substrate layer is a triangle, a bell, a parabola, a semi-ellipse, a semicircle or a triangle, a bell, a parabola, a semi-ellipse, a semicircle with a bottom truncated by a cross-section line parallel to the third direction, and the zigzag or the wave is formed by repeatedly tiling the field plate layer along the third direction.
Optionally, the thickness of the field plate layer is the same as the thickness of the drift region along the first direction, and the top surface of the field plate layer is flush with the top surface of the drift region.
Optionally, a length of a surface, in the second direction, of the field plate layer located on any one of two sides of the device region, where the surface is in contact with the drift region is 0.15 micrometers to 0.3 micrometers, and a length of the device region in the second direction is 0.6 micrometers to 0.8 micrometers.
The invention also provides a preparation method of the LDMOS device structure, which is used for preparing any one of the LDMOS device structures, and comprises the following steps:
providing a substrate layer, and arranging an oxygen buried layer above the substrate layer along a first direction, wherein the first direction is perpendicular to the substrate layer;
a device region is arranged above the oxygen-buried layer along a first direction, medium regions are arranged on two sides of the device region along a second direction, the second direction is parallel to the substrate layer, and the medium regions and the device region form a device layer;
a groove with a preset shape is arranged at the position, close to the preset drain electrode region, of the medium region to form a field plate layer, the groove penetrates through the medium region, one side of the field plate layer is in contact with the device region, polysilicon materials are filled in the groove to form a field plate control end, and the field plate control end and the field plate layer form a field plate structure;
a grid electrode region is arranged above the device layer along the first direction;
doping the device region to obtain a channel region of a second conductivity type and a drift region of a first conductivity type, which are adjacently arranged along a third direction, a source region of the first conductivity type on the surface of the channel region, a drain region of the first conductivity type on the surface of the drift region, and a body region of the second conductivity type, which penetrates through the source region and is connected with the channel region, wherein the channel region is close to the gate region, the drift region is in contact with the field plate layer, and a dielectric region close to the channel region is a dielectric layer.
As described above, the LDMOS device structure and the method for manufacturing the same of the present invention have the following beneficial effects:
according to the invention, the field plate layer is arranged on the side surface of the drift region of the device, so that high withstand voltage and low on-resistance are realized, and meanwhile, the parasitic capacitance of the gate drain is reduced.
Drawings
Fig. 1 is a schematic top view of an LDMOS device according to a first embodiment of the invention.
Fig. 2 is a schematic side cross-sectional view of an LDMOS device structure in a device region according to a first embodiment of the invention.
Fig. 3 is a schematic side sectional view of an LDMOS device structure in a dielectric region according to a first embodiment of the invention.
Description of element reference numerals
100. A substrate layer; 200. an oxygen burying layer;
310. a device region; 311. source regions, 312, body regions, 313, channel regions, 314, gate regions; 315. a drift region; 316. a drain region;
321. a dielectric layer; 322. a field plate structure; 3221. a field plate layer; 3222. and a field plate control end.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the schematic drawings showing the structure of the apparatus are not partially enlarged to general scale, and the schematic drawings are merely examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
As shown in fig. 1-3, the present invention provides an LDMOS device structure, where fig. 1 is a top view of the LDMOS device structure, fig. 2 is a side sectional view of a cross section of the LDMOS device structure in a device region, and fig. 3 is a side sectional view of a cross section of the LDMOS device structure in a dielectric region, and the LDMOS device structure includes: a substrate layer 100, a buried oxide layer 200, and a device layer;
the substrate layer 100, the oxygen-buried layer 200 and the device layer are stacked in sequence from bottom to top along a first direction, the oxygen-buried layer 200 is located on the substrate layer 100, the device layer is located on the oxygen-buried layer 200, and the first direction is perpendicular to the substrate layer 100;
the device layer includes a device region 310 and a dielectric region; the dielectric regions are distributed on two sides of the device region 310 along a second direction, and the second direction is parallel to the substrate layer 100;
as shown in fig. 2, the device region 310 includes a source region 311 of a first conductivity type, a body region 312 of a second conductivity type, a channel region 313 of the second conductivity type, a gate region 314, a drift region 315 of the first conductivity type, and a drain region 316 of the first conductivity type; the channel region 313 is concave, the source region 311 is disposed in the concave region of the channel region 313 and exposed on the surface of the device region 310, the body region 312 is disposed in the source region 311, and the body region 312 penetrates through the source region 311 to connect with the channel region 313 so as to lead out the channel region 313 to the surface of the device region 310; the drift region 315 is concave, and the drain region 316 is disposed in the concave region of the drift region 315 and exposed on the surface of the device region 310; the drift regions 315 are distributed adjacent to the channel region 313 along a third direction, the third direction is perpendicular to the first direction and the second direction, and the top surfaces of the source region 311 and the drain region 316 are aligned and have equal thickness; the gate region 314 is located above the surface of the channel region 313 near the source region 311;
as shown in fig. 3, the dielectric region includes a dielectric layer 321, a field plate layer 3221 and a field plate control terminal 3222; the dielectric layers 321 are symmetrically disposed along the second direction at positions near the channel region 313 on both sides of the device region 310 and wrap both sides of the channel region 313; the field plate layers 3221 are symmetrically arranged at two sides of the drift region 315 near the drain region 316 along the second direction; the field plate control end 3222 covers the surface of the field plate layer 3221 which is not in contact with the drift region 315 and fills the gap formed in the dielectric region by the field plate layer 3221, so that the field plate control end 3222 and the field plate layer 3221 form a field plate structure 322, the cross section of the field plate structure 322, which is located on any one of two sides of the device region 310 and is parallel to the substrate layer 100, is rectangular, and the field plate control end 3222 is used for applying a voltage to the field plate layer 3221.
The field plates in the prior art are generally disposed inside the drift region 315 to make the electric field uniform, but parasitic capacitance between the gate and the drain is easily generated, and at the same time, the on-resistance is increased while the breakdown voltage is increased, so that the improvement of the breakdown voltage and the on-resistance cannot be realized, and the performance improvement is limited. The present invention is realized by disposing field plate structures 322 on two of the drift regions 315The space distribution flexibility of the field plate structure 322 on the electric field adjustment of the drift region 315 is improved, and very smooth electric field intensity distribution can be formed; meanwhile, by arranging the field plate structure 322 outside the device region 310, the linear increase of the source-drain resistance is avoided while the source-drain withstand voltage is improved, the specific on-resistance can be reduced, and the specific on-resistance is 40mΩ.mm when the source-drain withstand voltage reaches 300-500V 2 The following are set forth; in addition, through the distribution of the field plate structures 322 at the two sides of the drift region 315, the parasitic capacitance of the gate drain formed between the gate and the introduction is avoided, and the switching efficiency of the device is improved.
In one embodiment, the material of the field plate layer 3221 is a dielectric layer 321. Preferably, the material of the field plate layer 3221 is an oxide.
In one embodiment, as shown in fig. 1, the field plate layer 3221 located on either side of the device region 310 increases in length along a section parallel to the substrate layer 100 along a direction parallel to the third direction from a position away from the device region 310 to a position close to the device region 310.
According to the invention, the lengths of the field plate layers 3221 in the third direction are uniformly changed, so that the electric field distribution of the drain terminal is more uniform, and the on-resistance is further reduced while the voltage resistance is kept to be improved.
In one embodiment, the field plate layer 3221 on either side of the device region 310 is triangular, bell-shaped, parabolic, semi-elliptical, or semi-circular in cross-sectional shape parallel to the substrate layer 100; or the field plate layer 3221 located on either side of the device region 310 has a cross-sectional shape parallel to the substrate layer 100 of a triangle, bell shape, parabolic shape, semi-elliptical shape or semi-circular shape with the bottom being truncated by a cross-section parallel to the third direction, as shown in fig. 1 and 3, a triangle, i.e., trapezoid, with the cross-sectional shape being truncated by a cross-section parallel to the third direction.
In one embodiment, the field plate layer 3221 on either side of the device region 310 is symmetrically patterned along a cross-sectional shape parallel to the substrate layer 100, the axis of symmetry of the cross-sectional shape being parallel to the second direction.
The field plate layer 3221 is arranged to be a symmetrical graph, so that the uniform adjustment of the field plate layer 3221 to the electric field distribution of the drift region 315 is further improved.
In one embodiment, when the field plate layer 3221 located on either side of the device region 310 is triangular in a cross-sectional shape parallel to the substrate layer 100 or triangular in a shape of a bottom truncated by a cross-section line parallel to the third direction, an angle between two sidewalls of the field plate layer 3221 in contact with the field plate control terminal 3222 and the third direction is less than 30 °.
In one embodiment, the length of the field plate structure 322 on either side of the device region 310, parallel to the rectangular cross-section of the substrate layer 100 along the third direction, is 1 micron to 3 microns.
In one embodiment, the length of the field plate layer 3221 parallel to the third direction at the location of contact with the drift region 315 is equal to the length of the field plate structure 322 parallel to the third direction.
Specifically, the length of the field plate layer 3221 along the third direction is related to the source-drain voltage resistance value to be achieved, and needs to be adjusted according to specific parameter requirements.
In one embodiment, the field plate layer 3221 and the field plate control end 3222 have equal thicknesses in a first direction.
In one embodiment, the field plate layer 3221 is equal in length to the field plate control end 3222 in a second direction.
According to the invention, the field plate control end 3222 is arranged to just cover the surface of the field plate layer 3221, so that the voltage control of the field plate control end 3222 on the field plate layer 3221 is improved, and the more accurate and sensitive adjustment on the electric field intensity distribution of the drift region 315 can be realized.
In one embodiment, the cross-sectional shape of the field plate layer 3221 located on either side of the device region 310 along a direction parallel to the substrate layer 100 is a triangle, a bell, a parabola, a semi-ellipse, a semicircle, or a triangle, a bell, a parabola, a semi-ellipse, a semicircle with a bottom truncated by a cross-section line parallel to the third direction, and the zigzag or wave is repeatedly tiled along the third direction.
In one embodiment, the field plate layer 3221 is the same thickness as the drift region 315 along the first direction, and the top surface of the field plate layer 3221 is flush with the top surface of the drift region 315.
In one embodiment, the length of the surface of the field plate layer 3221 located on either side of the device region 310, which contacts the drift region 315, along the second direction is 0.15 micrometers to 0.3 micrometers, and the length of the device region 310 along the second direction is 0.6 micrometers to 0.8 micrometers.
Specifically, the length of the device region 310 along the second direction, that is, the distance between the field plate layers 3221 on two sides of the device region, where the distance relates to the source-drain withstand voltage value to be implemented, needs to be adjusted in cooperation with other parameters of the field plate layers 3221.
In one embodiment, the device layer has a thickness in the first direction of 1500 to 4000 angstroms.
In one embodiment, the buried oxide layer 200 has a thickness in the first direction of 500 to 1500 angstroms.
In one embodiment, the gate region 314 has a length in the third direction of 0.5 microns to 0.6 microns.
In one embodiment, the gate region 314 includes a gate oxide layer in contact with the upper surface of the device layer and a polysilicon layer on the gate oxide layer.
In one embodiment, the gate oxide layer has a thickness of 120 to 140 a m in the first direction and the polysilicon layer has a thickness of 1000 to 2500 a m in the first direction.
Example two
The invention also provides a preparation method of the LDMOS device structure, which is used for preparing the LDMOS device structure in any one of the first embodiment, and comprises the following steps:
step 1: providing a substrate layer 100, and disposing an oxygen-buried layer 200 above the substrate layer 100 along a first direction, wherein the first direction is perpendicular to the substrate layer 100;
step 2: a device layer is arranged above the oxygen-buried layer 200 along a first direction, a dielectric layer 321 is arranged at two sides of the device layer along a second direction, the second direction is parallel to the substrate layer 100, and the dielectric region and the device region 310 form a device layer;
step 3: a trench of a preset shape is arranged in the dielectric region near the preset drain region 316 to form a field plate layer 3221, the trench penetrates through the dielectric region, one side of the field plate layer 3221 is in contact with the device region 310, polysilicon material is filled in the trench to form a field plate control end 3222, and the field plate control end 3222 and the field plate layer 3221 form a field plate structure 322;
step 4: disposing a gate region 314 above the device layer along a first direction;
step 5: the device region 310 is doped to obtain a channel region 313 of a second conductivity type and a drift region 315 of a first conductivity type, which are adjacently arranged along a third direction, a source region 311 of the first conductivity type on the surface of the channel region 313, a drain region 316 of the first conductivity type on the surface of the drift region 315, and a body region 312 of the second conductivity type connected with the channel region 313 through the source region 311, wherein the channel region 313 is close to the gate region 314, the drift region 315 is in contact with the field plate layer 3221, and a dielectric region close to the channel region 313 is a dielectric layer 321.
The following will describe in detail the method for fabricating the LDMOS device structure of the present invention with reference to the accompanying drawings, wherein it should be noted that the above-mentioned sequence does not strictly represent the order of fabricating the LDMOS device structure protected by the present invention, and those skilled in the art can vary depending on the actual fabrication steps.
Firstly, step 1 is performed to provide a substrate layer 100, and an oxygen-buried layer 200 is disposed above the substrate layer 100 along a first direction, wherein the first direction is perpendicular to the substrate layer 100.
Then, step 2 is performed, a device layer is disposed above the buried oxide layer 200 along the first direction, and dielectric layers 321 are disposed on two sides of the device layer along the second direction, where the second direction is parallel to the substrate layer 100, and the dielectric regions and the device regions 310 form a device layer.
Next, step 3 is performed, a trench of a preset shape is disposed in the dielectric region near the preset drain region 316 to form a field plate layer 3221, the trench penetrates through the dielectric region, one side of the field plate layer 3221 contacts the device region 310, polysilicon material is filled in the trench to form a field plate control end 3222, and the field plate control end 3222 and the field plate layer 3221 form a field plate structure 322.
Then, step 4 is performed to dispose a gate region 314 above the device layer along the first direction.
Finally, in step 5, the device region 310 is doped to obtain a channel region 313 of the second conductivity type and a drift region 315 of the first conductivity type, which are adjacently disposed along the third direction, a source region 311 of the first conductivity type on the surface of the channel region 313, a drain region 316 of the first conductivity type on the surface of the drift region 315, and a body region 312 of the second conductivity type connected to the channel region 313 through the source region 311, wherein the channel region 313 is close to the gate region 314, the drift region 315 is in contact with the field plate layer 3221, and a dielectric region close to the channel region 313 is a dielectric layer 321.
According to the invention, the field plate layers 3221 are arranged on two sides of the drift region 315, so that the performance of reducing on-resistance while ensuring the improvement of withstand voltage can be realized by using a simple process under the condition that the original process is not greatly adjusted.
In summary, the LDMOS device structure and the preparation method thereof can realize high withstand voltage and low on-resistance and reduce parasitic capacitance of the gate and the drain by arranging the field plate layer on the side surface of the drift region of the device.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. An LDMOS device structure, the LDMOS device structure comprising: a substrate layer, a buried oxide layer and a device layer;
the substrate layer, the oxygen-buried layer and the device layer are sequentially stacked from bottom to top along a first direction, the oxygen-buried layer is positioned on the substrate layer, the device layer is positioned on the oxygen-buried layer, and the first direction is perpendicular to the substrate layer;
the device layer comprises a device region and a medium region; the dielectric regions are distributed on two sides of the device region along a second direction, and the second direction is parallel to the substrate layer;
the device region comprises a source region of a first conductivity type, a body region of a second conductivity type, a channel region of the second conductivity type, a gate region, a drift region of the first conductivity type and a drain region of the first conductivity type; the source region is arranged in the concave region of the channel region and exposed on the surface of the device region, the body region is arranged in the source region, and the body region penetrates through the source region and is connected with the channel region so as to lead out the channel region to the surface of the device region; the drift region is concave, and the drain region is arranged in the concave region of the drift region and is exposed on the surface of the device region; the drift regions and the channel regions are adjacently distributed along a third direction, the third direction is perpendicular to the first direction and the second direction, and the top surfaces of the source region and the drain region are aligned and have equal thickness; the gate region is located above the surface of the channel region near the source region;
the dielectric region comprises a dielectric layer, a field plate layer and a field plate control end; the dielectric layers are symmetrically arranged at positions, close to the channel region, on two sides of the device region along the second direction and wrap two sides of the channel region; the field plate layers are symmetrically arranged at positions, close to the drain electrode region, on two sides of the drift region along the second direction; the field plate control end covers the surface of the field plate layer which is not contacted with the drift region and fills a gap formed in the dielectric region by the field plate layer, so that the field plate control end and the field plate layer form a field plate structure, the section of the field plate structure, which is parallel to the substrate layer, of any one of two sides of the device region is rectangular, and the field plate control end is used for applying voltage to the field plate layer; the length of the field plate layer in the position of contacting the drift region, which is parallel to the third direction, is equal to the length of the field plate structure in the third direction, and the thickness of the field plate layer is equal to the thickness of the field plate control end in the first direction.
2. The LDMOS device structure of claim 1, wherein the field plate layer on either side of the device region increases in length along a cross-section parallel to the substrate layer along a direction parallel to the third direction from a position away from the device region to a position closer to the device region.
3. The LDMOS device structure of claim 2, wherein the field plate layer on either side of the device region is triangular, bell-shaped, parabolic, semi-elliptical, or semi-circular in cross-sectional shape parallel to the substrate layer; or the field plate layer located on either side of the device region has a triangular, bell-shaped, parabolic, semi-elliptical or semicircular cross-sectional shape parallel to the substrate layer with a bottom truncated by a cross-section line parallel to the third direction.
4. The LDMOS device structure of claim 3, wherein the field plate layer on either side of the device region is symmetrically patterned along a cross-sectional shape parallel to the substrate layer, the axis of symmetry of the cross-sectional shape being parallel to the second direction.
5. The LDMOS device structure of claim 3, wherein the field plate layer on either side of the device region has a triangular cross-sectional shape parallel to the substrate layer or a triangular shape with a bottom truncated by a cross-sectional line parallel to the third direction, wherein an angle between both sidewalls of the field plate layer in contact with the field plate control terminal and the third direction is less than 30 °.
6. The LDMOS device structure of claim 1, wherein the field plate structure on either side of the device region has a length of 1 micron to 3 microns in the third direction parallel to the rectangular cross-section of the substrate layer.
7. The LDMOS device structure of claim 1, wherein the field plate layer on either side of the device region has a cross-sectional shape parallel to the substrate layer of a plurality of triangles, bells, parabolas, semi-ellipses, semi-circles or triangles with bottoms truncated by a cross-sectional line parallel to the third direction, bells, parabolas, semi-ellipses, semi-circles repeatedly tiled along the third direction to form a zigzag or wave.
8. The LDMOS device structure of claim 1, wherein the thickness of the field plate layer is the same as the thickness of the drift region in the first direction, and wherein a top surface of the field plate layer is flush with a top surface of the drift region.
9. The LDMOS device structure of claim 1, wherein a length of a side of the field plate layer located on either side of the device region in contact with the drift region along the second direction is 0.15-0.3 microns, and a length of the device region along the second direction is 0.6-0.8 microns.
10. A method for manufacturing an LDMOS device structure according to any of claims 1-9, characterized in that the method is used for manufacturing an LDMOS device structure, the method comprising:
providing a substrate layer, and arranging an oxygen buried layer above the substrate layer along a first direction, wherein the first direction is perpendicular to the substrate layer;
a device region is arranged above the oxygen-buried layer along a first direction, medium regions are arranged on two sides of the device region along a second direction, the second direction is parallel to the substrate layer, and the medium regions and the device region form a device layer;
a groove with a preset shape is arranged at the position, close to the preset drain electrode region, of the medium region to form a field plate layer, the groove penetrates through the medium region, one side of the field plate layer is in contact with the device region, polysilicon materials are filled in the groove to form a field plate control end, and the field plate control end and the field plate layer form a field plate structure;
a grid electrode region is arranged above the device layer along the first direction;
doping the device region to obtain a channel region of a second conductivity type and a drift region of a first conductivity type, which are adjacently arranged along a third direction, a source region of the first conductivity type on the surface of the channel region, a drain region of the first conductivity type on the surface of the drift region, and a body region of the second conductivity type, which penetrates through the source region and is connected with the channel region, wherein the channel region is close to the gate region, the drift region is in contact with the field plate layer, and a dielectric region close to the channel region is a dielectric layer.
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| CN102184944A (en) * | 2011-04-29 | 2011-09-14 | 南京邮电大学 | Junction terminal structure of lateral power device |
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| CN115332352A (en) * | 2022-08-26 | 2022-11-11 | 天狼芯半导体(成都)有限公司 | High-voltage LDMOS device and preparation method thereof |
| CN116207149A (en) * | 2021-11-30 | 2023-06-02 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
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| US11121224B2 (en) * | 2019-02-08 | 2021-09-14 | Texas Instruments Incorporated | Transistor with field plate over tapered trench isolation |
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| CN106935647A (en) * | 2015-12-31 | 2017-07-07 | 爱思开海力士有限公司 | Lateral direction power integrated device with low on-resistance |
| CN116207149A (en) * | 2021-11-30 | 2023-06-02 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method for manufacturing the same |
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