CN117219645A - Method for realizing semiconductor epitaxy and semiconductor device - Google Patents

Abstract

The invention provides a method for realizing semiconductor epitaxy, which comprises the following steps: etching the semiconductor substrate to form semiconductor island structures arranged in an array before the grid of the semiconductor device is formed, wherein at least the upper parts of the semiconductor island structures are connected with each other through at least one connecting structure so as to reduce defects generated by a subsequent epitaxial process; the etching semiconductor substrate forms a semiconductor island-shaped structure which is arranged in an array, and the semiconductor island-shaped structure at least comprises: etching the semiconductor substrate at a negative angle to form a first groove; forming a protective medium layer on the surface of the first groove; and continuing to etch the first groove to form the semiconductor island-shaped structure and the connection structure. According to the invention, the negative angle of the cantilever beam etched at one time is larger than that of the column body in the pixel area, and the isotropic etching amount required by the communication under the cantilever beam after the deep trench etching at the second time is reduced, so that polymer residues are reduced, and the process window and the yield are increased.

Description

A method for realizing semiconductor epitaxy and semiconductor device

Technical field

The present invention relates to the field of semiconductor technology, and in particular to a method for realizing semiconductor epitaxy and a semiconductor device.

Background technique

In the formation process of semiconductor devices, it is often necessary to perform etching, ion implantation, epitaxy and other processes on the semiconductor substrate. Taking an image sensor as an example, the photodiode in the photosensitive area of the image sensor is used to convert optical signals into electrical signals, and the photosensitive units can be formed through ion implantation or epitaxy. However, as the pixel size continues to decrease, the ion implantation method has some defects in the process. In order to ensure the blocking of high-energy P-type doped ions in the non-isolation area, the thickness of the resist mask used must also increase. This mask is easily tilted during steps such as development and ion implantation, causing the pixel area or isolation area to be unable to achieve normal ion implantation effects in subsequent processes, thereby affecting the performance of the final image sensor. In addition, ion implantation also has other disadvantages, such as excessive defects and uneven distribution of implanted doping ions. Moreover, ion implantation needs to be combined with a high-temperature annealing process to repair defects, which can easily damage the formed logic device.

A new process for image sensor photosensitive units is to form PN junctions or PIN junctions through deep trench etching and selective epitaxy, as mentioned in patents CN204632760U and CN113224093A. But this method also has certain shortcomings. During epitaxial growth, growth must be from the bottom of the deep trench upwards, otherwise lattice dislocation is likely to occur. At the same time, the line width at the intersection of the deep trench used to isolate the pixel unit is large (as shown in Figure 1, the line width at the intersection of the trench The length of AC is greater than the trench line width AB), which can easily form voids during epitaxial growth and cause dislocations at the interface of the epitaxial layer. This dislocation will further cause defects in the subsequent epitaxial growth process, thereby affecting the performance and yield of devices arranged in this area.

On this basis, there are also methods to improve the effect of epitaxy by forming a cantilever structure to connect each pixel unit. In the existing cantilever structure solution, it is necessary to connect the lower substrate of the connecting part through isotropic etching, but this will also cause the pixel area to be lateral etched and the pixel area cylinder to shrink. In addition, the lateral etching will The increased thickness of etching will also lead to increased polymer residue, making it difficult to remove the polymer in deep trenches and increasing defects.

Contents of the invention

The object of the present invention is to provide a method for realizing semiconductor epitaxy. Specifically, the method includes:

Before forming the gate of the semiconductor device, the semiconductor substrate is etched to form an array of semiconductor island structures, and at least the upper parts of each of the semiconductor island structures are connected to each other through at least one connection structure to reduce the subsequent epitaxial process. resulting defects;

Wherein, the etching of the semiconductor substrate to form an array-arranged semiconductor island structure at least includes:

Perform negative-angle etching on the semiconductor substrate to form a first trench;

Form a protective dielectric layer on the surface of the first trench;

Continue to etch the first trench to form the semiconductor island structure and the connection structure.

Further, during the process of etching the semiconductor substrate, by controlling the etching process conditions, the bottom of the connection structure is suspended to form a cantilever connection structure.

Further, forming a cantilever connection structure includes:

Continue to etch the first trench to form the semiconductor island structure and the connection structure, and a second trench that is not connected to each other is formed between the connection structures;

Through lateral isotropic etching, the second groove width on both sides of the connection structure is increased and connected to form the cantilever connection structure.

Further, when the semiconductor substrate is etched at a negative angle to form the first trench, the distance between adjacent connection structures is greater than the distance between adjacent semiconductor island structures. , the length direction of the first trench corresponds to the connection structure, and the width direction corresponds to the semiconductor island structure.

Further, when the semiconductor substrate is etched at a negative angle to form the first trench, the etching angle in the length direction of the first trench is greater than the first etching angle at the semiconductor island structure. The etching angle in the trench width direction is more negative.

Further, the method also includes:

Through an epitaxial process, a first epitaxial layer is formed on the surface of the semiconductor island structure;

Form a dielectric layer on the surface of the first epitaxial layer;

removing the dielectric layer at the opening of the first trench between the semiconductor island structures;

A second epitaxial layer is formed at the opening through an epitaxial process to seal the opening.

Further, the dielectric layer includes a combination of one or more sub-dielectric layers.

Further, the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer.

Further, the first sub-dielectric layer is silicon oxide; the second sub-dielectric layer is silicon nitride or silicon oxynitride.

Further, the second sub-dielectric layer is silicon nitride. By adjusting the silicon nitride growth process, the silicon nitride is negatively charged, and the first trench between the semiconductor island structures is The side walls produce pinning.

Further, the dielectric layer serves as a stop layer for the backside thinning process of the semiconductor substrate.

Further, the semiconductor island structure is polygonal.

Further, at least the upper parts of each of the semiconductor island structures are connected to each other through connection structures located at the corners of the polygons to reduce defects caused by subsequent epitaxial processes.

Furthermore, the semiconductor island-shaped structures are in a quadrilateral shape, and at least the upper portions of each of the semiconductor island-shaped structures are connected to each other through connection structures located at four corners of the quadrilateral to reduce defects caused by subsequent epitaxial processes.

Further, the semiconductor epitaxy implementation method is used to form an image sensor, and the semiconductor island structure is used to form a pixel unit.

Further, the first epitaxial layer at least includes a sub-epitaxial layer with a doping ion type opposite to that of the semiconductor island structure to form a PN junction structure of the pixel unit.

Further, forming the first epitaxial layer includes:

Epitaxially low doping or intrinsic semiconductor is formed on the sidewall surface of the semiconductor island structure to form the first sub-epitaxial layer of the first epitaxial layer;

A second sub-epitaxial layer with a doping ion type opposite to that of the semiconductor island structure is epitaxially formed on the surface of the first sub-epitaxial layer to form a PN junction structure of the pixel unit.

Further, the epitaxial formation of the first epitaxial layer on the sidewall surface of the semiconductor island structure includes:

A first doped type semiconductor material is epitaxially grown on the sidewall surface of the semiconductor island structure to form a third sub-epitaxial layer of the first epitaxial layer;

Etching to remove the third sub-epitaxial layer on the bottom surface of the first trench between the semiconductor island structures and etching to deepen the depth of the first trench;

Epitaxy a low-doping or intrinsic semiconductor on the surface of the third sub-epitaxial layer to form a fourth sub-epitaxial layer;

A semiconductor material of the opposite doping type to that of the first doping type is epitaxially grown on the surface of the fourth sub-epitaxial layer to form a fifth sub-epitaxial layer to form a PN junction structure of the pixel unit.

Further, the grooves on both sides of the connection structure are post-processed to make the bottom of the cantilever connection structure smooth.

Further, when the semiconductor island structure is a quadrilateral, the connection structure is an X-shape or a ring-shaped structure with four corners connected.

The present invention also provides a semiconductor device, which adopts the aforementioned semiconductor epitaxy implementation method during the formation process.

Through the above scheme, the present invention adopts negative angle etching, so that the negative angle of the first etching of the cantilever is larger than that of the pixel area cylinder, and the isotropic etching required for communication below the cantilever (side surface) after the second deep trench etching is The amount of etching is reduced, polymer residue is reduced, and the process window and yield are increased.

Description of drawings

Other features, objects and advantages of the present invention will become more apparent upon reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

Figure 1 is a schematic diagram of inconsistent line widths at the intersection of trenches in the existing solution;

Figure 2 is a schematic structural diagram of the application of the semiconductor epitaxial method in the present invention;

3 to 5 are structural schematic diagrams of the semiconductor island structure and the connection structure in different embodiments of the present invention.

In the figures, the same or similar reference numbers represent the same or similar devices (modules) or steps throughout the different views.

Detailed ways

The object of the present invention is to provide a method for realizing semiconductor epitaxy. Specifically, the method includes the following steps:

Before forming the gate of the semiconductor device, the semiconductor substrate 100 is etched to form semiconductor island structures 110 arranged in an array, and at least the upper parts of each of the semiconductor island structures 110 are connected to each other through at least one connection structure 120, so as to Reduce defects caused by subsequent epitaxial processes, as shown in Figure 2;

Among them, as shown in FIG. 3 , a cross-sectional view along the AA′, BB′, and CC′ directions as shown in FIG. 2 is shown. The etched semiconductor substrate 100 forms an array-arranged semiconductor. The island structure 110 at least includes:

Step S110: Perform negative-angle etching on the semiconductor substrate 100 to form a first trench 130;

Step S120: Form a protective dielectric layer 200 on the surface of the first trench 130;

Step S130: Continue etching the first trench 130 to form the semiconductor island structure 110 and the connection structure 120.

In an optional embodiment, in step S130, the bottom of the connection structure 120 can be suspended by controlling the etching process conditions to form a cantilever connection structure 121.

Preferably, as shown in Figure 4, the cantilever connection structure 121 can be formed through the following steps:

Step S131: Continue to etch the first trench 130 to form the semiconductor island structure 110 and the connection structure 120, and form a non-connected second trench 140 between the connection structures 120;

Step S132: Through lateral isotropic etching, the width of the second trench 140 on both sides of the connection structure 120 is increased and connected to form the cantilever connection structure 121.

In an optional embodiment, in step S110, the semiconductor substrate 100 is etched at a negative angle. When the first trench 130 is formed, the lines of the first trench 130 on both sides of the connection structure The width is not less than the line width of the first trench 130 between the semiconductor island structures 110 .

Similarly, in another optional implementation, when forming the first trench 130 in step S110, the etching angle at the connection structure 120 is greater than the etching angle at the semiconductor island structure 110. .

Further, as shown in Figure 5, in one embodiment, the method further includes:

Step S210: Form the first epitaxial layer 111 on the surface of the semiconductor island structure 110 through an epitaxial process;

Step S220: Form a dielectric layer 112 on the surface of the first epitaxial layer 111;

Step S230: Remove the dielectric layer 112 at the opening of the first trench 130 between the semiconductor island structures 110;

Step S240: Form the second epitaxial layer 113 at the opening through an epitaxial process, and seal the opening.

Preferably, the dielectric layer 112 formed in step S220 may include a combination of one or more sub-dielectric layers. For example, the dielectric layer 112 may be composed of at least a first sub-dielectric layer 1121 and a second sub-dielectric layer 1122 . Preferably, in one implementation, the first sub-dielectric layer 1121 may be made of silicon oxide material, and the second sub-dielectric layer 1122 may be made of silicon nitride or silicon oxynitride material.

In an optional embodiment, the second sub-dielectric layer 1122 is made of silicon nitride. In the present invention, the silicon nitride growth process can be adjusted to make the silicon nitride negatively charged, thereby increasing the charge of the silicon nitride. The sidewalls of the first trench 130 between the semiconductor island structures 110 are pinning.

Further, in an optional embodiment, the dielectric layer 112 can be used as a stop layer in the backside thinning process of the semiconductor substrate 100, and the semiconductor substrate 100 can be thinned to a suitable position in subsequent processes.

In an embodiment of the present invention, the semiconductor epitaxy implementation method is used to form an image sensor, wherein the semiconductor island structure 110 is used to form a pixel unit.

In an optional embodiment, the first epitaxial layer 111 at least includes a sub-epitaxial layer with a doping ion type opposite to that of the semiconductor island structure 110 to form a PN junction structure of the pixel unit.

Specifically, in an optional implementation, as shown in FIG. 5 , forming the first epitaxial layer 111 in step S210 includes the following steps:

Step S2111: Epitaxy low-doping or intrinsic semiconductor on the sidewall surface of the semiconductor island structure 110 to form the first sub-epitaxial layer 1111 of the first epitaxial layer 111;

Step S2112: Epitaxially form a second sub-epitaxial layer 1112 with a doping ion type opposite to that of the semiconductor island structure 110 on the surface of the first sub-epitaxial layer 1111 to form a PN junction structure of the pixel unit.

In another optional implementation, forming the first epitaxial layer 111 in step S210 includes the following steps:

Step S2121: Epitaxially extend the first doping type semiconductor material on the sidewall surface of the semiconductor island structure to form the third sub-epitaxial layer 1113 of the first epitaxial layer 111;

Step S2122: Etch to remove the third sub-epitaxial layer on the bottom surface of the first trench between the semiconductor island structures 110 and etching to deepen the depth of the first trench;

Epitaxy a low-doping or intrinsic semiconductor on the surface of the third sub-epitaxial layer to form a fourth sub-epitaxial layer;

A semiconductor material of the opposite doping type to that of the first doping type is epitaxially grown on the surface of the fourth sub-epitaxial layer to form a fifth sub-epitaxial layer to form a PN junction structure of the pixel unit.

In the present invention, the semiconductor substrate 100 is etched to form semiconductor island structures 110 arranged in an array. In an optional embodiment, the semiconductor island structures 110 may be in a polygonal shape. On this basis, in an optional embodiment, at least the upper portions of each of the semiconductor island structures 110 are connected to each other through connection structures 120 located at the corners of the polygons to reduce defects caused by subsequent epitaxial processes.

For example, optionally, the semiconductor island-shaped structures 110 may be in a quadrilateral shape, and at least the upper portions of each of the semiconductor island-shaped structures 110 are connected to each other through connection structures 120 located at the four corners of the quadrilateral. Further, in this embodiment, the connecting structure 120 may be selected to be an X-shaped or annular structure with four corners connected.

In an optional embodiment of the present invention, when etching the semiconductor substrate 100, the etching process conditions can be controlled to make the bottom of the connection structure 120 suspended to form a cantilever connection structure 121. Preferably, when forming the cantilever connection structure 121, the semiconductor island structure 110 and the connection structure 120 can be formed by continuing to etch the first trench 130, and the connection structures 120 are interconnected. second trench 140; then, through lateral isotropic etching, the width of the second trench 140 on both sides of the connection structure is increased and connected to form the cantilever connection structure 121.

In actual operation, a plasma with isotropic etching capability can be formed first by dry etching, and then the plasma can be used to etch the side walls of the semiconductor island structure 110 and the connection structure 120 , until the bottom of the connection structure is connected to form a cantilever connection structure 121. In an optional implementation, a chemical dry etching process can be used for etching. This etching method has a higher selectivity ratio for silicon and silicon oxide. The etching rate is generally selected to be 30~300 A/min. The temperature does not exceed 135℃. The chemical dry etching process can repair the plasma damage caused by the previous process and optimize the roughness of the trench surface.

In another optional implementation, wet etching can also be used to achieve isotropic etching of the sidewalls of the epitaxial layer. Preferably, solutions such as hydrofluoric acid, nitric acid, ammonia water, etc. can be used to etch the semiconductor. The sidewalls of the island structure 110 and the connection structure 120 are wet etched. The etching temperature is preferably 20~40°C, and the etching time can be adjusted according to the thickness required to be etched.

Preferably, the bottom of the cantilever connection structure 121 can be made smooth by post-processing the grooves on both sides of the connection structure 120 . By smoothing the bottom of the cantilever connection structure 121, by-products generated during the etching process can be effectively removed, and the surface dielectric layer, hard mask, etc. can be removed. During post-processing, it is preferable to use a mixed solution of chemical reagents such as hydrofluoric acid, hydrogen peroxide, ammonia, and hydrochloric acid for wet etching. The etching time is preferably 30 to 300 seconds, and the etching temperature is preferably 20 to 40°C.

The present invention also provides a semiconductor device, which is suitable for adopting the aforementioned semiconductor epitaxy implementation method during the formation process. The semiconductor device may be an image sensor, wherein the semiconductor island structure may serve as a pixel unit of the image sensor, and then optical isolation and electrical isolation between the pixel units are formed.

It is obvious to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Accordingly, the embodiments should be considered in all respects as illustrative and not restrictive. Furthermore, it is evident that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude the plural. Several elements stated in a device claim can also be embodied by one element. The words first, second, etc. are used to indicate names and do not indicate any specific order.

Claims (21)

1. A method for realizing semiconductor epitaxy, which is characterized by including: Before forming the gate of the semiconductor device, the semiconductor substrate is etched to form an array of semiconductor island structures, and at least the upper parts of each of the semiconductor island structures are connected to each other through at least one connection structure to reduce the subsequent epitaxial process. resulting defects; Wherein, the etching of the semiconductor substrate to form an array-arranged semiconductor island structure at least includes: Perform negative-angle etching on the semiconductor substrate to form a first trench; Form a protective dielectric layer on the surface of the first trench; Continue to etch the first trench to form the semiconductor island structure and the connection structure. 2. The method for realizing semiconductor epitaxy according to claim 1, characterized in that, in the process of continuing to etch the first trench to form the semiconductor island structure and the connection structure, by controlling The etching process conditions make the bottom of the connection structure suspended, forming a cantilever connection structure. 3. The method for realizing semiconductor epitaxy according to claim 2, wherein forming the cantilever connection structure includes: Continue to etch the first trench to form the semiconductor island structure and the connection structure, and a second trench that is not connected to each other is formed between the connection structures; Through lateral isotropic etching, the second groove width on both sides of the connection structure is increased and connected to form the cantilever connection structure. 4. The method for realizing semiconductor epitaxy according to claim 1, wherein when the semiconductor substrate is etched at a negative angle to form the first trench, the distance between the adjacent connection structures is The distance is greater than the distance between adjacent semiconductor island structures, the length direction of the first trench corresponds to the connection structure, and the width direction corresponds to the semiconductor island structure. 5. The method for realizing semiconductor epitaxy according to claim 1, characterized in that when the semiconductor substrate is etched at a negative angle to form the first trench, in the length direction of the first trench The etching angle is more negative than the etching angle in the first trench width direction at the semiconductor island structure. 6. The implementation method of semiconductor epitaxy according to claim 1, characterized in that the method further includes: Through an epitaxial process, a first epitaxial layer is formed on the surface of the semiconductor island structure; Form a dielectric layer on the surface of the first epitaxial layer; removing the dielectric layer at the opening of the first trench between the semiconductor island structures; A second epitaxial layer is formed at the opening through an epitaxial process to seal the opening. 7. The method for implementing semiconductor epitaxy according to claim 6, wherein the dielectric layer includes a combination of one or more sub-dielectric layers. 8. The method for implementing semiconductor epitaxy according to claim 7, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer. 9. The method for implementing semiconductor epitaxy according to claim 8, wherein the first sub-dielectric layer is silicon oxide; and the second sub-dielectric layer is silicon nitride or silicon oxynitride. 10. The method of forming an image sensor according to claim 8, wherein the second sub-dielectric layer is silicon nitride, wherein the silicon nitride is negatively charged by adjusting the silicon nitride growth process. , pinning the sidewalls of the first trench between the semiconductor island structures. 11. The method for realizing semiconductor epitaxy according to claim 6, wherein the dielectric layer serves as a stop layer for the backside thinning process of the semiconductor substrate. 12. The method for implementing semiconductor epitaxy according to claim 1, wherein the semiconductor island structure is polygonal. 13. The method of realizing semiconductor epitaxy according to claim 12, characterized in that at least the upper parts of each of the semiconductor island-shaped structures are connected to each other through connection structures located at the corners of the polygons, so as to reduce the damage caused by subsequent epitaxial processes. defect. 14. The method for realizing semiconductor epitaxy according to claim 13, characterized in that the semiconductor island-shaped structure is a quadrilateral, and at least the upper parts of each of the semiconductor island-shaped structures are connected to each other through connection structures located at the four corners of the quadrilateral. connection to reduce defects caused by subsequent epitaxial processes. 15. The method of realizing semiconductor epitaxy according to claim 1, characterized in that, the method of realizing semiconductor epitaxy is used to form an image sensor, and the semiconductor island structure is used to form a pixel unit. 16. The method of claim 6, wherein the first epitaxial layer at least includes a sub-epitaxial layer with a doping ion type opposite to that of the semiconductor island structure to form the pixel. The PN junction structure of the unit. 17. The method for implementing semiconductor epitaxy according to claim 16, wherein forming the first epitaxial layer includes: Epitaxially low doping or intrinsic semiconductor is formed on the sidewall surface of the semiconductor island structure to form the first sub-epitaxial layer of the first epitaxial layer; A second sub-epitaxial layer with a doping ion type opposite to that of the semiconductor island structure is epitaxially formed on the surface of the first sub-epitaxial layer to form a PN junction structure of the pixel unit. 18. The method for realizing semiconductor epitaxy according to claim 16, wherein the forming the first epitaxial layer by epitaxy on the sidewall surface of the semiconductor island structure includes: A first doped type semiconductor material is epitaxially grown on the sidewall surface of the semiconductor island structure to form a third sub-epitaxial layer of the first epitaxial layer; Etching to remove the third sub-epitaxial layer on the bottom surface of the first trench between the semiconductor island structures and etching to deepen the depth of the first trench; Epitaxy a low-doping or intrinsic semiconductor on the surface of the third sub-epitaxial layer to form a fourth sub-epitaxial layer; A semiconductor material of the opposite doping type to that of the first doping type is epitaxially grown on the surface of the fourth sub-epitaxial layer to form a fifth sub-epitaxial layer to form a PN junction structure of the pixel unit. 19. The method for realizing semiconductor epitaxy according to claim 2, characterized in that post-processing is performed on the grooves on both sides of the connection structure to smooth the bottom of the cantilever connection structure. 20. The method for realizing semiconductor epitaxy according to claim 13, characterized in that when the semiconductor island structure is a quadrilateral, the connection structure is an X-shape or a ring-shaped structure with four corners connected. 21. A semiconductor device, characterized in that the semiconductor epitaxy implementation method according to claims 1 to 20 is used in the formation process.