CN117219645A - Method for realizing semiconductor epitaxy and semiconductor device - Google Patents
Method for realizing semiconductor epitaxy and semiconductor device Download PDFInfo
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- CN117219645A CN117219645A CN202210621621.6A CN202210621621A CN117219645A CN 117219645 A CN117219645 A CN 117219645A CN 202210621621 A CN202210621621 A CN 202210621621A CN 117219645 A CN117219645 A CN 117219645A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 145
- 238000000034 method Methods 0.000 title claims abstract description 80
- 238000000407 epitaxy Methods 0.000 title claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 230000007547 defect Effects 0.000 claims abstract description 13
- 230000001681 protective effect Effects 0.000 claims abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 abstract description 4
- 238000004891 communication Methods 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
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- 238000002955 isolation Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 240000004282 Grewia occidentalis Species 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
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- 238000012805 post-processing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The invention provides a method for realizing semiconductor epitaxy, which comprises the following steps: etching the semiconductor substrate to form semiconductor island structures arranged in an array before the grid of the semiconductor device is formed, wherein at least the upper parts of the semiconductor island structures are connected with each other through at least one connecting structure so as to reduce defects generated by a subsequent epitaxial process; the etching semiconductor substrate forms a semiconductor island-shaped structure which is arranged in an array, and the semiconductor island-shaped structure at least comprises: etching the semiconductor substrate at a negative angle to form a first groove; forming a protective medium layer on the surface of the first groove; and continuing to etch the first groove to form the semiconductor island-shaped structure and the connection structure. According to the invention, the negative angle of the cantilever beam etched at one time is larger than that of the column body in the pixel area, and the isotropic etching amount required by the communication under the cantilever beam after the deep trench etching at the second time is reduced, so that polymer residues are reduced, and the process window and the yield are increased.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for implementing semiconductor epitaxy and a semiconductor device.
Background
In the formation of semiconductor devices, processes such as etching, ion implantation, epitaxy, etc. are often required for the semiconductor substrate. Taking an image sensor as an example, a photodiode in a photosensitive area of the image sensor is used to convert an optical signal into an electrical signal, wherein the photosensitive unit can be formed by ion implantation, epitaxy, or the like. However, as the pixel size continues to decrease, there are some drawbacks in the process, and the thickness of the resist mask used is also increased in order to ensure blocking of high energy P-type dopant ions in non-isolated regions. The mask is easily inclined in the steps of development, ion implantation and the like, so that the effect of normal ion implantation cannot be achieved in a pixel region or an isolation region in a subsequent process, and the performance of a final image sensor is affected. In addition, ion implantation has other disadvantages such as excessive defects, uneven distribution of implanted dopant ions, etc., and the ion implantation requires a high temperature annealing process to repair the defects, which is liable to damage the logic devices already formed.
A new process for forming the photosensitive cells of image sensors is by deep trench etching and selective epitaxy to form PN junctions or PIN junctions, as is mentioned in both CN204632760U and CN113224093 a. However, this method has certain drawbacks. During epitaxial growth, the deep trenches must be grown upwards from the bottoms of the deep trenches, otherwise lattice dislocation is easy to occur, meanwhile, the line width of the intersections of the deep trenches for isolating the pixel units is large (as shown in fig. 1, the length of the line width AC of the intersections of the deep trenches is larger than the line width AB of the deep trenches), voids are easy to form during epitaxial growth, and dislocation at the interface of the epitaxial layer is caused. This dislocation can further lead to defects in the subsequent epitaxial growth process, affecting the performance and yield of devices disposed in that region.
On this basis, there is also a method of improving the effect of epitaxy by forming a cantilever structure to connect each pixel cell. In the existing cantilever structure scheme, the lower substrate of the connecting part is required to be communicated in an isotropic etching mode, but the pixel area is laterally etched and the column body of the pixel area is reduced, in addition, polymer residues are aggravated due to the increase of the thickness of the lateral etching, the polymer in the deep groove is difficult to remove, and defects are increased.
Disclosure of Invention
The invention aims to provide a method for realizing semiconductor epitaxy, which concretely comprises the following steps:
etching the semiconductor substrate to form semiconductor island structures arranged in an array before the grid of the semiconductor device is formed, wherein at least the upper parts of the semiconductor island structures are connected with each other through at least one connecting structure so as to reduce defects generated by a subsequent epitaxial process;
the etching semiconductor substrate forms a semiconductor island-shaped structure which is arranged in an array, and the semiconductor island-shaped structure at least comprises:
etching the semiconductor substrate at a negative angle to form a first groove;
forming a protective medium layer on the surface of the first groove;
and continuing to etch the first groove to form the semiconductor island-shaped structure and the connection structure.
Further, in the process of etching the semiconductor substrate, the bottom of the connecting structure is suspended by controlling the etching process conditions, so that a cantilever connecting structure is formed.
Further, the forming the cantilever beam connecting structure includes:
continuing to etch the first groove to form the semiconductor island-shaped structure and the connection structure, and forming a second groove which is not communicated with each other between the connection structures;
and the width of the second grooves at two sides of the connecting structure is increased and communicated through lateral isotropic etching, so that the cantilever connecting structure is formed.
Further, when the semiconductor substrate is subjected to negative angle etching to form a first groove, the distance between adjacent connection structures is larger than the distance between adjacent semiconductor island structures, the length direction of the first groove corresponds to the connection structures, and the width direction of the first groove corresponds to the semiconductor island structures.
Further, when the semiconductor substrate is subjected to negative angle etching to form a first groove, the etching angle in the length direction of the first groove is more negative than the etching angle in the width direction of the first groove in the semiconductor island-shaped structure.
Further, the method further comprises:
forming a first epitaxial layer on the surface of the semiconductor island-shaped structure through an epitaxial process;
forming a dielectric layer on the surface of the first epitaxial layer;
removing the dielectric layer at the opening of the first groove between the semiconductor island structures;
and forming a second epitaxial layer at the opening through an epitaxial process, and closing the opening.
Further, the dielectric layer comprises a combination of one or more sub-dielectric layers.
Further, the dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer.
Further, the first sub-dielectric layer is silicon oxide; the second sub-dielectric layer is silicon nitride or silicon oxynitride.
Further, the second sub-dielectric layer is silicon nitride, and negative charges are carried on the silicon nitride by adjusting the silicon nitride growth process, so that pinning is generated on the side wall of the first groove between the semiconductor island structures.
Further, the dielectric layer is used as a stop layer of the back thinning process of the semiconductor substrate.
Further, the semiconductor island structure is polygonal.
Further, at least the upper parts of the semiconductor island structures are connected with each other through a connecting structure positioned at the polygonal corner, so that defects generated in a subsequent epitaxial process are reduced.
Further, the semiconductor island structures are quadrilateral, and at least the upper parts of the semiconductor island structures are connected with each other through connecting structures at four corners of the quadrilateral, so that defects generated by a subsequent epitaxial process are reduced.
Further, the implementation method of the semiconductor epitaxy is used for forming an image sensor, and the semiconductor island-shaped structure is used for forming a pixel unit.
Further, the first epitaxial layer at least comprises a sub-epitaxial layer with the doping ion type opposite to that of the semiconductor island-shaped structure, so that a PN junction structure of the pixel unit is formed.
Further, the forming the first epitaxial layer includes:
a low doped or intrinsic semiconductor is epitaxially grown on the surface of the side wall of the semiconductor island-shaped structure, and a first sub-epitaxial layer of the first epitaxial layer is formed;
and forming a second sub-epitaxial layer with the opposite doping ion type to the semiconductor island-shaped structure on the surface of the first sub-epitaxial layer in an epitaxial manner to form a PN junction structure of the pixel unit.
Further, the step of performing epitaxy on the surface of the side wall of the semiconductor island-shaped structure to form a first epitaxial layer comprises the following steps:
a semiconductor material of a first doping type is epitaxially grown on the surface of the side wall of the semiconductor island-shaped structure, and a third sub-epitaxial layer of the first epitaxial layer is formed;
etching to remove the third sub-epitaxial layer on the bottom surface of the first groove between the semiconductor island structures and deepen the depth of the first groove;
a low-doped or intrinsic semiconductor is epitaxially grown on the surface of the third sub-epitaxial layer, so that a fourth sub-epitaxial layer is formed;
and epitaxially growing a semiconductor material with the opposite doping type to the first doping type on the surface of the fourth sub-epitaxial layer to form a fifth sub-epitaxial layer so as to form the PN junction structure of the pixel unit.
Further, the grooves on two sides of the connecting structure are subjected to post-treatment, so that the bottom of the cantilever beam connecting structure is smooth.
Further, when the semiconductor island structure is quadrilateral, the connection structure is an annular structure with X-shape or four corners connected.
The invention also provides a semiconductor device, and the method for realizing the semiconductor epitaxy is adopted in the forming process.
According to the scheme, the negative angle etching is adopted, so that the negative angle of the cantilever beam etched for the first time is larger than that of the pixel area column body, the isotropic etching (side etching) amount required by the communication under the cantilever beam after the deep trench etching for the second time is reduced, polymer residues are reduced, and the process window and the yield are increased.
Drawings
Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments which follows, which is read in connection with the accompanying drawings.
FIG. 1 is a schematic diagram of a prior art scheme of line width non-uniformity at a trench intersection;
fig. 2 is a schematic structural diagram of a semiconductor epitaxial method according to the present invention;
fig. 3 to 5 are schematic views of structures of semiconductor island structures and connection structures according to various embodiments of the present invention.
In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout the different drawings.
Detailed Description
The invention aims to provide a method for realizing semiconductor epitaxy, which comprises the following steps:
before forming the gate of the semiconductor device, etching the semiconductor substrate 100 to form semiconductor island structures 110 arranged in an array, wherein at least upper parts of the semiconductor island structures 110 are connected with each other through at least one connecting structure 120, so as to reduce defects generated by a subsequent epitaxial process, as shown in fig. 2;
wherein, as shown in fig. 3, which shows a cross-sectional view in A-A ', B-B ', C-C ' direction as shown in fig. 2, the etching the semiconductor substrate 100 to form the semiconductor island-like structure 110 arranged in an array at least includes:
step S110: performing negative angle etching on the semiconductor substrate 100 to form a first trench 130;
step S120: forming a protective dielectric layer 200 on the surface of the first trench 130;
step S130: and continuing to etch the first trench 130 to form the semiconductor island structure 110 and the connection structure 120.
In an optional embodiment, in step S130, the bottom of the connection structure 120 may be suspended by controlling the etching process conditions, so as to form the cantilever connection structure 121.
Preferably, as shown in fig. 4, the formation of the cantilever beam connecting structure 121 may be formed by:
step S131: continuing to etch the first trench 130 to form the semiconductor island structure 110 and the connection structure 120, wherein a second trench 140 which is not communicated with each other is formed between the connection structures 120;
step S132: the second grooves 140 on both sides of the connection structure 120 are increased in width and are connected by the etching with the same polarity in the lateral direction, so as to form the cantilever connection structure 121.
In an alternative embodiment, in step S110, the semiconductor substrate 100 is subjected to negative angle etching, so that the line width of the first trenches 130 on both sides of the connection structure is not smaller than the line width of the first trenches 130 between the semiconductor island structures 110 when the first trenches 130 are formed.
Likewise, in another alternative embodiment, step S110 is performed to form the first trench 130 at a greater etching angle at the connection structure 120 than at the semiconductor island structure 110.
Further, as shown in fig. 5, in one embodiment, the method further comprises:
step S210: forming a first epitaxial layer 111 on the surface of the semiconductor island structure 110 through an epitaxial process;
step S220: forming a dielectric layer 112 on the surface of the first epitaxial layer 111;
step S230: removing the dielectric layer 112 at the opening of the first trench 130 between the semiconductor island structures 110;
step S240: and forming a second epitaxial layer 113 at the opening through an epitaxial process, and closing the opening.
Preferably, the dielectric layer 112 formed in step S220 may include a combination of one or more sub-dielectric layers. For example, the dielectric layer 112 may be composed of at least a first sub-dielectric layer 1121 and a second sub-dielectric layer 1122. Preferably, in one embodiment, the first sub-dielectric layer 1121 may be a silicon oxide material and the second sub-dielectric layer 1122 may be selected from a silicon nitride or silicon oxynitride material.
In an alternative embodiment, the second sub-dielectric layer 1122 is made of a silicon nitride material, and in the present invention, the silicon nitride may be negatively charged by adjusting the silicon nitride growth process, so as to pin the sidewalls of the first trench 130 between the semiconductor island structures 110.
Further, in an alternative embodiment, the dielectric layer 112 may be used as a stop layer for a back side thinning process of the semiconductor substrate 100, and the semiconductor substrate 100 is thinned to a proper position in a subsequent process.
In one embodiment of the present invention, the implementation method of semiconductor epitaxy is used to form an image sensor, where the semiconductor island structure 110 is used to form a pixel unit.
In an alternative embodiment, the first epitaxial layer 111 includes at least a sub-epitaxial layer doped with an ion type opposite to that of the semiconductor island structure 110, so as to form a PN junction structure of the pixel unit.
Specifically, in an alternative embodiment, as shown in fig. 5, the forming the first epitaxial layer 111 in step S210 includes the following steps:
step S2111: a low doped or intrinsic semiconductor is epitaxially grown on the surface of the side wall of the semiconductor island-shaped structure 110, so as to form a first sub-epitaxial layer 1111 of the first epitaxial layer 111;
step S2112: a second sub-epitaxial layer 1112 having an opposite doping ion type to the semiconductor island structure 110 is epitaxially formed on the surface of the first sub-epitaxial layer 1111 to form a PN junction structure of the pixel unit.
In another alternative embodiment, the forming the first epitaxial layer 111 in step S210 includes the steps of:
step S2121: a semiconductor material with a first doping type is epitaxially grown on the surface of the side wall of the semiconductor island-shaped structure, and a third sub-epitaxial layer 1113 of the first epitaxial layer 111 is formed;
step S2122: etching to remove the third sub-epitaxial layer on the bottom surface of the first trench between the semiconductor island structures 110 and deepen the depth of the first trench;
a low-doped or intrinsic semiconductor is epitaxially grown on the surface of the third sub-epitaxial layer, so that a fourth sub-epitaxial layer is formed;
and epitaxially growing a semiconductor material with the opposite doping type to the first doping type on the surface of the fourth sub-epitaxial layer to form a fifth sub-epitaxial layer so as to form the PN junction structure of the pixel unit.
In the present invention, the semiconductor substrate 100 is etched to form semiconductor island structures 110 arranged in an array, and in an alternative embodiment, the semiconductor island structures 110 may be polygonal. On the basis, in an alternative embodiment, at least upper portions of the semiconductor island structures 110 are connected to each other by a connection structure 120 at the corners of the polygon, so as to reduce defects generated in a subsequent epitaxial process.
For example, alternatively, the semiconductor island structures 110 may be quadrilateral, and at least upper portions of the semiconductor island structures 110 are connected to each other by connection structures 120 at four corners of the quadrilateral. Further, in this embodiment, the connection structure 120 may be selected to be an X-shaped or four-corner connected ring structure.
In an alternative embodiment of the present invention, when the semiconductor substrate 100 is etched, the bottom of the connection structure 120 may be suspended by controlling the etching process conditions, so as to form the cantilever connection structure 121. Preferably, in forming the cantilever connection structure 121, the semiconductor island structure 110 and the connection structure 120 may be formed by continuing to etch the first trench 130, and a second trench 140 that is not communicated with each other may be formed between the connection structures 120; then, the width of the second grooves 140 at both sides of the connection structure is increased and communicated by the lateral isotropic etching, so as to form the cantilever connection structure 121.
In the actual operation process, a plasma with isotropic etching capability may be formed by dry etching, and then the plasma is used to etch the sidewalls of the semiconductor island structure 110 and the connection structure 120 until the bottoms of the connection structures are communicated, so as to form the cantilever connection structure 121. In an alternative embodiment, a chemical dry etching process may be used to etch, where the etching mode has a high selectivity to silicon and silicon oxide, and the etching rate is generally selected to be 30-300A/min, and the temperature is not more than 135 ℃. The chemical dry etching process can repair plasma damage caused by the previous process and optimize the roughness of the surface of the groove.
In another alternative embodiment, the isotropic etching of the sidewall of the epitaxial layer may also be performed by wet etching, and preferably, the sidewalls of the semiconductor island structures 110 and the connection structures 120 may be wet etched using a solution of hydrofluoric acid, nitric acid, ammonia water, or the like. The etching temperature is preferably 20-40 ℃, and the etching time can be adjusted according to the thickness required to be etched.
Preferably, the bottom of the cantilever connection 121 may be smoothed by post-processing the grooves on both sides of the connection 120. By smoothing the bottom of the cantilever connection structure 121, byproducts generated during etching can be effectively removed, and a dielectric layer, a hard mask, etc. on the surface can be removed. The post-treatment can be preferably performed by adopting mixed solution of chemical reagents such as hydrofluoric acid, hydrogen peroxide, ammonia water, hydrochloric acid and the like, wherein the etching time is preferably 30-300 seconds, and the etching temperature is preferably 20-40 ℃.
The invention also provides a semiconductor device which is suitable for adopting the realization method of the semiconductor epitaxy in the forming process. The semiconductor device may be an image sensor, wherein the semiconductor island structure may serve as a pixel cell of the image sensor, after which optical and electrical isolation between the pixel cells is formed.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Thus, the embodiments should be considered in all respects as illustrative and not restrictive. Furthermore, it is evident that the word "comprising" does not exclude other elements or steps, and that the word "a" or "an" does not exclude a plurality. The elements recited in the apparatus claims may also be embodied by one element. The terms first, second, etc. are used to denote a name, but not any particular order.
Claims (21)
1. A method for implementing semiconductor epitaxy, comprising:
etching the semiconductor substrate to form semiconductor island structures arranged in an array before the grid of the semiconductor device is formed, wherein at least the upper parts of the semiconductor island structures are connected with each other through at least one connecting structure so as to reduce defects generated by a subsequent epitaxial process;
the etching semiconductor substrate forms a semiconductor island-shaped structure which is arranged in an array, and the semiconductor island-shaped structure at least comprises:
etching the semiconductor substrate at a negative angle to form a first groove;
forming a protective medium layer on the surface of the first groove;
and continuing to etch the first groove to form the semiconductor island-shaped structure and the connection structure.
2. The method of claim 1, wherein during the etching of the first trench to form the semiconductor island structure and the connection structure, the bottom of the connection structure is suspended by controlling etching process conditions to form a cantilever connection structure.
3. The method of claim 2, wherein forming the cantilever connection comprises:
continuing to etch the first groove to form the semiconductor island-shaped structure and the connection structure, and forming a second groove which is not communicated with each other between the connection structures;
and the width of the second grooves at two sides of the connecting structure is increased and communicated through lateral isotropic etching, so that the cantilever connecting structure is formed.
4. The method of claim 1, wherein when the semiconductor substrate is subjected to negative angle etching to form a first trench, a distance between adjacent connection structures is greater than a distance between adjacent semiconductor island structures, a length direction of the first trench corresponds to the connection structures, and a width direction corresponds to the semiconductor island structures.
5. The method of claim 1, wherein the etching angle in the longitudinal direction of the first trench is more negative than the etching angle in the width direction of the first trench in the island-like structure of the semiconductor when the semiconductor substrate is subjected to negative angle etching to form the first trench.
6. The method of implementing semiconductor epitaxy of claim 1, wherein the method further comprises:
forming a first epitaxial layer on the surface of the semiconductor island-shaped structure through an epitaxial process;
forming a dielectric layer on the surface of the first epitaxial layer;
removing the dielectric layer at the opening of the first groove between the semiconductor island structures;
and forming a second epitaxial layer at the opening through an epitaxial process, and closing the opening.
7. The method of claim 6, wherein the dielectric layer comprises a combination of one or more sub-dielectric layers.
8. The method of claim 7, wherein the dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer.
9. The method of claim 8, wherein the first sub-dielectric layer is silicon oxide; the second sub-dielectric layer is silicon nitride or silicon oxynitride.
10. The method of claim 8, wherein the second sub-dielectric layer is silicon nitride, and wherein the silicon nitride is negatively charged by adjusting the silicon nitride growth process to create pinning to the sidewalls of the first trench between the semiconductor islands.
11. The method of claim 6, wherein the dielectric layer is used as a stop layer for a back side thinning process of the semiconductor substrate.
12. The method of claim 1, wherein the semiconductor island is polygonal.
13. The method of claim 12, wherein at least upper portions of each of said semiconductor islands are interconnected by a connection structure at said polygonal corners to reduce defects generated by subsequent epitaxial processes.
14. The method of claim 13, wherein the semiconductor island is quadrilateral, and at least upper portions of the semiconductor islands are connected to each other by connection structures at four corners of the quadrilateral, so as to reduce defects generated in subsequent epitaxial processes.
15. The method of claim 1, wherein the method of semiconductor epitaxy is used to form an image sensor and the semiconductor island structure is used to form a pixel cell.
16. The method of claim 6, wherein the first epitaxial layer comprises at least a sub-epitaxial layer of a dopant ion type opposite to that of the semiconductor island structure to form a PN junction structure of the pixel cell.
17. The method of claim 16, wherein forming the first epitaxial layer comprises:
a low doped or intrinsic semiconductor is epitaxially grown on the surface of the side wall of the semiconductor island-shaped structure, and a first sub-epitaxial layer of the first epitaxial layer is formed;
and forming a second sub-epitaxial layer with the opposite doping ion type to the semiconductor island-shaped structure on the surface of the first sub-epitaxial layer in an epitaxial manner to form a PN junction structure of the pixel unit.
18. The method of claim 16, wherein performing epitaxy on a surface of a sidewall of the semiconductor island to form a first epitaxial layer comprises:
a semiconductor material of a first doping type is epitaxially grown on the surface of the side wall of the semiconductor island-shaped structure, and a third sub-epitaxial layer of the first epitaxial layer is formed;
etching to remove the third sub-epitaxial layer on the bottom surface of the first groove between the semiconductor island structures and deepen the depth of the first groove;
a low-doped or intrinsic semiconductor is epitaxially grown on the surface of the third sub-epitaxial layer, so that a fourth sub-epitaxial layer is formed;
and epitaxially growing a semiconductor material with the opposite doping type to the first doping type on the surface of the fourth sub-epitaxial layer to form a fifth sub-epitaxial layer so as to form the PN junction structure of the pixel unit.
19. The method of claim 2, wherein the trenches on both sides of the connection structure are post-processed to smooth the bottom of the cantilever connection structure.
20. The method of claim 13, wherein when the semiconductor island structure is a quadrangle, the connection structure is an X-shape or a ring structure with four corners connected.
21. A semiconductor device characterized in that a method for realizing semiconductor epitaxy according to claims 1 to 20 is employed in the formation process.
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