CN117219639A - Method for realizing semiconductor epitaxy and semiconductor device - Google Patents
Method for realizing semiconductor epitaxy and semiconductor device Download PDFInfo
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- CN117219639A CN117219639A CN202210620842.1A CN202210620842A CN117219639A CN 117219639 A CN117219639 A CN 117219639A CN 202210620842 A CN202210620842 A CN 202210620842A CN 117219639 A CN117219639 A CN 117219639A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 102
- 238000000034 method Methods 0.000 title claims abstract description 70
- 238000000407 epitaxy Methods 0.000 title claims abstract description 32
- 238000002955 isolation Methods 0.000 claims abstract description 51
- 238000005530 etching Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 230000001681 protective effect Effects 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000012010 growth Effects 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 230000009646 cyclic growth Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The invention provides a method for realizing semiconductor epitaxy, which comprises the following steps: etching the semiconductor substrate through at least two etching processes before the grid electrode of the semiconductor device is formed, forming semiconductor island-shaped structures which are arranged in an array mode, wherein at least the upper parts of the semiconductor island-shaped structures are connected with each other through a connecting structure, and a first groove is formed between the semiconductor island-shaped structures; forming a first epitaxial layer on the surface of the first groove through an epitaxial process, so that an opening of the first groove, the line width of which is smaller than a preset threshold value, is closed, and the line width of the opening of which the line width is larger than the preset threshold value is reduced but not completely closed; filling a medium through an opening at the position where the line width of the first groove is larger than a preset threshold value, and forming an isolation medium layer on the surface of the first epitaxial layer; and forming a second epitaxial layer on the surfaces of the semiconductor substrate, the first epitaxial layer and the isolation medium layer through epitaxy by an epitaxy process, so that the first groove is sealed. The method can lead the lateral epitaxy of the bottom to be more uniform, increase the process window, simplify the process flow and improve the performance of the device.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for implementing semiconductor epitaxy and a semiconductor device.
Background
In the formation of semiconductor devices, processes such as etching, ion implantation, epitaxy, etc. are often required for the semiconductor substrate. Taking an image sensor as an example, a photodiode in a photosensitive area of the image sensor is used to convert an optical signal into an electrical signal, wherein the photosensitive unit can be formed by ion implantation, epitaxy, or the like. However, as the pixel size continues to decrease, there are some drawbacks in the process, and the thickness of the resist mask used is also increased in order to ensure blocking of high energy P-type dopant ions in non-isolated regions. The mask is easily inclined in the steps of development, ion implantation and the like, so that the effect of normal ion implantation cannot be achieved in a pixel region or an isolation region in a subsequent process, and the performance of a final image sensor is affected. In addition, ion implantation has other disadvantages such as excessive defects, uneven distribution of implanted dopant ions, etc., and the ion implantation requires a high temperature annealing process to repair the defects, which is liable to damage the logic devices already formed.
A new process for forming the photosensitive cells of image sensors is by deep trench etching and selective epitaxy to form PN junctions or PIN junctions, as is mentioned in both CN204632760U and CN113224093 a. However, this method has certain drawbacks. During epitaxial growth, the deep trenches must be grown upwards from the bottoms of the deep trenches, otherwise lattice dislocation is easy to occur, meanwhile, the line width of the intersections of the deep trenches for isolating the pixel units is large (as shown in fig. 1, the length of the line width AC of the intersections of the deep trenches is larger than the line width AB of the deep trenches), voids are easy to form during epitaxial growth, and dislocation at the interface of the epitaxial layer is caused. This dislocation can further lead to defects in the subsequent epitaxial growth process, affecting the performance and yield of devices disposed in that region.
On the basis, the epitaxial effect is improved by forming a cantilever structure to connect each pixel unit, but in the original scheme, after the cantilever structure is completed, a mode of removing a side wall dielectric protection layer, directly extending and closing a groove is generally adopted, and the line width of the upper part of the groove is smaller, so that the upper part of the groove is easy to be closed prematurely, and the lateral epitaxial thickness of the lower part of the groove is thinner. The thickness of the side wall epitaxial layer is increased by a cyclic growth mode of continuous back etching, and the problem of inconsistent upper and lower line widths of the column body is caused.
Disclosure of Invention
The invention aims to provide a method for realizing semiconductor epitaxy, which comprises the following steps:
etching the semiconductor substrate through at least two etching processes before the grid electrode of the semiconductor device is formed, forming semiconductor island-shaped structures which are arranged in an array mode, wherein at least the upper parts of the semiconductor island-shaped structures are connected with each other through a connecting structure, and a first groove is formed between the semiconductor island-shaped structures;
forming a first epitaxial layer on the surface of the first groove through an epitaxial process, so that an opening of the first groove, the line width of which is smaller than a preset threshold value, is closed, and the line width of the opening of which the line width is larger than the preset threshold value is reduced but not completely closed;
filling a medium through an opening at the position where the line width of the first groove is larger than a preset threshold value, and forming an isolation medium layer on the surface of the first epitaxial layer;
and forming a second epitaxial layer on the surfaces of the semiconductor substrate, the first epitaxial layer and the isolation medium layer through epitaxy by an epitaxy process, so that the first groove is sealed.
Further, a lateral PN junction structure is formed when the first epitaxial layer is formed.
Further, after the isolation dielectric layer is formed on the surface of the first epitaxial layer, before the second epitaxial layer is formed, the method further comprises:
removing the isolation medium layer at the opening of the first groove with the line width larger than a preset threshold value through back etching;
further, the forming the second epitaxial layer includes:
and forming a device layer on the second epitaxial layer through an epitaxial process.
Further, the isolation medium layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride and polysilicon.
Further, the isolation dielectric layer is made of one or more of silicon oxide, silicon nitride and silicon oxynitride, and the bottom of the isolation dielectric layer is used as a stop layer for thinning the semiconductor substrate when the back surface process of the semiconductor is carried out later.
Further, the isolation medium layer is made of silicon oxide and/or polysilicon, and serves as a lateral pinning layer.
Further, the at least two etching processes include:
etching the semiconductor substrate according to a preset photoetching pattern to form a second groove;
forming a protective medium layer on the surface of the second groove;
etching the protective dielectric layer at the bottom of the second groove, and continuing etching the semiconductor substrate to form a third groove;
and isotropically etching the third groove to form the first groove with the bottoms mutually communicated, so that the connecting structure forms a cantilever beam connecting structure.
Further, the semiconductor island structure is polygonal.
Further, at least upper portions of the semiconductor island structures are connected to each other by the connection structure located in the middle of each side of the polygon.
Further, the semiconductor island structures are quadrilateral, and at least the upper parts of the semiconductor island structures are connected with each other through the connecting structures positioned at the midpoints of the sides of the quadrilateral.
Further, the implementation method of the semiconductor epitaxy is used for forming an image sensor, and the semiconductor island-shaped structure is used for forming a pixel unit.
Further, the grooves on two sides of the connecting structure are subjected to post-treatment, so that the bottom of the cantilever beam connecting structure is smooth.
The invention also provides a semiconductor device, and the method for realizing the semiconductor epitaxy is adopted in the forming process.
According to the scheme, the novel semiconductor epitaxy realization method and the semiconductor device are provided, the epitaxy part in the groove is not influenced by whether the position of the groove is closed or not for the first time, the epitaxy can be controlled through the position with wider line width (such as intersection of the grooves), the lateral epitaxy of the bottom is more uniform, and the process window is increased. In addition, the gap generated after epitaxy is smaller, and the pixel unit with smaller size is suitable to be formed. The medium filled in the groove can also be used as a pinning layer and a thinning stop layer of the back process, so that the process flow is simplified, and the performance of the device is improved.
Drawings
Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments which follows, which is read in connection with the accompanying drawings.
FIG. 1 is a schematic diagram of a prior art scheme of line width non-uniformity at a trench intersection;
fig. 2 is a schematic structural diagram of a semiconductor epitaxial method according to the present invention;
fig. 3 to 13 are schematic views of structures of semiconductor islands and connection structures according to various embodiments of the present invention.
In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout the different drawings.
Detailed Description
The invention aims to provide a method for realizing semiconductor epitaxy, which concretely comprises the following steps:
before forming the grid electrode of the semiconductor device, etching the semiconductor substrate 100 through at least two etching processes to form semiconductor island structures 110 arranged in an array, wherein at least the upper parts of the semiconductor island structures 110 are connected with each other through a connecting structure 120, and a first groove 130 is formed between the semiconductor island structures 110, as shown in fig. 2, wherein a-a ', B-B ', and C-C ' identify different cross-sectional directions in subsequent fig. 3-10;
then, forming a first epitaxial layer 140 on the surface of the first trench 130 through an epitaxial process, so that the opening of the first trench 130 with the line width smaller than a preset threshold value is closed, and the line width of the opening of the first trench with the line width larger than the preset threshold value is reduced but not completely closed;
filling a medium through an opening of the first trench 130 where the line width is greater than a preset threshold value, and forming an isolation medium layer 150 on the surface of the first epitaxial layer 140;
a second epitaxial layer 160 is formed by epitaxial process on the semiconductor substrate 100, the first epitaxial layer 140, and the surface of the isolation dielectric layer 150 to form a low doped and/or undoped semiconductor material, so as to seal the first trench 130.
Preferably, the first epitaxial layer 140 includes at least a portion of the semiconductor substrate 100 with a doping type opposite to that of the semiconductor substrate 100, and forms a lateral PN junction structure with the semiconductor substrate 100.
Specifically, in an alternative embodiment of the present invention, first, at least two etching processes are performed by:
step S110: etching the semiconductor substrate 100 according to a preset photolithography pattern to form a second trench 131, as shown in fig. 3;
step S120: forming a protective dielectric layer 132 on the surface of the second trench 131, as shown in fig. 4;
step S130: etching the protective dielectric layer 132 at the bottom of the second trench 131, and continuing to etch the semiconductor substrate 100 to form a third trench 133, as shown in fig. 5;
step S140: and isotropically etching the third trench 133 to form the first trench 130 with mutually communicated bottoms, so that the connection structure 120 forms a cantilever connection structure, as shown in fig. 6.
Preferably, in step S110, the hard mask layer 200 may be formed prior to the surface of the semiconductor substrate 100, and then etched according to a predetermined photolithography pattern, as shown in fig. 3.
Preferably, in such an embodiment, the upper portion of the semiconductor substrate 100 includes the intrinsic semiconductor substrate layer 101, and the forming of the second trench 131 in step S110 may take the interface of the intrinsic semiconductor substrate layer 101 and the bottom substrate layer as a stop layer, as shown in fig. 3.
Further, after step S110, the sidewalls of the second trench 131 may be laterally etched, so that the second trench 131 extends a portion below the hard mask layer 200, as shown in fig. 3.
Preferably, the protective dielectric layer 132 formed in step S120 may be selected from one or more of silicon oxide, silicon nitride, or silicon oxynitride.
In an alternative embodiment, in step S140, a chemical dry etching process may be used to perform etching, where the etching mode has a higher selectivity to silicon and silicon oxide, and the etching rate is generally selected to be 30-300A/min, and the temperature is not more than 135 ℃. The chemical dry etching process can repair plasma damage caused by the previous process and optimize the roughness of the surface of the groove.
In another alternative embodiment, the isotropic etching of the sidewall of the epitaxial layer may also be performed by wet etching, and preferably, the sidewalls of the semiconductor island structures 110 and the connection structures 120 may be wet etched using a solution of hydrofluoric acid, nitric acid, ammonia water, or the like. The etching temperature is preferably 20-40 ℃, and the etching time can be adjusted according to the thickness required to be etched.
Preferably, the formation of the cantilever beam connecting structure is performed by post-processing the grooves on both sides of the connecting structure 120, so that the bottom of the cantilever beam connecting structure is smooth. The bottom of the cantilever beam connecting structure formed by the scheme is quite sharp, so that the bottom of the cantilever beam connecting structure is smooth, and the subsequent filling of the epitaxial layer is facilitated. The bottom of the cantilever connection structure can be smoothed to effectively remove byproducts generated in the etching process, and remove a dielectric layer, a hard mask and the like on the surface. The post-treatment can be preferably performed by adopting mixed solution of chemical reagents such as hydrofluoric acid, hydrogen peroxide, ammonia water, hydrochloric acid and the like, wherein the etching time is preferably 30-300 seconds, and the etching temperature is preferably 20-40 ℃.
On the basis, after the first trench 130 is formed, a first epitaxial layer 140 is formed on the surface of the first trench 130 through an epitaxial process, so that an opening at the position where the line width of the first trench 130 is smaller than a preset threshold value is closed, and the line width of the opening at the position where the line width is larger than the preset threshold value is reduced but not completely closed.
In one embodiment, the first epitaxial layer 140 includes at least a first sub-epitaxial layer 141 and a second sub-epitaxial layer 142, and specifically is formed by:
step S211: epitaxial the intrinsic semiconductor on the surface of the first trench 130 to form a first sub-epitaxial layer 141, as shown in fig. 7;
step S212: a second sub-epitaxial layer 142 is formed by epitaxially growing a semiconductor material having a doping type opposite to that of the semiconductor substrate 100 on the surface of the first sub-epitaxial layer 141, specifically, when the second sub-epitaxial layer 142 is formed, the opening of the first trench 130 with a line width smaller than a preset threshold may be closed, and the line width of the opening with a line width larger than the preset threshold may be reduced but not completely closed, as shown in fig. 8.
Alternatively, when the second sub-epitaxial layer 142 is formed, it is also possible to not implement the sealing, and then form a third sub-epitaxial layer 143 on the surface of the second sub-epitaxial layer 142 by epitaxy of the intrinsic semiconductor, where the line width of the first trench 130 is smaller than the preset threshold value, the third sub-epitaxial layer 143 seals the opening, and the line width of the opening where the line width is larger than the preset threshold value is reduced but not completely sealed.
In another alternative embodiment, the semiconductor material having the opposite doping type to the semiconductor substrate 100 may be directly epitaxially formed on the surface of the first trench 130, so that the opening where the line width of the first trench 130 is smaller than the preset threshold is closed, and the line width of the opening where the line width is larger than the preset threshold is reduced but not completely closed.
Further, in this embodiment, the epitaxial layer formed by epitaxy and having the opposite doping type to the semiconductor substrate 100 may not be sealed, and a third sub-epitaxial layer 143 (not shown) is formed on the surface of the epitaxial layer by epitaxy of the intrinsic semiconductor, where the line width of the first trench 130 is smaller than the preset threshold, and the line width of the opening where the line width is larger than the preset threshold is reduced but not completely sealed by the third sub-epitaxial layer 143.
After the first epitaxial layer 140 is formed, a dielectric layer 150 is further formed on the surface of the first epitaxial layer 140 by filling a dielectric through the opening where the line width of the first trench 130 is greater than a preset threshold, as shown in fig. 9.
Preferably, the isolation dielectric layer 150 may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and polysilicon. Further, if the material of the isolation dielectric layer 150 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride, the bottom of the isolation dielectric layer 150 may be used as a stop layer for thinning the semiconductor substrate 100 during the subsequent semiconductor back side process. In another alternative embodiment, if the isolation dielectric layer 150 is made of silicon oxide and/or polysilicon, the isolation dielectric layer 150 may serve as a lateral pinning layer.
Specifically, in one embodiment, the isolation dielectric layer 150 includes a polysilicon layer therein, and in this embodiment, after the first epitaxial layer 140 is formed, the isolation dielectric layer 150 is formed by:
step S310: filling oxide through the opening of the first trench 130 where the line width is greater than a preset threshold value, forming a first isolation oxide layer 151 on the surface of the first epitaxial layer 140, and keeping the opening open;
step S320: filling polysilicon material through the opening of the first trench 130 where the line width is greater than a preset threshold value, so as to form an isolation polysilicon layer 160;
step S330: etching back the isolation polysilicon layer 160 to remove the isolation polysilicon layer 160 on the upper part of the semiconductor substrate;
step S340: forming a second isolation oxide layer 152 on the surface of the isolation polysilicon layer 160;
step S350: forming an isolation nitride layer 153 on the surface of the second isolation oxide layer 152;
step S360: forming a third isolation oxide layer 154 on the surface of the isolation nitride layer 153, as shown in fig. 10;
step S370: etching back the third isolation oxide layer 154 and the isolation nitride layer 154, and reserving a part of the third isolation oxide layer 154 and the isolation nitride layer 153 at the opening where the line width of the first trench 130 is greater than a preset threshold, as shown in fig. 11;
step S380: the third isolation oxide layer 154 and the first isolation oxide layer 151 on the surface of the semiconductor substrate 100 are removed as shown in fig. 12.
Through the above steps, the oxide layer and the nitride layer which remain are used as the isolation dielectric layer 150.
Preferably, after forming the isolation dielectric layer 150, the isolation dielectric layer 150 at the opening where the line width of the first trench 130 is greater than the preset threshold may be removed by etching back, and then the second epitaxial layer 160 is formed, as shown in fig. 13.
The second epitaxial layer 160 is formed by epitaxially depositing a low-doped and/or undoped semiconductor material on the surfaces of the semiconductor substrate 100, the first epitaxial layer 140, and the isolation dielectric layer 150, so that the first trench 130 is closed.
Preferably, the second epitaxial layer 160 is formed as the device layer 300 of the semiconductor device. Thereafter, the device layer 300 may be planarized and devices such as gates may be disposed therein.
In a preferred embodiment, the semiconductor island structure 110 may be polygonal. Preferably, at least upper portions of the semiconductor islands 110 are connected to each other by the connection structures 120 located in the middle of sides of the polygon. Preferably, the semiconductor island structure 110 is a quadrilateral, and at least upper portions of the semiconductor island structures 120 are connected to each other by the connection structures 120 located at midpoints of sides of the quadrilateral.
In one embodiment, the semiconductor epitaxy implementation method of the present invention is used to form an image sensor, the semiconductor island structure 110 is used to form a photosensitive region of a pixel unit, and the first epitaxial layer and the second epitaxial layer can be used as isolation structures between the pixel units.
The invention also provides a semiconductor device which is suitable for adopting the realization method of the semiconductor epitaxy in the forming process. The semiconductor device may be an image sensor, wherein the semiconductor island structure may serve as a pixel cell of the image sensor, after which optical and electrical isolation between the pixel cells is formed.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Thus, the embodiments should be considered in all respects as illustrative and not restrictive. Furthermore, it is evident that the word "comprising" does not exclude other elements or steps, and that the word "a" or "an" does not exclude a plurality. The elements recited in the apparatus claims may also be embodied by one element. The terms first, second, etc. are used to denote a name, but not any particular order.
Claims (14)
1. A method for implementing semiconductor epitaxy, comprising:
etching the semiconductor substrate through at least two etching processes before the grid electrode of the semiconductor device is formed, forming semiconductor island-shaped structures which are arranged in an array mode, wherein at least the upper parts of the semiconductor island-shaped structures are connected with each other through a connecting structure, and a first groove is formed between the semiconductor island-shaped structures;
forming a first epitaxial layer on the surface of the first groove through an epitaxial process, so that an opening of the first groove, the line width of which is smaller than a preset threshold value, is closed, and the line width of the opening of which the line width is larger than the preset threshold value is reduced but not completely closed;
filling a medium through an opening at the position where the line width of the first groove is larger than a preset threshold value, and forming an isolation medium layer on the surface of the first epitaxial layer;
and forming a second epitaxial layer on the surfaces of the semiconductor substrate, the first epitaxial layer and the isolation medium layer through epitaxy by an epitaxy process, so that the first groove is sealed.
2. The method of claim 1, wherein a lateral PN junction structure is formed when the first epitaxial layer is formed.
3. The method for implementing semiconductor epitaxy according to claim 1, wherein after forming the isolation dielectric layer on the surface of the first epitaxial layer, before forming the second epitaxial layer, the method further comprises:
and removing the isolation medium layer at the opening part of the first groove line width larger than a preset threshold value through back etching.
4. The method of claim 3, wherein forming the second epitaxial layer comprises:
and forming a device layer on the second epitaxial layer through an epitaxial process.
5. The method of claim 1, wherein the isolation dielectric layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, and polysilicon.
6. The method of claim 5, wherein the isolation dielectric layer is made of one or more of silicon oxide, silicon nitride and silicon oxynitride, and the bottom of the isolation dielectric layer is used as a stop layer for thinning the semiconductor substrate during the subsequent semiconductor back side process.
7. The method of claim 5, wherein the isolation dielectric layer comprises silicon oxide and/or polysilicon, and the isolation dielectric layer is used as a lateral pinning layer.
8. The method of claim 1, wherein the at least two etching processes comprise:
etching the semiconductor substrate according to a preset photoetching pattern to form a second groove;
forming a protective medium layer on the surface of the second groove;
etching the protective dielectric layer at the bottom of the second groove, and continuing etching the semiconductor substrate to form a third groove;
and isotropically etching the third groove to form the first groove with the bottoms mutually communicated, so that the connecting structure forms a cantilever beam connecting structure.
9. The method of claim 1, wherein the semiconductor island is polygonal.
10. The method of claim 9, wherein at least upper portions of each of said semiconductor islands are interconnected by said connection structures intermediate sides of said polygon.
11. The method of claim 10, wherein the semiconductor islands are quadrilateral, and at least upper portions of the semiconductor islands are connected to each other by the connection structures at midpoints of sides of the quadrilateral.
12. The method of claim 1, wherein the method of semiconductor epitaxy is used to form an image sensor and the semiconductor island structure is used to form a pixel cell.
13. The method of claim 8, wherein the trenches on both sides of the connection structure are post-processed to smooth the bottom of the cantilever connection structure.
14. A semiconductor device characterized in that a method for realizing semiconductor epitaxy according to claims 1 to 13 is employed in the formation process.
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