CN115706120A

CN115706120A - Semiconductor epitaxy realization method and semiconductor device

Info

Publication number: CN115706120A
Application number: CN202111063355.1A
Authority: CN
Inventors: 赵立新
Original assignee: Galaxycore Shanghai Ltd Corp
Current assignee: Galaxycore Shanghai Ltd Corp
Priority date: 2021-08-13
Filing date: 2021-09-10
Publication date: 2023-02-17

Abstract

The invention provides a method for realizing semiconductor epitaxy, which specifically comprises the following steps: before a grid electrode of the semiconductor device is formed, a semiconductor substrate is etched to form semiconductor island-shaped structures which are arranged in an array mode, and at least the upper portions of the semiconductor island-shaped structures are connected with each other through at least one connecting structure, so that defects generated in a subsequent epitaxial process are reduced. The invention also provides an image sensor, and the semiconductor epitaxy realization method is adopted in the forming process. According to the method for realizing the semiconductor epitaxy, the upper parts of the semiconductor island structures which are arranged in an array are fixed, so that the process defects generated in the subsequent epitaxy step are reduced, and the performance of a semiconductor device is improved.

Description

Semiconductor epitaxy realization method and semiconductor device

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a method for implementing semiconductor epitaxy and a semiconductor device.

Background

In the process of forming a semiconductor device, processes such as etching, ion implantation, epitaxy, etc. are often required to be performed on a semiconductor substrate. Taking an image sensor as an example, photodiodes in the photosensitive area of the image sensor are used to convert optical signals into electrical signals, wherein the photosensitive cells can be formed by ion implantation or epitaxy.

The conventional process of forming a PN junction or a PIN junction in a photosensitive cell of an image sensor is by means of ion implantation. In the case of decreasing pixel size, in order to make each pixel continue to provide similar performance (especially full well capacity) as the original large-sized pixel, the N-type doping depth of the photosensitive region in the pixel must be increased to maintain a proper photosensitive volume. However, as the depth of the implant in the photosensitive region increases, the P-type isolation between pixels is required to be deeper and deeper, and the implantation energy for performing the isolation P-type doping also needs to be increased. The thickness of the resist mask used is also increased in order to ensure blocking of the high energy P-type dopant ions in the non-isolated regions. The mask is easy to incline in the steps of developing, ion implantation and the like, so that the pixel region or the isolation region in the subsequent process cannot achieve the effect of normal ion implantation, and the performance of the final image sensor is influenced. This problem is addressed in 2009 CN101677079B, where multiple ion implantation masks are used to try to solve the problem, but this solution is too complicated in process, high in cost, and not suitable for practical application. In addition, ion implantation has other disadvantages, such as excessive defects, uneven distribution of implanted dopant ions, etc., and the ion implantation requires a high temperature annealing process to repair the defects, which easily damages the formed logic devices.

A new process for forming a PN junction or PIN junction by deep trench etching and selective epitaxy is used in the photosensitive cell of an image sensor, as mentioned in patents CN204632760U and CN 113224093A. The selective epitaxy has wide reaction temperature range (400-1150 ℃) and controllable doping concentration (generally 10℃) ¹³ ~10 ²¹ at/cc), flexible doping type (both N type and P type), and less defects. The scheme needs to firstly carry out deep trench etching on a semiconductor substrate and then selectively epitaxially grow a P-type or N-type semiconductor material. The scheme can finely control the size of the PN junction, realize a lateral PN junction structure and ensure that the doping concentration is uniform and controllable. However, this method also has certain disadvantages:

1. the epitaxial growth must grow from the bottom of the deep trench upward, otherwise, lattice dislocation easily occurs, and meanwhile, the line width of the intersection of the deep trench for isolating the pixel unit is large (as shown in fig. 1, the length of the line width AC of the intersection of the trench is larger than the line width AB of the trench), and voids are easily formed during the epitaxial growth and cause dislocation at the interface of the epitaxial layer. The dislocation can further cause defects in the subsequent epitaxial growth process, thereby affecting the performance and yield of devices disposed in the region;

2. if the deep groove is directly filled up from the bottom when the epitaxial process is carried out, the effect of optical isolation among pixels is difficult to achieve due to the fact that no gap exists in the middle of the deep groove;

3. if the notch is directly sealed from the upper part of the deep groove by adopting an epitaxial process, although a gap in the deep groove can be formed to achieve the optical isolation of the pixel unit, because the epitaxial growth does not start from the bottom, some dislocation defects can be generated, and the performance of a subsequent sensor is further influenced;

4. in both the schemes 1 and 2, in the process of isolating the deep trench in the pixel unit of the back-illuminated image sensor, the back deep trench isolation is not easy to align with the front isolation region of the pixel unit, which causes the deviation of the isolation region and affects the performance of the pixel unit.

Disclosure of Invention

The invention aims to provide a method for realizing a semiconductor epitaxy, which specifically comprises the following steps.

Before a grid of the semiconductor device is formed, the semiconductor substrate is etched to form semiconductor island-shaped structures which are arranged in an array mode, and at least the upper portions of the semiconductor island-shaped structures are connected with each other through at least one connecting structure, so that defects generated in a subsequent epitaxial process are reduced.

Further, the semiconductor island-shaped structure is polygonal.

Further, at least upper parts of the semiconductor island-shaped structures are connected with each other through the connecting structures positioned at the corners of the polygons, so that defects generated in a subsequent epitaxial process are reduced.

Furthermore, the semiconductor island-shaped structures are quadrilateral, and at least the upper parts of the semiconductor island-shaped structures are connected with each other through connecting structures positioned at four corners of the quadrilateral, so that defects generated in a subsequent epitaxial process are reduced.

Further, in the process of etching the semiconductor substrate, the bottom of the connecting structure is suspended by controlling the etching process conditions to form a cantilever beam connecting structure.

Further, in the process of etching the semiconductor substrate, after the cantilever beam connecting structure is formed, the semiconductor substrate is continuously etched, so that the size of the section of the subsequent part of the island-shaped semiconductor structure is kept unchanged.

Further, the forming the suspension beam connection structure includes:

etching the semiconductor substrate to form the semiconductor island-shaped structure and the connecting structure, wherein the grooves on two sides of the connecting structure are not communicated with each other;

and increasing the width of the grooves on two sides of the connecting structure through lateral isotropic etching to form the cantilever beam connecting structure.

Further, the implementation method of the semiconductor epitaxy is used for forming an image sensor, and the semiconductor island-shaped structures are used for forming pixel units.

Further, the method for implementing the semiconductor epitaxy is used for forming an image sensor, the semiconductor island-shaped structure is used for forming a pixel unit, and after the semiconductor island-shaped structure and the connection structure are formed by etching the semiconductor substrate, the method further comprises the following steps:

and forming a first epitaxial layer by at least one epitaxial process, closing the upper part of the groove between the semiconductor island structures, and forming a gap between the first epitaxial layers on the side walls of the semiconductor island structures so as to realize optical isolation between the pixel units of the image sensor.

epitaxially forming a first epitaxial layer on the side wall of the semiconductor island-shaped structure, and keeping a groove between the semiconductor island-shaped structures in an open state;

forming an isolation medium on the surface of the first epitaxial layer and/or filling the isolation medium in the groove between the semiconductor island structures;

performing back etching on the isolation medium to expose the first epitaxial layer at the opening of the trench between the semiconductor island structures;

and epitaxially forming a second epitaxial layer on the surface of the first epitaxial layer, so that the groove openings between the island-shaped semiconductor structures are closed, and a gap is formed between the first epitaxial layers on the side walls of the island-shaped semiconductor structures, so as to realize optical isolation between the pixel units of the image sensor.

Further, the first epitaxial layer at least comprises a sub-epitaxial layer with the ion doping type opposite to that of the semiconductor island-shaped structure, so that a PN junction structure of the pixel unit is formed.

Further, the forming the first epitaxial layer by at least one epitaxial process includes:

extending a low-doped or intrinsic semiconductor on the surface of the side wall of the semiconductor island structure to form a first sub epitaxial layer of the first epitaxial layer;

and epitaxially forming a second sub epitaxial layer with the doping ion type opposite to that of the semiconductor island structure on the surface of the first sub epitaxial layer to form a PN junction structure of the pixel unit.

Further, the epitaxially forming a first epitaxial layer on the sidewall surface of the semiconductor island structure includes:

extending a semiconductor material of a first doping type on the surface of the side wall of the semiconductor island structure to form a third sub-epitaxial layer of the first epitaxial layer;

etching to remove the third sub epitaxial layer on the bottom surface of the groove between the semiconductor island structures and etching to deepen the depth of the groove;

extending a low-doped or intrinsic semiconductor on the surface of the third sub-epitaxial layer to form a fourth sub-epitaxial layer;

and extending a semiconductor material with the opposite doping type to the first doping type on the surface of the fourth sub-epitaxial layer to form a fifth sub-epitaxial layer so as to form a PN junction structure of the pixel unit.

And further, post-processing the grooves on two sides of the connecting structure to smooth the bottom of the suspension beam connecting structure.

Further, the etching the semiconductor substrate to form the semiconductor island-shaped structures arranged in an array includes:

forming a hard mask layer on the semiconductor substrate;

etching the hard mask layer according to a preset photoetching pattern;

and etching the semiconductor substrate according to the hard mask layer to form the semiconductor island-shaped structure and the connecting structure.

Further, when the semiconductor island-shaped structure is a quadrilateral, the connection structure is an X-shaped or a ring-shaped structure with four corners connected.

Further, before the step of continuing to etch the semiconductor substrate, the method further comprises the steps of:

and forming a first protective dielectric layer on the side wall surfaces of the semiconductor island structure and the connecting structure so as to protect the connecting structure during continuous etching.

Further, the suspension beam connecting structure is formed by suspending the bottom of the connecting structure, and comprises:

etching the semiconductor substrate to form the semiconductor island-shaped structure and the connecting structure, wherein the bottom of the connecting structure is not communicated;

forming a second protective dielectric layer on the surfaces of the side walls of the semiconductor island-shaped structure and the connecting structure so as to protect the connecting structure when the etching is continued;

and continuously etching to ensure that the grooves on the two sides of the connecting structure are etched in a laterally same-polarity manner, so that the width of the grooves on the two sides of the connecting structure is increased, and the cantilever beam connection is formed.

And forming a second protective dielectric layer on the surfaces of the side walls of the semiconductor island-shaped structure and the connecting structure so as to protect the connecting structure when the etching is continued.

The invention also provides a semiconductor device which is suitable for adopting the implementation method of the semiconductor epitaxy in the forming process.

The invention provides a novel method for realizing semiconductor epitaxy by the scheme, and forms an image sensor by combining the scheme. Firstly, the invention ensures that at least upper parts of the island-shaped semiconductor structures are provided with a certain degree of interconnection structures, particularly cantilever beam connection structures, in the etching process through unique structural design, so that a lateral PN junction structure can be extended in the deep groove, and an optically isolated gap structure is reserved. And because the semiconductor island structures are connected with each other, lattice mismatch does not exist among the island structures in the subsequent epitaxial process, so that the defect of epitaxial growth when the groove is sealed in the subsequent epitaxial process is greatly reduced, and the dark current and white spots of the image sensor are effectively reduced. Secondly, when the deep groove is epitaxially filled, a gap is reserved in the groove, the gap can be opened in the subsequent wafer back thinning process, and a back groove for isolating optical crosstalk of the pixel unit can be directly formed. Because the lateral PN junction structure of the photosensitive unit of the image sensor and the back groove for isolating the optical crosstalk of the pixel unit are formed by one-time exposure process and have the characteristic of self-alignment, the size of the pixel unit of the image sensor can be increased to the maximum extent, and the alignment problem caused by adopting a multi-step exposure process in the traditional scheme is solved. Thirdly, the invention forms a high-concentration N-type epitaxial layer in the deep trench epitaxy first, then forms an intrinsic or low-doped epitaxial layer, and then carries out a high-concentration P-type epitaxial layer. The structure can reduce the depletion voltage of the PN junction and keep the Full Well Capacity (FWC) of the pixel unit unchanged; or under the condition of keeping the depletion voltage of the PN junction unchanged, the full-well capacity of the pixel unit is greatly increased. Finally, in the preferred scheme of the invention, fine epitaxial process control can be carried out, the size of the PN junction can be controlled in the application of an image sensor and the like, and the doping concentration is uniform and controllable. Meanwhile, structures such as a photosensitive unit of a similar image sensor can be formed before a logic device of a grid electrode is formed, and damage to the device caused by high-temperature epitaxy can be avoided.

Drawings

Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments thereof, which proceeds with reference to the accompanying drawings.

FIG. 1 is a schematic diagram illustrating a line width inconsistency at a trench intersection in a conventional scheme;

FIGS. 2-8 are schematic views of the island-shaped semiconductor structures and the connecting structures of the present invention in different embodiments;

FIGS. 9 to 24 are schematic structural views illustrating the application of the semiconductor epitaxial method of the present invention to an image sensor;

fig. 25 to 26 are schematic structural diagrams of a protective dielectric layer according to an embodiment of the invention.

In the drawings, like or similar reference numbers indicate like or similar devices (modules) or steps throughout the different views.

Detailed Description

The invention provides a method for realizing semiconductor epitaxy, which can effectively solve the problem of epitaxy defects caused by inconsistent line width at the staggered part of a groove in a semiconductor device.

Specifically, in the embodiment of the present invention, before the gate of the semiconductor device is formed, the semiconductor substrate 100 is etched to form the semiconductor island structures 200 arranged in an array, and at least upper portions of the semiconductor island structures 200 are connected to each other by at least one connection structure 210, so as to reduce defects generated by a subsequent epitaxial process, as shown in fig. 2.

Specifically, in an alternative embodiment, as shown in fig. 3, a hard mask layer 110 is first formed on the semiconductor substrate 100; thus, the hard mask layer 110 is etched according to a preset photoetching pattern; and etching the semiconductor substrate 100 according to the hard mask layer 110 to form the semiconductor island structure 200 and the connection structure 210.

Preferably, the semiconductor substrate 100 may be composed of two parts, i.e., a first substrate 1001 and a second substrate 1002, and the first substrate 1001 doped with N-type and the second substrate 1002 doped with P-type may be selected to form a semiconductor substrate.

Preferably, the etching may be performed by using inductively coupled plasma etching or capacitively coupled plasma etching, in which the hard mask layer 110 (typically, a silicide, such as silicon oxide or silicon nitride) is first opened, and then the trench profile between the semiconductor island structures 200 may be controlled by adjusting parameters of a single cycle at each stage of multiple cycles through multiple repeated cyclic etching. Preferably, at least one etching process and one deposition process are included in a single cycle. The etching process can be adjusted by parameters such as the period of a single cycle, the time ratio of the etching process in the single cycle, the pressure of the etching chamber and the like.

Preferably, SF may be employed in a single cycle ₆ 、O ₂ 、SiF ₄ Etching the semiconductor substrate 100 by using the gases, wherein the gas flow is preferably 200 to 2000SCCM, and the deposition process gas in a single cycle is preferably a compound containing fluorine, carbon and hydrogen, such as: c ₄ F ₈ 、CHF ₃ And so on.

As shown in fig. 2, in a preferred embodiment, the semiconductor island structures 200 may be polygonal. Preferably, the connection structures 210 may extend from corners of each of the semiconductor island-like structures 200, i.e., at least upper portions of each of the semiconductor island-like structures 200 are connected to each other by the connection structures 210 located at the corners of the polygon.

Further, as shown in fig. 4 and 5, the semiconductor island structures 200 are quadrilateral, and at least upper portions of the semiconductor island structures 200 are connected to each other through connection structures 210 located at four corners of the quadrilateral. The connecting structure 210 may be an X-shaped or a ring-shaped structure with four corners connected.

As shown in fig. 3, the semiconductor islands 200 are connected to each other through a connection structure 210, the connection structure 210 is at least located at an upper portion of the semiconductor island 200, and the semiconductor islands 200 can be connected to each other through the connection structure 210 from top to bottom according to actual requirements.

In an alternative embodiment, as shown in fig. 6, during the etching process of the semiconductor substrate 100, by controlling the etching process conditions, the bottom of the connection structure 210 may be suspended, that is, only the upper portions of the semiconductor islands 200 are connected to each other, that is, connected by the suspended beam connection structure 211.

Preferably, when the cantilever connection structure 211 is formed, the semiconductor substrate 100 may be etched first to form the semiconductor island structure 200 and the connection structure 210, and at this time, trenches on two sides of the connection structure 210 are not communicated with each other; then, the width of the trench on both sides of the connection structure 210 is increased by laterally isotropic etching, so as to form the suspended beam connection structure 211. That is, the bottom or the middle of the trench is widened, so that the bottoms of the trenches on the two sides of the connection structure 210 are communicated with each other, and the connection structure 210 is suspended. In two possible embodiments, as shown in fig. 6 and 7, the cross section of the groove may be a trapezoid or a bowl-like structure, according to the schematic section of the broken line AA' in fig. 4.

Wherein, preferably, the lateral isotropic etching process comprises dry etching or wet etching having isotropy. In an actual operation process, plasma with isotropic etching capability may be formed by dry etching, and then the plasma is used to etch the sidewalls of the semiconductor island-shaped structure 200 and the connection structure 210 until the bottoms of the connection structures are communicated, so as to form the cantilever connection structure 211.

In an optional embodiment, a chemical dry etching process can be adopted for etching, the etching mode has a high selection ratio of silicon to silicon oxide, the etching rate is generally selected to be 30 to 300A/min, and the temperature is not more than 135 ℃. The chemical dry etching process can repair plasma damage caused by the previous process and optimize the roughness of the surface of the groove.

In another alternative embodiment, the isotropic etching of the epitaxial layer sidewall may also be implemented by wet etching, and preferably, the sidewalls of the semiconductor island structure 200 and the connection structure 210 may be wet etched by using a solution of hydrofluoric acid, nitric acid, ammonia water, or the like. The etching temperature is preferably 20 to 40 ℃, and the etching time can be adjusted according to the required etching thickness.

In another optional implementation manner, in the process of etching the semiconductor substrate 100, the suspension beam connection structure 211 is formed by etching, and then the semiconductor substrate 100 is etched continuously, so that the size of the subsequent partial cross section of the semiconductor island-shaped structure 200 is kept unchanged, and a trapezoidal and rectangular combined structure is formed. That is, a shallow trench is formed by etching, and the cantilever beam connection structure 211 is formed, and then the semiconductor substrate 100 is etched to make the trench deeper, as shown in fig. 8, which is a schematic cross-sectional view according to a dotted line AA' in fig. 4 in this embodiment. Preferably, in this manner, a first protective dielectric layer 215 can be formed prior to the sidewalls of the semiconductor island structures 200 and the connection structures 210, as shown in fig. 25, to protect the connection structures 210 when etching is continued.

In another alternative embodiment, preferably, the semiconductor substrate 100 may be etched first to form the semiconductor island structure 200 and the connection structure 210, and the bottom of the connection structure 210 is not connected; then, forming a second protective dielectric layer 216 on the sidewall surfaces of the semiconductor island structures 200 and the connection structures 210, as shown in fig. 26, to protect the connection structures 210 during the etching process; after that, the etching may be continued, so that the trenches on both sides of the connection structure 210 are etched in a laterally isotropic manner, so that the width of the trenches on both sides of the connection structure 210 is increased, and the cantilever beam connection structure 211 is formed.

And forming a second protective dielectric layer on the surfaces of the side walls of the semiconductor island-shaped structure and the connecting structure so as to protect the connecting structure when etching is continued.

Preferably, the bottom of the cantilever beam connection structure 211 formed by the above scheme is often relatively sharp, and on this basis, the trenches on both sides of the connection structure 210 may be post-processed in the subsequent process, so that the bottom of the cantilever beam connection structure 211 is smooth, which is beneficial to the subsequent epitaxial layer filling, as shown in fig. 6, 7, and 8. By smoothing the bottom of the catenary connection structure 211, byproducts generated in the etching process can be effectively removed, and a dielectric layer, a hard mask and the like on the surface can be removed. During post-treatment, mixed solution of chemical reagents such as hydrofluoric acid, hydrogen peroxide, ammonia water and hydrochloric acid can be preferably adopted for wet etching, the etching time is preferably 30 to 300 seconds, and the etching temperature is preferably 20 to 40 ℃.

In a specific embodiment of the present invention, the method for implementing the semiconductor epitaxy is to be used for forming an image sensor, that is, the semiconductor island structure 200 is to be used for forming a pixel unit, and after the semiconductor island structure 200 and the connection structure 210 are formed by etching the semiconductor substrate 100, the method further includes:

the optical isolation between the image sensor pixel units can be realized by forming the first epitaxial layer 300 through at least one epitaxial process and closing the upper part of the trench between the semiconductor island structures 200, and forming a gap 310 between the first epitaxial layer 300 on the sidewall of the semiconductor island structures, as shown in fig. 9, according to the schematic cross-sectional view of the dotted line CC' in fig. 4 in this embodiment.

In another embodiment, after etching the semiconductor substrate 100 to form the semiconductor island structure 200 and the connection structure 210, optical isolation between the image sensor pixel units can be achieved by:

first, epitaxially forming a first epitaxial layer 300 on the sidewalls of the semiconductor island structures 200 and keeping the trenches between the semiconductor island structures 200 in an open state, as shown in fig. 10, which is a schematic cross-sectional view of this embodiment according to the dashed line CC' in fig. 4;

then, an isolation dielectric 320 is formed on the surface of the first epitaxial layer 300 and/or the isolation dielectric 320 is filled in the trench between the semiconductor island structures 200, as shown in fig. 11, which is a schematic cross-sectional view of this embodiment according to the dashed line CC' in fig. 4;

preferably, after the filling, the isolation dielectric 320 may be subjected to a chemical mechanical polishing process, and the hard mask layer 110 is removed, so that the semiconductor substrate 100 is exposed, as shown in fig. 12, which is a schematic cross-sectional view of such an embodiment according to the dashed line CC' in fig. 4.

Then, the isolation dielectric 320 is etched back to expose the first epitaxial layer 300 at the trench openings between the semiconductor island structures 200, as shown in fig. 13, which is a schematic cross-sectional view of this embodiment according to a dashed line CC in fig. 4. At this time, the isolation dielectric 320 at the bottom of the trench is also etched to be thinned.

A second epitaxial layer 330 is epitaxially formed on the surface of the first epitaxial layer 300, so as to close the trench openings between the semiconductor island structures 200 and form a gap 310, as shown in fig. 14, which is a schematic cross-sectional view according to a dashed line CC' in fig. 4 in this embodiment, thereby achieving optical isolation between the pixel units of the image sensor.

Optionally, the first epitaxial layer 300 may include at least a sub-epitaxial layer with a doping ion type opposite to that of the semiconductor island structure 200, and the sub-epitaxial layer and the semiconductor island structure 200 may form a PN junction structure of the pixel unit, so as to also achieve electrical isolation between the pixel units.

Specifically, in an alternative embodiment, after etching to form the semiconductor island structure 200 shown in fig. 15 (according to the schematic cross-sectional view of the dashed line CC' in fig. 4), the forming the first epitaxial layer 300 by at least one epitaxial process includes:

forming a first sub-epitaxial layer 410 of the first epitaxial layer 300 by epitaxy of a low-doped or intrinsic semiconductor on the sidewall surface of the semiconductor island structure 200, as shown in fig. 16; and then, epitaxially forming a second sub-epitaxial layer 420 with the doping ion type opposite to that of the semiconductor island structure 200 on the surface of the first sub-epitaxial layer 410 to form a PN junction structure of the pixel unit. The first sub-epitaxial layer 410 may implement buffering in the PN junction as shown in fig. 17. Fig. 16 and 17 are schematic cross-sectional views of the embodiment according to the dashed line CC 'in fig. 4, and fig. 18 is a schematic cross-sectional view of the embodiment according to the dashed line BB' in fig. 4.

On this basis, further, after etching to form the semiconductor island structure 200 as shown in fig. 19 (according to the schematic cross-sectional view of the dashed line CC' in fig. 4), the first epitaxial layer 300 can also be formed by:

firstly, extending a semiconductor material of a first doping type (i.e., P-type or N-type) on the sidewall surface of the semiconductor island structure 200 to form a third sub-epitaxial layer 430 of the first epitaxial layer 300, as shown in fig. 20;

then, etching to remove the third sub-epitaxial layer 430 on the bottom surface of the trench between the semiconductor island structures 200, and etching to deepen the depth of the trench, as shown in fig. 21;

extending a low-doped or intrinsic semiconductor on the surface of the third sub-epitaxial layer 430 to form a fourth sub-epitaxial layer 440, as shown in fig. 22;

a semiconductor material with a doping type opposite to the first doping type (i.e. opposite to the doping ion type of the third sub-epitaxial layer 430) is epitaxially grown on the surface of the fourth sub-epitaxial layer 440 to form a fifth sub-epitaxial layer 450, so that the fifth sub-epitaxial layer 450 and the third sub-epitaxial layer 430 can form a PN junction structure of the pixel unit, as shown in fig. 23. Fig. 20 to 23 are schematic cross-sectional views in the direction of the dotted line CC 'in fig. 4 in this embodiment, and fig. 24 is a schematic cross-sectional view in the direction of the dotted line BB' in fig. 4 in this embodiment.

In an alternative embodiment, in order to achieve electrical isolation between the semiconductor island structures 200 in the connection structure 210, semiconductor ions of a type opposite to that of the doped ions of the semiconductor island structures 200 may be implanted in the connection structure 210 by means of ion implantation, or in a preferred embodiment, the line width of the connection structure 210 is controlled, and the semiconductor ions of a type opposite to that of the doped ions of the semiconductor island structures 200 are diffused into the connection structure 210 by a heat treatment after the first epitaxial layer 300 is epitaxial.

The invention also provides a semiconductor device which is suitable for adopting the implementation method of the semiconductor epitaxy in the forming process. The semiconductor device may be an image sensor, wherein the semiconductor island structures may serve as pixel cells of the image sensor, followed by optical and electrical isolation between the pixel cells.

Through the scheme, the invention provides a novel method for realizing semiconductor epitaxy, and through a unique structural design, a certain degree of interconnection structure is ensured between at least the upper parts of island-shaped semiconductor structures in the etching process, so that the defects generated by growth at the junction of deep grooves in the subsequent epitaxy process are reduced, and the dark current and white spots of an image sensor are effectively reduced. On the other hand, the invention can carry out fine epitaxial process control in the preferable scheme, can control the size of the PN junction in the application of an image sensor and the like, and has uniform and controllable doping concentration. Meanwhile, structures such as a photosensitive unit of a similar image sensor can be formed before a logic device of a grid electrode is formed, and damage to the device caused by high-temperature epitaxy can be avoided.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. It will furthermore be evident that the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. Several elements recited in the apparatus claims may also be implemented by one element. The terms first, second, etc. are used to denote names, but not any particular order.

Claims

1. A method for realizing semiconductor epitaxy is characterized by comprising the following steps:

before a grid electrode of the semiconductor device is formed, a semiconductor substrate is etched to form semiconductor island-shaped structures which are arranged in an array mode, and at least the upper portions of the semiconductor island-shaped structures are connected with each other through at least one connecting structure, so that defects generated in a subsequent epitaxial process are reduced.

2. A method of semiconductor epitaxy according to claim 1 characterised in that the semiconductor island structures are polygonal.

3. A method of semiconductor epitaxy as claimed in claim 2, wherein at least upper portions of the semiconductor island structures are connected to each other by connecting structures located at corners of the polygons to reduce defects generated by a subsequent epitaxy process.

4. A method of semiconductor epitaxy according to claim 3, wherein the semiconductor island structures are quadrilateral, and at least upper parts of the semiconductor island structures are connected with each other through connecting structures located at four corners of the quadrilateral, so as to reduce defects generated in a subsequent epitaxy process.

5. The method for implementing semiconductor epitaxy according to claim 1, wherein during etching the semiconductor substrate, the bottom of the connection structure is suspended by controlling etching process conditions to form a suspended beam connection structure.

6. A semiconductor epitaxy realization method as claimed in claim 5, characterized in that during the etching of the semiconductor substrate, after the formation of the suspended beam connection structure, the etching of the semiconductor substrate is continued so that the size of the cross section of the subsequent part of the semiconductor island structure remains unchanged.

7. A method of implementing semiconductor epitaxy as claimed in claim 5 wherein the forming a suspended beam connection structure comprises:

8. The method of claim 1, wherein the semiconductor epitaxy is used to form an image sensor and the semiconductor island structures are used to form pixel cells.

9. The method of claim 8, wherein the method of forming the semiconductor epitaxy is used to form an image sensor, the semiconductor island structures are used to form pixel cells, and after etching the semiconductor substrate to form the semiconductor island structures and the connection structures, further comprising:

10. The method for implementing semiconductor epitaxy as claimed in claim 8, wherein the method for implementing semiconductor epitaxy is used for forming an image sensor, the semiconductor island structures are used for forming pixel units, and after etching the semiconductor substrate to form the semiconductor island structures and the connection structures, the method further comprises:

11. The method for realizing the semiconductor epitaxy according to any one of claims 9 to 10, wherein the first epitaxial layer at least comprises a sub-epitaxial layer with a doping ion type opposite to that of the semiconductor island structure so as to form a PN junction structure of the pixel unit.

12. A method of implementing semiconductor epitaxy as claimed in claim 8, wherein the forming the first epitaxial layer by at least one epitaxial process comprises:

extending a low-doped or intrinsic semiconductor on the surface of the side wall of the semiconductor island-shaped structure to form a first sub-epitaxial layer of the first epitaxial layer;

and epitaxially forming a second sub-epitaxial layer with the ion doping type opposite to that of the semiconductor island-shaped structure on the surface of the first sub-epitaxial layer so as to form a PN junction structure of the pixel unit.

13. A method of implementing semiconductor epitaxy as claimed in claim 8, wherein the epitaxially forming a first epitaxial layer on the surface of the sidewall of the semiconductor island structure comprises:

etching to remove the third sub-epitaxial layer on the bottom surface of the groove between the semiconductor island-shaped structures and deepen the depth of the groove;

14. A method of semiconductor epitaxy as claimed in claim 5 wherein the trenches on both sides of the link are post-processed to smooth the bottom of the suspended beam link.

15. A method of implementing semiconductor epitaxy as claimed in claim 1, wherein etching the semiconductor substrate to form semiconductor island structures arranged in an array comprises:

forming a hard mask layer on the semiconductor substrate;

etching the hard mask layer according to a preset photoetching pattern;

16. A method of semiconductor epitaxy according to claim 4, characterised in that when the semiconductor island-like structure is a quadrilateral, the linking structure is an X-shaped or a ring-shaped structure with four corners linked.

17. A semiconductor device, characterized in that, in the forming process, the method for realizing the semiconductor epitaxy according to claims 1 to 16 is adopted.

18. A method of implementing semiconductor epitaxy as claimed in claim 6, further comprising, before said continuing to etch the semiconductor substrate, the steps of:

and forming a first protective dielectric layer on the side wall surfaces of the semiconductor island-shaped structure and the connecting structure so as to protect the connecting structure when the etching is continued.

19. A method of implementing semiconductor epitaxy as claimed in claim 5 wherein the suspending the bottom of the connection structure to form a suspended beam connection structure comprises:

continuing etching to enable the grooves on the two sides of the connecting structure to be etched in a lateral isotropic manner, so that the width of the grooves on the two sides of the connecting structure is increased, and the cantilever beam connection is formed;

20. A semiconductor device, characterized in that a method of implementing a semiconductor epitaxy as claimed in claims 18 to 19 is used in the formation.