CN108091662B - Manufacturing method for improving depth-width ratio of ion implantation region - Google Patents
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
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Abstract
The invention discloses a manufacturing method for improving the aspect ratio of an ion implantation area, which comprises the following steps: step one, forming a first isolation layer and a first polycrystalline silicon layer on the front side of a semiconductor substrate in sequence; step two, forming a second dielectric layer; step three, photoetching is carried out to open the area outside the ion implantation area and to implant ions into the second dielectric layer outside the ion implantation area; step four, carrying out selective polycrystalline silicon epitaxial growth to form a second polycrystalline silicon layer; fifthly, removing the second dielectric layer; step six, using the second polycrystalline silicon layer as a barrier layer to carry out ion implantation to form an ion implantation area with required depth; and seventhly, removing the second polysilicon layer, the first polysilicon layer and the first isolation layer. The invention can make the width and the depth of the ion implantation area separately adjustable, thereby improving the depth-to-width ratio of the ion implantation area.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for increasing the aspect ratio of an ion implantation region.
Background
In a CMOS Image Sensor (CIS) chip manufacturing process, in order to improve Image definition and realize high pixel per unit area, it is necessary to implement isolation between each pixel unit on a pattern with a high aspect ratio by using high-energy ion implantation, which is generally referred to as P-type high-energy ion implantation, and a P-type well with a deep junction is formed by the P-type high-energy ion implantation. In the high energy implantation process of the P-type well, which is a substitute layer of the CIS process developed along moore's law, the line width (space) has been required to be less than 0.17 micrometers, and in order to reach the junction depth required by the P-type well, a barrier layer of more than 3 micrometers needs to be adopted to block the high energy implantation of the P-type well, so as to prevent the ion implantation of the P-type well from affecting the photodiode of the pixel unit, which is located outside the P-type well and is isolated by the P-type well.
As shown in fig. 1A to fig. 1C, a method for manufacturing a conventional ion implantation region is illustrated; first, as shown in fig. 1A, a photoresist 102 is formed on a surface of a semiconductor substrate such as a silicon substrate 101, and the photoresist 102 has a thickness of 3 μm or more, and serves as a barrier layer for subsequent high-energy ion implantation. Next, as shown in fig. 1B, the region where ion implantation is required is opened by performing photolithography and development, and the opened region of the photoresist 102 is shown by a reference numeral 201 in fig. 1B. Next, as shown in fig. 1C, high-energy ion implantation 202 is performed using the pattern of the photoresist 102 as a mask to form an ion implantation region 103.
As can be seen from the above, in the conventional process, a photoresist is usually used as a barrier layer for high energy implantation, and a photoresist with a thickness of 3 μm or more means that the aspect ratio of the photoresist pattern corresponding to KRF (KRF) excimer laser is over 10:1, the more rigorous the depth of field requirement of the pattern is, the more easily the pattern collapses, and aiming at the photoresist process, the existing technology can only achieve the limit of 0.17 micron.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a manufacturing method for improving the aspect ratio of an ion implantation region, which can obtain the ion implantation region with smaller line width and deeper junction depth.
In order to solve the above technical problems, the manufacturing method for improving the aspect ratio of the ion implantation region provided by the invention comprises the following steps:
providing a semiconductor substrate for forming an ion implantation area, and sequentially forming a first isolation layer and a first polycrystalline silicon layer on the front surface of the semiconductor substrate, wherein the first isolation layer is isolated between the semiconductor substrate and the first polycrystalline silicon layer and is used for protecting the surface of the semiconductor substrate when the first polycrystalline silicon layer is removed; the first polysilicon layer is used as a seed layer of a polysilicon epitaxial process of a subsequent second polysilicon layer.
And secondly, forming a second dielectric layer on the surface of the first polycrystalline silicon layer, wherein the thickness of the second dielectric layer is set according to the implantation energy required by the depth of the formed ion implantation area, so that the implantation energy corresponding to the ion implantation area does not penetrate through the subsequently formed second polycrystalline silicon layer with the same thickness as the second dielectric layer.
Step three, photoetching is carried out to open the area outside the ion implantation area and protect the formation area of the ion implantation area, and then the second dielectric layer is etched to remove the second dielectric layer outside the ion implantation area until the surface of the second polycrystalline silicon layer is exposed and the second dielectric layer in the formation area of the ion implantation area is reserved; and the width of the second reserved dielectric layer is the same as that of the ion implantation area.
Performing selective polysilicon epitaxial growth to form a second polysilicon layer, wherein the selective polysilicon epitaxial growth process of the second polysilicon layer uses the first polysilicon layer as a seed layer and is self-aligned to a region where the second dielectric layer is removed and is formed outside the ion implantation region; and then, flattening the second polysilicon layer by adopting a chemical mechanical polishing process so as to enable the thickness of the second polysilicon layer to be the same as that of the second dielectric layer.
And fifthly, removing the second dielectric layer.
And sixthly, performing ion implantation by taking the second polycrystalline silicon layer as a barrier layer to form the ion implantation region with the required depth, wherein the width of the ion implantation region is defined by the photoetching process in the third step, the depth of the ion implantation region is determined by the implantation energy of the ion implantation in the sixth step, and the thickness of the barrier layer is independent of the setting of the width of the ion implantation region while ensuring the implantation energy of the ion implantation region, so that the width and the depth of the ion implantation region are separately adjustable, and the aspect ratio of the ion implantation region can be improved.
And seventhly, removing the second polycrystalline silicon layer, the first polycrystalline silicon layer and the first isolation layer.
The further improvement is that in the step one, the semiconductor substrate is a silicon substrate; the first isolation layer is composed of a first oxidation layer and a second nitridation layer which are sequentially overlapped.
In a further improvement, the first oxide layer is formed by a furnace tube process, and the first oxide layer is formed on the front surface of the semiconductor substrate and is also formed on the back surface of the semiconductor substrate.
The second nitride layer is formed by adopting a furnace tube process, and is formed on the front surface of the semiconductor substrate and also formed on the back surface of the semiconductor substrate.
The first polycrystalline silicon layer is formed by adopting a furnace tube process, and is formed on the front surface of the semiconductor substrate and also formed on the back surface of the semiconductor substrate.
In a further improvement, the thickness of the first oxide layer is 100 angstroms; the thickness of the second nitride layer is 1000-1500 angstroms; the thickness of the first polysilicon layer is 1000 angstroms to 2000 angstroms.
In a further improvement, the second dielectric layer is an oxide layer formed by chemical vapor deposition.
The further improvement is that the thickness of the second dielectric layer is more than 3 microns, and the implantation energy of the ion implantation area in the sixth step is more than 950 kev.
In a further improvement, the width of the ion implantation region is less than 0.17 micron.
The further improvement is that the ion implantation region is a P-type ion implantation region for realizing isolation between the photosensitive diodes of the adjacent pixel units of the CMOS image sensor, the integration level of the pixels of the CMOS image sensor is improved by reducing the width of the P-type ion implantation region, and the isolation performance between the photosensitive diodes of the pixel units is improved by increasing the junction depth of the P-type ion implantation region.
The further improvement is that after the second dielectric layer is formed in the second step, an etching barrier layer for etching the second dielectric layer is formed on the surface of the second dielectric layer, and the etching barrier layer is amorphous carbon or organic carbon.
In a further improvement, the etch stop layer has a thickness of 1 micron.
The further improvement is that the third step is as follows:
and 31, forming a photoresist pattern by adopting a reverse phase mask process or a negative photoresist process to define the ion implantation area, wherein the photoresist pattern only covers the formation area of the ion implantation area, and the photoresist outside the ion implantation area is developed and removed.
And 32, etching the etching barrier layer by taking the photoresist pattern as a mask.
And step 33, removing the photoresist pattern.
And step 34, etching the second dielectric layer by taking the etching barrier layer as a mask.
And step 35, removing the etching barrier layer.
And step 36, removing the polymer by adopting an etching process.
In a further improvement, the etching of the etch stop layer in step 32 is a dry etch and the etching gas comprises oxygen and sulfur dioxide.
In step 34, the second dielectric layer is etched by a dry etching method, and etching gases include C4F8, C4F6, and C5F 8.
In step 35, the etching barrier layer is removed by dry etching using an etching gas as oxygen.
And step 36, wet etching is carried out by adopting sulfuric acid hydrogen peroxide and ammonia water hydrogen peroxide to remove the polymer.
And the further improvement is that in the fifth step, hydrofluoric acid is adopted to carry out wet etching to remove the second dielectric layer.
The further improvement is that in the seventh step, the polycrystalline silicon on the front and back sides of the semiconductor substrate is removed by using a mixed solution of nitric acid and hydrofluoric acid; removing the second nitride layer on the front and back sides of the semiconductor substrate by using phosphoric acid; and removing the first oxide layer on the front side and the back side of the semiconductor substrate by using hydrofluoric acid.
According to the invention, the region outside the ion implantation region is opened and the formation region of the ion implantation region is protected by the photoetching process in the third step, and the method which is opposite to the method that the region of the ion implantation region is directly opened by the photoetching process in the prior art is adopted, namely, the photoetching reverse pattern definition process is adopted; the photoetching reverse pattern definition process is combined with the removal of the second dielectric layer outside the ion implantation area and the selective polycrystalline silicon epitaxial growth is carried out in the area where the second dielectric layer is removed, so that a second polycrystalline silicon layer can be formed in a self-aligning mode in the area outside the ion implantation area, the second polycrystalline silicon layer can be used as a self-aligning etching mask to remove the second dielectric layer remained in the ion implantation area, and therefore an opening structure of the ion implantation area defined by the second polycrystalline silicon layer is formed, and the second polycrystalline silicon layer can be used as a barrier layer to carry out high-energy ion implantation to form a required ion implantation area; in this way, the line width of the ion implantation area is directly defined by adopting the photoetching reverse pattern in the third step, and the small line width can be defined without etching the photoresist or the dielectric layer with high thickness with small line width. The thickness of the second dielectric layer is not limited by the line width of the pattern when the second dielectric layer outside the small line width pattern is etched, so that the thickness of the second dielectric layer is independent of the line width, namely the width, of the ion implantation area, the thickness of the finally formed barrier layer of the second polycrystalline silicon layer is independent of the width of the ion implantation area, and the thickness of the barrier layer of the second polycrystalline silicon layer determines the maximum value of the implantation energy of the ion implantation area and further determines the junction depth of the ion implantation area.
When the method is applied to the formation of the isolated P-type ion implantation region, namely the common P-type trap, between the photosensitive diodes for forming adjacent pixel units in the CIS, the line width of the P-type ion implantation region of the CIS can reach below 0.17 micrometer, the aspect ratio of the P-type ion implantation region can exceed 10:1, and the defect that the aspect ratio of a photoresist pattern corresponding to krypton difluoride (KRF) excimer laser in the prior art exceeds 10 is overcome: 1, the pattern is easy to collapse, and breaks through the defect that the line width of a P-type ion implantation area of the CIS in the prior art can only reach the limit of 0.17 micrometer.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A-1C illustrate a conventional method for fabricating an ion implantation region;
FIG. 2 is a flow chart of a method for increasing the aspect ratio of an ion implantation region according to an embodiment of the present invention;
fig. 3A-3N are device structure diagrams in steps of a method according to an embodiment of the invention.
Detailed Description
Fig. 2 is a flowchart of a manufacturing method for increasing the aspect ratio of the ion implantation region 9 according to an embodiment of the present invention; as shown in fig. 3A to fig. 3N, which are device structure diagrams in the steps of the method according to the embodiment of the present invention, the manufacturing method for increasing the aspect ratio of the ion implantation region 9 according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 3A, providing a semiconductor substrate 1 for forming an ion implantation region 9, and sequentially forming a first isolation layer and a first polysilicon layer 4 on the front surface of the semiconductor substrate 1, wherein the first isolation layer is isolated between the semiconductor substrate 1 and the first polysilicon layer 4 and is used for protecting the surface of the semiconductor substrate 1 when the first polysilicon layer 4 is removed; the first polysilicon layer 4 serves as a seed layer for a subsequent polysilicon epitaxy process of the second polysilicon layer 8.
In the embodiment of the invention, the semiconductor substrate 1 is a silicon substrate; the first isolation layer is composed of a first oxidation layer 2 and a second nitridation layer 3 which are sequentially overlapped.
As shown in fig. 1A, the first oxide layer 2 is formed by a furnace process, and the first oxide layer 2 is formed on the front surface of the semiconductor substrate 1 and also formed on the back surface of the semiconductor substrate 1.
As shown in fig. 1B, the second nitride layer 3 is formed by a furnace process, and the second nitride layer 3 is formed on the front surface of the semiconductor substrate 1 and also formed on the back surface of the semiconductor substrate 1.
As shown in fig. 1C, the first polysilicon layer 4 is formed by a furnace process, and the first polysilicon layer 4 is formed on the front surface of the semiconductor substrate 1 and also formed on the back surface of the semiconductor substrate 1.
Preferably, the thickness of the first oxide layer 2 is 100 angstroms; the thickness of the second nitride layer 3 is 1000-1500 angstroms; the thickness of the first polysilicon layer 4 is 1000 angstroms to 2000 angstroms.
Step two, as shown in fig. 3D, a second dielectric layer 5 is formed on the surface of the first polysilicon layer 4, and the thickness of the second dielectric layer 5 is set according to the implantation energy required by the depth of the ion implantation region 9, so as to ensure that the implantation energy corresponding to the ion implantation region 9 does not penetrate through the subsequently formed second polysilicon layer 8 having the same thickness as the second dielectric layer 5.
In the embodiment of the present invention, the second dielectric layer 5 is an oxide layer formed by chemical vapor deposition. The thickness of the second dielectric layer 5 is more than 3 micrometers, and the implantation energy of the ion implantation region 9 in the sixth step is more than 950 kev.
Preferably, as shown in fig. 3E, after the second dielectric layer 5 is formed, an etching blocking layer 6 is formed on the surface of the second dielectric layer 5 when the second dielectric layer 5 is etched, where the etching blocking layer 6 is amorphous carbon (APF) or organic carbon (SOC).
The thickness of the etch stop layer 6 is 1 micron.
Step three, performing photoetching to open a region 301 outside the ion implantation region 9 and protect a formation region 302 of the ion implantation region 9, and then etching the second dielectric layer 5 to remove the second dielectric layer 5 outside the ion implantation region 9 until the surface of the second polysilicon layer 8 is exposed and the second dielectric layer 5 in the formation region 302 of the ion implantation region 9 is reserved; the width of the second dielectric layer 5 is the same as the width of the ion implantation region 9.
Preferably, the third step comprises the following sub-steps:
step 31, as shown in fig. 3F, forming a photoresist pattern 7 by using a reverse phase mask process or a negative photoresist process to define the ion implantation region 9, where the photoresist pattern 7 only covers the formation region 302 of the ion implantation region 9, and the photoresist outside the ion implantation region 9 is removed by development.
Step 32, as shown in fig. 3G, the etching barrier layer 6 is etched by using the photoresist pattern 7 as a mask.
Preferably, the etching of the etching barrier layer 6 is dry etching and the etching gas includes oxygen and sulfur dioxide.
Step 33, as shown in fig. 3G, the photoresist pattern 7 is removed.
Step 34, as shown in fig. 3G, etching the second dielectric layer 5 with the etching barrier layer 6 as a mask, thereby opening the region 301 outside the ion implantation region 9
Preferably, the etching of the second dielectric layer 5 is dry etching, and the etching gas includes C4F8, C4F6, and C5F 8.
Step 35, as shown in fig. 3H, the etching barrier layer 6 is removed.
Preferably, the etching barrier layer 6 is removed by dry etching using an etching gas as oxygen.
And step 36, removing the polymer by adopting an etching process.
Preferably, sulfuric acid hydrogen peroxide and ammonia water hydrogen peroxide are used for wet etching to remove the polymer.
Step four, as shown in fig. 3I, performing selective polysilicon epitaxial growth to form the second polysilicon layer 8, wherein the selective polysilicon epitaxial growth process of the second polysilicon layer 8 uses the first polysilicon layer 4 as a seed layer and is self-aligned to form a removed region 301 of the second dielectric layer 5 outside the ion implantation region 9; then, as shown in fig. 3J, the second polysilicon layer is planarized by a chemical mechanical polishing process so that the thickness of the second polysilicon layer 8 is the same as that of the second dielectric layer 5.
Step five, as shown in fig. 3K, the second dielectric layer 5 is removed, and the formation region 302 of the ion implantation region 9 is defined by the second polysilicon layer 8.
In the embodiment of the invention, hydrofluoric acid is adopted to perform wet etching to remove the second dielectric layer 5.
Step six, as shown in fig. 3L, performing ion implantation 303 with the second polysilicon layer 8 as a barrier layer to form the ion implantation region 9 with a desired depth, where the width of the ion implantation region 9 is defined by the photolithography process in step three, the depth of the ion implantation region 9 is determined by the implantation energy of the ion implantation in step six, and the thickness of the barrier layer is independent of the setting of the width of the ion implantation region 9 while ensuring the implantation energy of the ion implantation region 9, so that the width and the depth of the ion implantation region 9 are separately adjustable, thereby improving the aspect ratio of the ion implantation region 9.
Preferably, the width of the ion implantation region 9 is 0.17 μm or less. The ion implantation region 9 is a P-type ion implantation region 9, and is configured to implement isolation between the photosensitive diodes of the adjacent pixel units of the CMOS image sensor, improve the integration of the pixels of the CMOS image sensor by reducing the width of the P-type ion implantation region 9, and improve the isolation performance between the photosensitive diodes of the pixel units by improving the junction depth of the P-type ion implantation region 9.
And seventhly, removing the second polysilicon layer 8, the first polysilicon layer 4 and the first isolation layer.
Preferably, as shown in fig. 3M, the polycrystalline silicon 4 and 8 on the front and back surfaces of the semiconductor substrate 1 are removed using a mixed solution of nitric acid and hydrofluoric acid.
As shown in fig. 3N, the second nitride layer 3 on the front and back sides of the semiconductor substrate 1 is removed using phosphoric acid; and removing the first oxide layer 2 on the front and back surfaces of the semiconductor substrate 1 by using hydrofluoric acid.
In the embodiment of the present invention, the region outside the ion implantation region 9 is opened by the photolithography process of step three, and the formation region 302 of the ion implantation region 9 is protected, which is opposite to the method of directly opening the region of the ion implantation region 9 by the photolithography process of the prior art, that is, the photolithography reverse pattern definition process is adopted in the embodiment of the present invention; the photoetching reverse pattern definition process is combined with the removal of the second dielectric layer 5 outside the ion implantation area 9 and the selective polycrystalline silicon epitaxial growth is carried out in the area where the second dielectric layer 5 is removed, so that the second polycrystalline silicon layer 8 can be formed in a self-aligning mode and can be self-aligned with the area outside the ion implantation area 9, the second polycrystalline silicon layer 8 can be used as a self-aligning etching mask to remove the second dielectric layer 5 remained in the ion implantation area 9, and therefore an opening structure of the ion implantation area 9 defined by the second polycrystalline silicon layer 8 is formed, and the second polycrystalline silicon layer 8 can be used as a barrier layer to carry out high-energy ion implantation to form the required ion implantation area 9; in this way, the line width of the ion implantation region 9 in the embodiment of the present invention is directly defined by using the photolithography reverse pattern in step three, and the photoresist or the dielectric layer with a high thickness and a small line width does not need to be etched, so that the definition of the small line width can be realized. Because the thickness of the second dielectric layer 5 is not limited by the line width of the pattern when the second dielectric layer 5 outside the small line width pattern is etched, the thickness of the second dielectric layer 5 can be independent of the line width, namely the width, of the ion implantation area 9, the thickness of the finally formed barrier layer of the second polycrystalline silicon layer 8 can be independent of the width of the ion implantation area 9, and the thickness of the barrier layer of the second polycrystalline silicon layer 8 determines the maximum value of the implantation energy of the ion implantation area 9 and further determines the junction depth of the ion implantation area 9, the embodiment of the invention can finally enable the width and the depth of the ion implantation area 9 to be separately adjustable, thereby improving the depth-to-width ratio of the ion implantation area 9, and obtaining the ion implantation area 9 with smaller line width and deeper junction depth.
When the embodiment of the invention is applied to the formation of the P-type ion implantation region 9 for forming the isolation between the photosensitive diodes of adjacent pixel units in the CIS, namely the common P-type well, the line width of the P-type ion implantation region 9 of the CIS can reach below 0.17 micrometer, the aspect ratio of the P-type ion implantation region 9 can exceed 10:1, and the defect that the aspect ratio of the photoresist pattern 7 corresponding to krypton difluoride (KRF) excimer laser in the prior art exceeds 10 is overcome: 1, the pattern is easy to collapse, and breaks through the defect that the line width of the P-type ion implantation region 9 of the CIS in the prior art can only reach the limit of 0.17 micron.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (12)
1. A manufacturing method for improving the aspect ratio of an ion implantation area is characterized by comprising the following steps:
providing a semiconductor substrate for forming an ion implantation area, and sequentially forming a first isolation layer and a first polycrystalline silicon layer on the front surface of the semiconductor substrate, wherein the first isolation layer is isolated between the semiconductor substrate and the first polycrystalline silicon layer and is used for protecting the surface of the semiconductor substrate when the first polycrystalline silicon layer is removed; the first polysilicon layer is used as a seed layer of a polysilicon epitaxial process of a subsequent second polysilicon layer;
the semiconductor substrate is a silicon substrate; the first isolation layer consists of a first oxide layer and a second nitride layer which are sequentially stacked;
the first oxidation layer is formed by adopting a furnace tube process, and is formed on the front surface of the semiconductor substrate and also formed on the back surface of the semiconductor substrate;
the second nitride layer is formed by adopting a furnace tube process, and is formed on the front surface of the semiconductor substrate and also formed on the back surface of the semiconductor substrate;
the first polycrystalline silicon layer is formed by adopting a furnace tube process, and is formed on the front surface of the semiconductor substrate and also formed on the back surface of the semiconductor substrate;
forming a second dielectric layer on the surface of the first polycrystalline silicon layer, wherein the thickness of the second dielectric layer is set according to the implantation energy required by the depth of the ion implantation area, so as to ensure that the implantation energy corresponding to the ion implantation area does not penetrate through the subsequently formed second polycrystalline silicon layer with the same thickness as the second dielectric layer;
step three, photoetching is carried out to open the area outside the ion implantation area and protect the formation area of the ion implantation area, and then the second dielectric layer is etched to remove the second dielectric layer outside the ion implantation area until the surface of the first polycrystalline silicon layer is exposed and the second dielectric layer in the formation area of the ion implantation area is reserved; the width of the second reserved dielectric layer is the same as that of the ion implantation area;
performing selective polysilicon epitaxial growth to form a second polysilicon layer, wherein the selective polysilicon epitaxial growth process of the second polysilicon layer uses the first polysilicon layer as a seed layer and is self-aligned to a region where the second dielectric layer is removed and is formed outside the ion implantation region; then, flattening the second polycrystalline silicon by adopting a chemical mechanical polishing process so as to enable the thickness of the second polycrystalline silicon layer to be the same as that of the second dielectric layer;
fifthly, removing the second dielectric layer;
step six, carrying out ion implantation by taking the second polycrystalline silicon layer as a barrier layer to form the ion implantation region with the required depth, wherein the width of the ion implantation region is defined by the photoetching process in the step three, the depth of the ion implantation region is determined by the implantation energy of the ion implantation in the step six, and the thickness of the barrier layer is independent of the setting of the width of the ion implantation region while ensuring the implantation energy of the ion implantation region, so that the width and the depth of the ion implantation region are separately adjustable, and the aspect ratio of the ion implantation region can be improved;
and seventhly, removing the second polycrystalline silicon layer, the first polycrystalline silicon layer and the first isolation layer.
2. The method as claimed in claim 1, wherein the step of forming the second metal layer comprises: the thickness of the first oxide layer is 100 angstroms; the thickness of the second nitride layer is 1000-1500 angstroms; the thickness of the first polysilicon layer is 1000 angstroms to 2000 angstroms.
3. The method as claimed in claim 1, wherein the step of forming the second metal layer comprises: the second dielectric layer is an oxide layer formed by chemical vapor deposition.
4. The method according to claim 1 or 3, wherein the step of forming the second metal layer comprises: the thickness of the second dielectric layer is more than 3 microns, and the implantation energy of the ion implantation area in the sixth step is more than 950 kev.
5. The method according to claim 4, wherein the step of forming the second metal layer comprises: the width of the ion implantation area is less than 0.17 micrometer.
6. The method as claimed in claim 5, wherein the step of forming the second metal layer comprises: the ion implantation area is a P-type ion implantation area and is used for realizing isolation between the photosensitive diodes of adjacent pixel units of the CMOS image sensor, the integration level of the pixels of the CMOS image sensor is improved by reducing the width of the P-type ion implantation area, and the isolation performance between the photosensitive diodes of the pixel units is improved by improving the junction depth of the P-type ion implantation area.
7. The method as claimed in claim 3, wherein the step of forming the second electrode further comprises: and step two, after the second dielectric layer is formed, forming an etching barrier layer on the surface of the second dielectric layer when the second dielectric layer is etched, wherein the etching barrier layer is amorphous carbon or organic carbon.
8. The method as claimed in claim 7, wherein the step of forming the second metal layer comprises: the thickness of the etching barrier layer is 1 micron.
9. The method as claimed in claim 7, wherein the step of forming the second metal layer comprises: step three is as follows:
step 31, forming a photoresist pattern by using a reverse phase mask process or a negative photoresist process to define the ion implantation area, wherein the photoresist pattern only covers a formation area of the ion implantation area, and the photoresist outside the ion implantation area is removed by development;
step 32, etching the etching barrier layer by taking the photoresist pattern as a mask;
step 33, removing the photoresist pattern;
step 34, etching the second dielectric layer by taking the etching barrier layer as a mask;
step 35, removing the etching barrier layer;
and step 36, removing the polymer by adopting an etching process.
10. The method as claimed in claim 9, wherein the step of forming the second metal layer comprises: etching the etching barrier layer in step 32 to be dry etching, wherein etching gas comprises oxygen and sulfur dioxide;
in step 34, the second dielectric layer is etched by a dry etching method, and etching gases include C4F8, C4F6 and C5F 8;
in step 35, removing the etching barrier layer by dry etching with etching gas as oxygen;
and step 36, wet etching is carried out by adopting sulfuric acid hydrogen peroxide and ammonia water hydrogen peroxide to remove the polymer.
11. The method as claimed in claim 3, wherein the step of forming the second electrode further comprises: and fifthly, removing the second dielectric layer by adopting hydrofluoric acid to perform wet etching.
12. The method as claimed in claim 1, wherein the step of forming the second metal layer comprises: removing the polysilicon on the front and back surfaces of the semiconductor substrate by using a mixed solution of nitric acid and hydrofluoric acid in the seventh step; removing the second nitride layer on the front and back sides of the semiconductor substrate by using phosphoric acid; and removing the first oxide layer on the front side and the back side of the semiconductor substrate by using hydrofluoric acid.
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