CN117203742A - Field effect transistor, manufacturing method thereof and integrated circuit - Google Patents
Field effect transistor, manufacturing method thereof and integrated circuit Download PDFInfo
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- CN117203742A CN117203742A CN202180096515.4A CN202180096515A CN117203742A CN 117203742 A CN117203742 A CN 117203742A CN 202180096515 A CN202180096515 A CN 202180096515A CN 117203742 A CN117203742 A CN 117203742A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The application provides a field effect transistor, a manufacturing method thereof and an integrated circuit, wherein the field effect transistor can comprise: a first cold source, a second cold source, a channel, a gate, and a gate dielectric layer. The first cold source pole includes: the semiconductor device comprises a first doped layer, a second doped layer and a first conductor layer, wherein the first doped layer is in contact with a channel. The second cold source electrode comprises: a third doped layer, a fourth doped layer, and a second conductor layer, the third doped layer being in contact with the channel. The first doping layer and the third doping layer belong to the same doping type, the second doping layer and the fourth doping layer belong to the same doping type, and the first doping layer and the second doping layer belong to different doping types. By arranging the first cold source electrode and the second cold source electrode in the field effect transistor and adjusting the carrier state density of the first cold source electrode or the second cold source electrode, the subthreshold swing of the field effect transistor can be reduced, and further the working voltage of the integrated circuit is reduced, so that the power consumption of the integrated circuit is lower.
Description
The present application relates to the field of semiconductor technology, and in particular, to a field effect transistor, a method for manufacturing the same, and an integrated circuit.
With the continuous development of electronic technology, the trend of integrated circuits has been changed from pursuing performance and integration level to mainly reduce power consumption, and the most effective method for reducing power consumption is to reduce the operating voltage Vdd. An integrated circuit generally includes a field effect transistor (metal oxide semiconductor field effect transistor, MOSFET), which is in an off-state (or subthreshold state) when the gate voltage of the field effect transistor is below a threshold voltage, and at this time, there is a trace leakage current between the source and the drain, which is referred to as a subthreshold current. When the drain current is changed by an order of magnitude, the increment of the required gate voltage is called sub-threshold swing (SS), the sub-threshold swing is related to factors such as device structure and temperature, and the smaller the sub-threshold swing is, the larger the working speed of the field effect transistor in the sub-threshold state is.
The traditional field effect transistor realizes the switch by adjusting the thermionic emission of the channel barrier, the subthreshold current is an exponential function related to the Boltzmann constant, and the subthreshold swing cannot be smaller than 60mV/dec at room temperature because electrons meet the Boltzmann distribution characteristic. In order to maintain a large switching ratio I of the field effect transistor on /I off The operating voltage Vdd must be many times the subthreshold swing, where I on Representing the on-state current of the field effect transistor, I off Representing the off-state current of the field effect transistor. If the subthreshold swing is unchanged, the working voltage Vdd is reduced, which can cause on-state electricityStream I on Becomes smaller and the performance of the device deteriorates. Therefore, due to the limitation of the subthreshold swing of the field effect transistor, the operating voltage of the integrated circuit is difficult to reduce, and further, the power consumption of the integrated circuit is difficult to continue to reduce.
Disclosure of Invention
The application provides a field effect transistor, a manufacturing method thereof and an integrated circuit, which are used for reducing subthreshold swing of the field effect transistor, further reducing working voltage of the integrated circuit and enabling power consumption of the integrated circuit to be lower.
In a first aspect, embodiments of the present application provide a field effect transistor, which may include: the semiconductor device comprises a first cold source electrode, a second cold source electrode, a channel positioned between the first cold source electrode and the second cold source electrode, a grid electrode and a grid electrode dielectric layer positioned between the channel and the grid electrode. The first cold source pole includes: the semiconductor device comprises a first doped layer, a second doped layer and a first conductor layer positioned between the first doped layer and the second doped layer, wherein the first doped layer is in contact with a channel. The second cold source electrode comprises: a third doped layer, a fourth doped layer, and a second conductor layer between the third doped layer and the fourth doped layer, the third doped layer being in contact with the channel. The first doping layer and the third doping layer belong to the same doping type, and the second doping layer and the fourth doping layer belong to the same doping type; the first doped layer and the second doped layer are of different doping types. In one embodiment of the present application, the field effect transistor may be an N-type cold source transistor, the first doped layer is an N-type doped layer, and the second doped layer is a P-type doped layer. In another embodiment of the present application, the field effect transistor may be a P-type cold source transistor, the first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer.
In the embodiment of the present application, by providing the first cold source and the second cold source, the first cold source is exemplified, and the second cold source has a similar structure to the first cold source, which is not described herein again. The first cold source may include a first doped layer, a first conductor layer, and a second doped layer, where the first doped layer and the second doped layer are of different doping types, for example, the first doped layer may be an N-type doped layer, and the second doped layer may be a P-type doped layer. By arranging the doping layers with different doping types in the first cold source electrode, an energy gap can be formed in the first cold source electrode, and the energy band of the high-energy carriers filtered by adjusting the state density is lower, so that the energy band of the injected carriers is lower. The traditional field effect transistor realizes the switch by adjusting the thermionic emission of the channel barrier, and the energy of injected carriers is higher. Therefore, compared with the conventional field effect transistor, in the embodiment of the application, the field effect transistor behaves as a low temperature environment, and thus the structure formed by the first doped layer, the first conductor layer and the second doped layer is called a cold source, and the field effect transistor may be called a cold source field effect transistor.
By arranging the conductor layers in the first cold source electrode and the second cold source electrode, a Schottky barrier can be formed between the conductor layers and the doped layers, electrons tunnel to the conductor layers from one side of the P-type doped layer and further tunnel to one side of the N-type doped layer, so that the tunneling probability can be greatly improved, and the on-state current of the field effect transistor is improved.
The first cold source electrode and the second cold source electrode are arranged in the field effect transistor, and high-energy electrons can be effectively filtered by adjusting the carrier state density of the first cold source electrode or the second cold source electrode, so that the subthreshold swing of the field effect transistor is reduced, the subthreshold swing of the field effect transistor can be smaller than 60mV/dec, the working voltage of an integrated circuit is further reduced, and the power consumption of the integrated circuit is lower. And by arranging the conductor layers in the first cold source electrode and the second cold source electrode, the tunneling probability of electrons in the first cold source electrode and the second cold source electrode can be improved, and the on-state current of the field effect transistor is further improved.
In a specific implementation, in the field effect transistor provided by the embodiment of the present application, the first conductor layer may include: a metallic material, a semi-metallic material, or a metal silicide material. The second conductor layer may include: a metallic material, a semi-metallic material, or a metal silicide material. Wherein the metal material can be at least one of aluminum, gold, silver, platinum, palladium, cobalt, tungsten or ruthenium. The semi-metal (semi-metal) material refers to conduction band and valence bandThe spacing between the two is very narrow. According to the energy band theory, solids can be classified into metals, semi-metals, semiconductors, and insulators in order, according to the interval between conduction and valence bands from narrow to wide. That is, the separation between the conduction band and the valence band of the semi-metallic material is smaller than the separation between the conduction band and the valence band of the semiconductor material and larger than the separation between the conduction band and the valence band of the metallic material. For semiconductors and insulators, the separation between the conduction and valence bands is relatively large, such that the density of states of electrons near the fermi level is equal to zero, becoming the bandgap, with the bandgap of the insulator being larger than that of the semiconductor. The fermi level of the metal is in the conduction band, with a sufficiently high electron density in the vicinity that the current can conduct well. In contrast, in the case of a semimetal material, since the interval between the conduction band and the valence band of the semimetal material is sufficiently small so that the density of states of electrons in the vicinity of the fermi level is close to zero but is not zero, the semimetal material has no band gap. Semi-metallic materials are in the periodic table at the transition from metallic to non-metallic, with physical and chemical properties intermediate between metallic and non-metallic. For example, the semi-metallic material may be at least one of arsenic, antimony, bismuth, tin, or graphite. The metal silicide material may be NiSi 2 、TiSi 2 Or CoSi. Of course, the first conductor layer and the second conductor layer may also include other conductor materials, for example, the first conductor layer (or the second conductor layer) may include graphene, two-dimensional metal, or metalloid, and the like.
In the embodiment of the application, the first cold source electrode and the second cold source electrode are arranged in the field effect transistor, so that the first cold source electrode can be used as the source electrode, the second cold source electrode can be used as the drain electrode, or the first cold source electrode can be used as the drain electrode, and the second cold source electrode can be used as the source electrode, namely after the source electrode and the drain electrode of the field effect transistor in the embodiment of the application are exchanged, the characteristics of the cold source transistor are still provided, and the flexibility of the field effect transistor in use in an integrated circuit is improved. And the first cold source electrode and the second cold source electrode have similar structures and can be manufactured by adopting the same or similar processes, so that the complexity of the manufacturing process is simplified and the cost of the manufacturing process is reduced.
Optionally, in the field effect transistor provided by the embodiment of the present application, the first cold source electrode and the second cold source electrode may be symmetrically disposed with respect to the channel. In the manufacturing process, the same process can be adopted to manufacture each part of the first cold source electrode and the second cold source electrode, so that the complexity of the manufacturing process is reduced, and the cost of the manufacturing process is saved. And the field effect transistor has high flexibility in application to integrated circuits. Of course, the first cold source and the second cold source may be disposed asymmetrically, which is not limited herein. When the first cold source and the second cold source are arranged in an extremely asymmetric mode, the complexity of the manufacturing process of the field effect transistor is low and the cost of the manufacturing process is low because the structures of the first cold source and the second cold source are similar.
For example, the first cold source and the second cold source may have a vertically stacked symmetrical structure. Specifically, the first doped layer, the channel and the third doped layer are located inside the same semiconductor substrate, alternatively, the semiconductor substrate may be a silicon-based semiconductor material. The first conductor layer is positioned on the surface of the semiconductor substrate, the first conductor layer is in contact with the first doped layer, and the second doped layer is positioned on one side of the first conductor layer away from the first doped layer. The second conductor layer is positioned on the surface of the semiconductor substrate, the second conductor layer is in contact with the third doped layer, and the fourth doped layer is positioned on one side of the second conductor layer away from the third doped layer. That is, the first cold source electrode and the second cold source electrode are symmetrically arranged relative to the channel, and the first cold source electrode and the second cold source electrode both adopt vertical lamination structures.
In one implementation of the present application, the gate is located on one side of the semiconductor substrate, and the field effect transistor may further include: an insulating layer covering the top and side surfaces of the gate electrode. For example, the insulating layer may include a first insulating layer, and a second insulating layer covering the first insulating layer, where the first insulating layer may be made of a silicon oxide material, and the second insulating layer may be made of a silicon oxide material, and of course, the first insulating layer and the second insulating layer may be made of other materials, which is not limited herein. According to the embodiment of the application, the grid electrode and the first cold source electrode and the second cold source electrode can be insulated by the insulating layer covering the top surface and the side surface of the grid electrode, so that the grid electrode and the first cold source electrode or the second cold source electrode are prevented from being in short circuit.
In one implementation of the present application, the first cold source and the second cold source may also adopt a laterally stacked symmetrical structure. Specifically, the first cold source, the channel and the second cold source are located inside the same semiconductor substrate, and optionally, the semiconductor substrate may be a silicon-based semiconductor material. The first conductor layer is positioned on one side of the first doped layer away from the channel, and the second doped layer is positioned on one side of the first conductor layer away from the first doped layer. The second conductor layer is positioned on one side of the third doped layer away from the channel, and the fourth doped layer is positioned on one side of the second conductor layer away from the third doped layer. That is, the first cold source electrode and the second cold source electrode are symmetrically arranged relative to the channel, and the first cold source electrode and the second cold source electrode both adopt a transverse lamination structure.
In practical applications, the surface of the semiconductor substrate may be provided with a recess, the gate dielectric layer being located in the recess, and a portion of the gate being embedded in the recess. Therefore, the distance between the grid electrode and a channel in the semiconductor substrate is relatively short, and the on-off between the first cold source electrode and the second cold source electrode can be controlled conveniently through the grid electrode.
In one implementation of the present application, the field effect transistor in the embodiment of the present application may also be an asymmetric structure. The first cold source, the channel and the third doped layer are located inside the same semiconductor substrate. Alternatively, the semiconductor substrate may be a silicon-based semiconductor material. The first conductor layer is positioned on one side of the first doped layer away from the channel, and the second doped layer is positioned on one side of the first conductor layer away from the first doped layer. The second conductor layer is positioned on the surface of the semiconductor substrate, the second conductor layer is in contact with the third doped layer, and the fourth doped layer is positioned on one side of the second conductor layer away from the third doped layer. That is, the first cold source and the second cold source may be asymmetrically disposed. The first cold source electrode can adopt a transverse laminated structure, and the second cold source electrode can adopt a vertical laminated structure.
In an implementation manner of the present application, the field effect transistor provided in the embodiment of the present application may also be a charge trapping field effect transistor, and the gate dielectric layer may include: the charge trapping device comprises a tunneling layer, a charge trapping layer and a charge blocking layer, wherein the tunneling layer is positioned on one side of the gate close to a channel, the charge trapping layer is positioned between the tunneling layer and the gate, and the charge blocking layer is positioned between the charge trapping layer and the gate.
In one implementation of the present application, the field effect transistor may be a ferroelectric field effect transistor. The gate dielectric layer includes: an interface oxide layer positioned on one side of the gate electrode close to the channel, and a ferroelectric layer positioned between the interface oxide layer and the gate electrode.
In addition to the above-described structures, the field effect transistor in the embodiment of the present application may be other types of field effect transistors, and the structures of the field effect transistors of the types are described below.
In one implementation of the application, the first cold source, the channel and the second cold source form a columnar structure, the gate dielectric layer is wrapped on the outer side of the channel, and the gate is wrapped on the outer side of the gate dielectric layer. That is, the field effect transistor in the embodiment of the present application may be a vertical structure field effect transistor. The vertical structure field effect transistor has a compact structure, and the second doping layer in the first cold source electrode and the fourth doping layer in the second cold source electrode are respectively positioned at two ends, so that the first cold source electrode and the second cold source electrode can be conveniently led out. In addition, the grid electrode is wrapped on the outer side of the channel, the overlapping area between the grid electrode and the channel is large, the width-to-length ratio of the channel is increased, and the performance of the field effect transistor is improved.
In one implementation of the present application, the first cold source, the channel, and the second cold source are located on a surface of the same semiconductor substrate. The second doped layer is in a block shape, the first conductor layer wraps a part of the second doped layer close to the semiconductor substrate, and the first doped layer is located on the surface of one side, close to the channel, of the first conductor layer. The fourth doped layer is in a block shape, the second conductor layer wraps a part of the fourth doped layer close to the semiconductor substrate, and the third doped layer is located on the surface of one side, close to the channel, of the second conductor layer. That is, the field effect transistor provided in the embodiment of the present application may be a fin field effect transistor. In the fin-type field effect transistor, the grid electrode is positioned on the surface of one side of the semiconductor substrate, provided with the channel, and the grid electrode covers the channel, so that the overlapping area between the grid electrode and the channel is large, the width-to-length ratio of the channel is increased, and the performance of the field effect transistor is improved. Isolation dielectric layers 18 are provided on the outer sides of the opposite sides of the semiconductor substrate 10. The isolation dielectric layer 18 has a function of protecting the semiconductor substrate 10 and also has a function of insulation.
In one implementation of the present application, the first cold source and the second cold source are located on the surface of the same semiconductor substrate. The field effect transistor includes: at least two channels located on one side of the semiconductor substrate; at least two channels in the field effect transistor are sequentially arranged in a direction perpendicular to the surface of the semiconductor substrate with a gap between adjacent two channels and a gap between the semiconductor substrate and the nearest channel. Optionally, the gate is located on a surface of the semiconductor substrate on a side where the channels are provided, and the gate wraps around each channel in the field effect transistor. Thus, the overlapping area between the grid electrode and the channel is larger, the width-to-length ratio of the channel is increased, and the performance of the field effect transistor is improved.
The first doped layer is connected to one end of each of the at least two channels, and the third doped layer is connected to the other end of each of the at least two channels. The first conductor layer is positioned on the surface of the first doped layer, which is far away from the side of the channel, and the second doped layer is positioned on the surface of the first conductor layer, which is far away from the side of the first doped layer. The second conductor layer is positioned on the surface of the third doped layer, which is far away from the side of the channel, and the fourth doped layer is positioned on the surface of the second conductor layer, which is far away from the side of the third doped layer. That is, the field effect transistor provided by the embodiment of the application may be a gate-all-around field effect transistor, and the second doped layer and the fourth doped layer in the gate-all-around field effect transistor are located at the outer side, so that the first cold source electrode and the second cold source electrode are conveniently led out. Isolation dielectric layers 18 are provided on the outer sides of the opposite sides of the semiconductor substrate 10. The isolation dielectric layer 18 has a function of protecting the semiconductor substrate 10 and also has a function of insulation.
Of course, the field effect transistor provided in the embodiment of the present application may be of other types, and is not illustrated here.
In a second aspect, embodiments of the present application also provide an integrated circuit, the integrated circuit comprising: any one of the field effect transistors described above, and a signal line electrically connected to the field effect transistor. The subthreshold swing of the field effect transistor provided by the embodiment of the application is lower, and can be smaller than 60mV/dec, so that the working voltage of the integrated circuit in the embodiment of the application is lower, and the power consumption of the integrated circuit is lower.
In a third aspect, an embodiment of the present application further provides a method for manufacturing a field effect transistor, where the method may include:
forming a channel, a first doping layer and a third doping layer respectively by adopting a doping process; the first doping layer is in contact with the channel, and the third doping layer is in contact with the channel; the first doping layer and the third doping layer belong to the same doping type;
forming a first conductor layer and a second conductor layer;
forming a second doping layer and a fourth doping layer by adopting a doping process; the first conductor layer is positioned between the first doping layer and the second doping layer, and the second conductor layer is positioned between the third doping layer and the fourth doping layer; the second doped layer and the fourth doped layer belong to the same doping type, and the second doped layer and the first doped layer belong to different doping types.
In the embodiment of the present application, by adopting the above manufacturing method, two cold sources, namely, a first cold source and a second cold source, may be formed in a field effect transistor, where the first cold source includes: the first doping layer, the second doping layer and the first conductor layer, the second cold source electrode comprises: a third doped layer, a fourth doped layer and a second conductor layer. The high-energy electrons can be effectively filtered by adjusting the carrier state density of the first cold source electrode or the second cold source electrode, so that the subthreshold swing of the field effect transistor is reduced, the subthreshold swing of the field effect transistor can be smaller than 60mV/dec, the working voltage of the integrated circuit is further reduced, and the power consumption of the integrated circuit is lower. And by arranging the conductor layers in the first cold source electrode and the second cold source electrode, the tunneling probability of electrons in the first cold source electrode and the second cold source electrode can be improved, and the on-state current of the field effect transistor is further improved.
Optionally, in the embodiment of the present application, the first cold source electrode and the second cold source electrode may be symmetrically disposed with respect to the channel, and since the first doping layer and the third doping layer belong to the same doping type, the same doping process may be used to form the first doping layer and the third doping layer, thereby saving process steps and manufacturing cost. Similarly, the first conductor layer and the second conductor layer can also be manufactured by the same process, and the second doping layer and the fourth doping layer can also be manufactured by the same doping process.
Fig. 1 is a schematic diagram of an internal structure of a terminal according to an embodiment of the present application;
fig. 2 is a simplified schematic structural diagram of a field effect transistor according to an embodiment of the present application;
FIG. 3a is a simplified schematic diagram of a field effect transistor of one type according to an embodiment of the present application;
FIG. 3b is a simplified schematic diagram of another type of FET in accordance with an embodiment of the present application;
fig. 4a is a schematic diagram of an energy level structure of a field effect transistor in the related art;
fig. 4b is a schematic energy level structure of a field effect transistor according to an embodiment of the present application;
FIG. 5a is a graph showing the drain current versus gate voltage of a single-ended cold source transistor;
FIG. 5b is a graph showing the drain current versus gate voltage of a double-ended cold source transistor;
Fig. 6 is a schematic cross-sectional view of a field effect transistor according to an embodiment of the present application;
fig. 7 is another schematic cross-sectional view of a field effect transistor according to an embodiment of the present application;
fig. 8 is another schematic cross-sectional view of a field effect transistor according to an embodiment of the present application;
fig. 9 is another schematic cross-sectional view of a field effect transistor according to an embodiment of the present application;
fig. 10 is another schematic cross-sectional view of a field effect transistor according to an embodiment of the present application;
fig. 11 is a schematic perspective view of a field effect transistor according to an embodiment of the present application;
fig. 12 is another schematic three-dimensional structure of a field effect transistor according to an embodiment of the present application;
FIG. 13 is a schematic cross-sectional view taken at the dashed line AA' of FIG. 12;
fig. 14 is another schematic three-dimensional structure of a field effect transistor according to an embodiment of the present application;
fig. 15 is a flowchart of a method for manufacturing a field effect transistor according to an embodiment of the present application.
Reference numerals:
10-a semiconductor substrate; 11-a first cold source; 111-a first doped layer; 112-a second doped layer; 113-a first conductor layer; 12-a second cold source; 121-a third doped layer; 122-a fourth doped layer; 123-a second conductor layer; 13-channel; 14-grid electrode; 15-a gate dielectric layer; 161-a first insulating layer; 162-a second insulating layer; 171-contact electrodes; 172-extraction electrodes; 173-a first barrier layer; 174-a second barrier layer; 18-isolating the dielectric layer; s1-a first surface; s2-a second surface.
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings. It should be noted that in this specification, like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
The field effect transistor may be a planar field effect transistor, a double gate field effect transistor, a triple gate field effect transistor, a fin field effect transistor (effect transistor, finFET), a gate-all-around field effect transistor, a Vertical structure metal oxide semiconductor field effect transistor (Vertical MOSFET), a floating gate metal oxide semiconductor field effect transistor (Floating Gate MOSFET), a charge trapping metal oxide semiconductor field effect transistor (Charge Trapping MOSFET), a thin film transistor (Thin Film Transistor), a ferroelectric field effect transistor (FeFET), and the like, and the types of the field effect transistors are not limited herein. The field effect transistor can be applied to an integrated circuit, and the integrated circuit can be an integrated circuit with various functions such as logic, storage (e.g. Flash, DRAM, etc.), simulation, sensing, etc. Of course, the field effect transistor in the embodiment of the present application may also be applied to other types of integrated circuits, which are not illustrated herein.
The field effect transistor provided by the embodiment of the application can also be applied to the terminal, and the subthreshold swing of the field effect transistor is lower and can be smaller than 60mV/dec, so that the power consumption of the terminal can be reduced by applying the field effect transistor to the terminal. Optionally, fig. 1 is a schematic diagram illustrating an internal structure of a terminal according to an embodiment of the present application, and as shown in fig. 1, the terminal may include a printed circuit board 101 (printed circuit board, PCB) and a chip 102, and the field effect transistor may be disposed in the chip 102.
Fig. 2 is a simplified schematic structural diagram of a field effect transistor according to an embodiment of the present application, and as shown in fig. 2, the field effect transistor may include: a first cold source 11, a second cold source 12, a channel 13 between the first cold source 11 and the second cold source 12, a gate 14, and a gate dielectric layer 15 between the channel 13 and the gate 14. Alternatively, the first cold source 11 acts as a source of a field effect transistor and the second cold source 12 acts as a drain of a field effect transistor; alternatively, the first cold source 11 serves as the drain of the field effect transistor and the second cold source 12 serves as the source of the field effect transistor. That is, the source and drain of the field effect transistor may be interchanged in the embodiment of the present application. In practice, the on state between the source and the drain may be controlled by applying a gate voltage to the gate 14. When the gate voltage is higher than the threshold voltage, the source and the drain are conducted. When the gate voltage is lower than the threshold voltage, the field effect transistor is in a subthreshold state, and a trace leakage current exists between the source electrode and the drain electrode.
The first cold source 11 may include: a first doped layer 111, a second doped layer 112, and a first conductor layer 113 between the first doped layer 111 and the second doped layer 112, the first doped layer 111 being in contact with the channel 13. The second cold source 12 may include: a third doped layer 121, a fourth doped layer 122, and a second conductor layer 123 between the third doped layer 121 and the fourth doped layer 122, the third doped layer 121 being in contact with the channel 13. The first doped layer 111 and the third doped layer 121 are of the same doping type, and the second doped layer 112 and the fourth doped layer 122 are of the same doping type; the first doped layer 111 and the second doped layer 112 are of different doping types.
In the embodiment of the present application, by providing the first cold source 11 and the second cold source 12, taking the first cold source 11 as an example, the second cold source 12 has a similar structure to the first cold source 11, and will not be described herein. The first cold source 11 may include a first doped layer 111, a first conductor layer 113 and a second doped layer 112, where the first doped layer 111 and the second doped layer 112 are of different doping types, for example, the first doped layer 111 may be an N-type doped layer, and the second doped layer 112 may be a P-type doped layer. By providing the doping layers with different doping types in the first cold source 11, an energy gap can be formed in the first cold source, and the energy band of the high-energy carriers filtered out by adjusting the state density can be lower, so that the energy band of the injected carriers is lower. The traditional field effect transistor realizes the switch by adjusting the thermionic emission of the channel barrier, and the energy of injected carriers is higher. Therefore, compared to the conventional field effect transistor, in the embodiment of the present application, the field effect transistor behaves as a low temperature environment, and thus the structure formed by the first doped layer 111, the first conductor layer 113 and the second doped layer 112 is referred to as a cold source, and the field effect transistor may be referred to as a cold source field effect transistor.
Fig. 3a and 3b are simplified schematic structural diagrams of different types of field effect transistors according to an embodiment of the present application, as shown in fig. 3a, in one embodiment of the present application, the field effect transistor may be an N-type cold source transistor (N-type cold source field effect transistor, nCSFET), the first doped layer 111 may be an N-type doped layer, the second doped layer 112 may be a P-type doped layer, the third doped layer 121 may be an N-type doped layer, and the fourth doped layer 122 may be a P-type doped layer. In another embodiment of the present application, as shown in fig. 3b, the field effect transistor may be a P-type cold source transistor (P-type cold source field effect transistor, pCSFET), the first doped layer 111 may be a P-type doped layer, the second doped layer 112 may be an N-type doped layer, the third doped layer 121 may be a P-type doped layer, and the fourth doped layer 122 may be an N-type doped layer.
In the process of manufacturing the field effect transistor, P-type ions can be doped in the semiconductor layer to obtain a P-type doped layer, and N-type ions are doped in the semiconductor layer to obtain an N-type doped layer. Specifically, the semiconductor layer may include: silicon, germanium, silicon carbide, III-V compound semiconductor, oxide semiconductor, or carbon nanotube, although the semiconductor layer may also include other semiconductor materials, which are not limited herein.
In the embodiment of the application, the first cold source electrode and the second cold source electrode are arranged in the field effect transistor, and high-energy electrons can be effectively filtered by adjusting the carrier state density of the first cold source electrode or the second cold source electrode, so that the subthreshold swing of the field effect transistor is reduced, the subthreshold swing of the field effect transistor can be less than 60mV/dec, the working voltage of an integrated circuit is further reduced, and the power consumption of the integrated circuit is lower. And by arranging the conductor layers in the first cold source electrode and the second cold source electrode, the tunneling probability of electrons in the first cold source electrode and the second cold source electrode can be improved, and the on-state current of the field effect transistor is further improved.
The principle that the field effect transistor can reduce the subthreshold swing in the embodiment of the application is described in detail below with reference to the accompanying drawings. Also, taking the field effect transistor in the embodiment of the present application as an example of the type shown in fig. 3a, that is, the first doped layer 111 in the first cold source 11 may be an N-type doped layer, the second doped layer 112 may be a P-type doped layer, the third doped layer 121 in the second cold source 12 may be an N-type doped layer, and the fourth doped layer 122 may be a P-type doped layer. The principle by which a field effect transistor of the type shown in fig. 3b can reduce the subthreshold swing is similar and will not be described in detail.
Fig. 4a is a schematic diagram of an energy level structure of a field effect transistor in the related art, and fig. 4b is a schematic diagram of an energy level structure of a field effect transistor in an embodiment of the present application. As shown in fig. 4a and 4b, the energy bands of the P-type doped layer and the N-type doped layer include a conduction band Ec, a forbidden band and a valence band Ev, wherein the conduction band Ec is above the forbidden band and the valence band Ev is below the forbidden band. As shown in fig. 4a, in the field effect transistor of the related art, an energy band of injected carriers (i.e., a region shown by an arrow W1 in fig. 4 a) is above a conduction band Ec, i.e., energy of injected carriers is high.
As shown in fig. 4b, in the first cold source or the second cold source, the energy band of the P-doped layer moves up with respect to the energy band of the N-doped layer, and the energy band of the N-doped layer moves down with respect to the energy band of the P-doped layer, until the fermi level is reached, the energy band of the P-doped layer and the energy band of the N-doped layer are equal, and the relative movement of the energy bands is stopped, so that the PN junction formed between the P-doped layer and the N-doped layer reaches an equilibrium state. In the PN junction reaching the equilibrium state, an overlapping area exists between the valence band Ev of the P-type doped layer and the conduction band Ec of the N-type doped layer, electrons can tunnel from the P-type doped layer to the N-type doped layer in the overlapping area, and electrons cannot tunnel in the area where the forbidden band is located. Thus, in fig. 4b, the region indicated by arrow W2 is the energy band of the filtered high-energy carriers, and the region indicated by arrow W3 is the energy band of the injected carriers. Because the overlapping area capable of generating electron tunneling only occupies a small part of the area, and the forbidden band of electrons incapable of tunneling occupies a large part of the area, the PN junction can effectively inhibit high-energy carriers excited by heat energy, and reduce electric leakage caused by heat excitation, thereby reducing subthreshold swing, for example, the subthreshold swing can be lower than 60mV/dec. At this time, the field effect transistor behaves like a cold source field effect transistor operating in a low temperature environment, and thus may be referred to as a cold source field effect transistor.
However, the on-state current of the field effect transistor cannot meet the requirement because the probability of electron tunneling in the PN junction is small. By arranging the conductor layers in the first cold source electrode and the second cold source electrode, namely arranging the conductor layers in the PN junction, a Schottky barrier can be formed between the conductor layers and the doped layers, electrons tunnel to the conductor layers from one side of the P-type doped layer and further tunnel to one side of the N-type doped layer, so that the tunneling probability can be greatly improved, and the on-state current of the field effect transistor is improved.
In the field effect transistor of the related art, the source is electrically connected to the contact electrode, and carriers are injected into the source from the contact electrode, and the subthreshold swing cannot be reduced by 60mV/dec at room temperature because the hot carriers on the potential barrier satisfy the fermi distribution. In the field effect transistor provided by the embodiment of the application, the first cold source electrode or the second cold source electrode suppresses the hot tail by introducing the energy gap. The first cold source electrode or the second cold source electrode forms a cold carrier to be injected into the source electrode through state density regulation. The "cold" carrier distribution does not extend into the thermalized fermi tail in the off-state, and the off-state current is greatly reduced because the hot tail has been cut off by the upper band gap. Whereas for the on-state current of the field effect transistor hot carriers can be transported directly from the source to the drain in the on-state. Therefore, the subthreshold swing of the field effect transistor in embodiments of the present application may not be limited to 60mV/dec.
In a specific implementation, in the field effect transistor provided by the embodiment of the present application, the first conductor layer may include: a metallic material, a semi-metallic material, or a metal silicide material. The second conductor layer may include: a metallic material, a semi-metallic material, or a metal silicide material. The metal material may be at least one of aluminum (Al), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), cobalt (Co), tungsten (W), and ruthenium (Ru). The semi-metal (semi-metal) material is a material having a narrow separation between a conduction band and a valence band. According to the energy band theory, solids can be classified into metals, semi-metals, semiconductors, and insulators in order, according to the interval between conduction and valence bands from narrow to wide. That is, the separation between the conduction band and the valence band of the semi-metallic material is smaller than the separation between the conduction band and the valence band of the semiconductor material and larger than the separation between the conduction band and the valence band of the metallic material. For semiconductors and insulators, the separation between the conduction and valence bands is relatively large, such thatThe density of states of electrons near the fermi level is equal to zero, becoming a band gap, where the insulator band gap is larger than the semiconductor. The fermi level of the metal is in the conduction band, with a sufficiently high electron density in the vicinity that the current can conduct well. In contrast, in the case of a semimetal material, since the interval between the conduction band and the valence band of the semimetal material is sufficiently small so that the density of states of electrons in the vicinity of the fermi level is close to zero but is not zero, the semimetal material has no band gap. Semi-metallic materials are in the periodic table at the transition from metallic to non-metallic, with physical and chemical properties intermediate between metallic and non-metallic. For example, the semi-metallic material may be at least one of arsenic, antimony, bismuth, tin, or graphite. The metal silicide can be NiSi 2 、TiSi 2 Or CoSi. Of course, the first conductor layer and the second conductor layer may also include other conductor materials, for example, the first conductor layer (or the second conductor layer) may include graphene, two-dimensional metal, or metalloid, and the like.
In the embodiment of the application, the first cold source electrode and the second cold source electrode are arranged in the field effect transistor, so that the first cold source electrode can be used as the source electrode, the second cold source electrode can be used as the drain electrode, or the first cold source electrode can be used as the drain electrode, and the second cold source electrode can be used as the source electrode, namely after the source electrode and the drain electrode of the field effect transistor in the embodiment of the application are exchanged, the characteristics of the cold source transistor are still provided, and the flexibility of the field effect transistor in use in an integrated circuit is improved. And the first cold source electrode and the second cold source electrode have similar structures and can be manufactured by adopting the same or similar processes, so that the complexity of the manufacturing process is simplified and the cost of the manufacturing process is reduced.
Fig. 5a is a schematic diagram of a drain current versus a gate voltage of a single-ended cold source transistor, and fig. 5b is a schematic diagram of a drain current versus a gate voltage of a double-ended cold source transistor. In the drain current versus gate voltage curve, steeper curves represent smaller subthreshold swings. As shown in fig. 5a, the single-ended cold source transistor refers to a configuration in which only one of the source and the drain is set as a cold source, and in fig. 5a, a curve L1 is a relationship between a drain current and a gate voltage when the source is set as a cold source, and a curve L2 is a relationship between a drain current and a gate voltage when the drain is set as a cold source. In fig. 5b, the double-ended cold source transistor refers to the field effect transistor comprising two cold sources, a first cold source and a second cold source. The relationship curve of the drain current and the gate voltage in both cases may be the curve L3 in fig. 5b, where the first cold source electrode is used as the source electrode, the second cold source electrode is used as the drain electrode, or the first cold source electrode is used as the drain electrode and the second cold source electrode is used as the source electrode.
As can be seen from fig. 5a, the fet has no effect of a cold source when only the drain is set as a cold source, where the subthreshold swing is greater than 60mV/dec. The FET has the effect of a cold source only when the source is set as the cold source, and the subthreshold swing is smaller than 60mV/dec. The ability to regulate and control the state density of the single-ended cold source transistor is lost after the source electrode and the drain electrode are exchanged, and as can be seen from fig. 5b, the ability to regulate and control the state density of the double-ended cold source transistor is not affected after the source electrode and the drain electrode of the double-ended cold source transistor are exchanged, and the subthreshold swing of the double-ended cold source transistor is less than 60mV/dec. Therefore, the double-ended cold source transistor can realize excellent characteristics of source and drain used interchangeably compared with the single-ended cold source transistor. In addition, the double-end cold source transistor can reduce the process complexity and is beneficial to the process integration of the integrated circuit.
Optionally, in the field effect transistor provided by the embodiment of the present application, the first cold source electrode and the second cold source electrode may be symmetrically disposed with respect to the channel. In the manufacturing process, the same process can be adopted to manufacture each part of the first cold source electrode and the second cold source electrode, so that the complexity of the manufacturing process is reduced, and the cost of the manufacturing process is saved. And the field effect transistor has high flexibility in application to integrated circuits. Of course, the first cold source and the second cold source may be disposed asymmetrically, which is not limited herein. When the first cold source and the second cold source are arranged in an extremely asymmetric mode, the complexity of the manufacturing process of the field effect transistor is low and the cost of the manufacturing process is low because the structures of the first cold source and the second cold source are similar.
For example, the first cold source and the second cold source may adopt vertically stacked symmetrical structures, as shown in fig. 6, fig. 6 is a schematic cross-sectional view of a field effect transistor according to an embodiment of the present application, the first doped layer 111, the channel 13 and the third doped layer 121 are located inside the same semiconductor substrate 10, alternatively, the semiconductor substrate 10 may be a silicon-based semiconductor material, and the semiconductor substrate 10 may have: the opposite first surface S1 and second surface S2, for example, the first surface S1 may be an upper surface of the semiconductor substrate 10, and the second surface S2 may be a lower surface of the semiconductor substrate 10. The first conductor layer 113 is located on the surface of the semiconductor substrate 10, the first conductor layer 113 is in contact with the first doped layer 111, and the second doped layer 112 is located on a side of the first conductor layer 113 away from the first doped layer 111. The second conductor layer 123 is located on the surface of the semiconductor substrate 10, for example, the first conductor layer 113 and the second conductor layer 123 may be located on the first surface S1 of the semiconductor substrate 10, the second conductor layer 123 is in contact with the third doped layer 121, and the fourth doped layer 122 is located on a side of the second conductor layer 123 remote from the third doped layer 121. That is, the first cold source 11 and the second cold source 12 may be symmetrically disposed with respect to the channel 13, and the first cold source 11 and the second cold source 12 each adopt a vertical stacked structure.
In the fabrication process, the first doping layer 111, the third doping layer 121, and the channel 13 may be formed on the surface of the semiconductor substrate 10 using a doping process. Since the first doping layer 111 and the third doping layer 121 belong to the same doping type, the first doping layer 111 and the third doping layer 121 can be manufactured by the same doping process, so that the process steps are saved, and the manufacturing cost is saved. The first conductor layer 113 and the second conductor layer 123 may be formed by the same process, and the second doped layer 112 and the fourth doped layer 122 may be formed by the same process.
In order to draw the first cold source and the second cold source, the field effect transistor may further include: a contact electrode 171 and an extraction electrode 172, the contact electrode 171 being electrically connected to the second doped layer 112 (or the fourth doped layer 122), the extraction electrode 172 being electrically connected to the contact electrode 171. The contact electrode 171 and the extraction electrode 172 may be made of a metal material, for example, tungsten metal. In order to block diffusion of metal in the contact electrode 171 and prevent the metal from entering the surrounding medium, a barrier layer may be provided on the side surface of the contact electrode 171, for example, a first barrier layer 173 may be provided on the side surface of the contact electrode 171, and a second barrier layer 174 may be provided on the side surface of the first barrier layer 173. The barrier layer is generally made of a conductive material, so that the barrier layer has better conductivity and does not affect the electrical connection between the contact electrode 171 and the second doped layer 112 (or the fourth doped layer 122), and may be made of a material such as titanium or titanium nitride.
With continued reference to fig. 6, in the field effect transistor provided in the embodiment of the present application, the gate 14 is located on one side of the semiconductor substrate 10, and the field effect transistor may further include: an insulating layer covering the top and side surfaces of the gate 14, the insulating layer may insulate the gate 14 from the first cold source 11, and the insulating layer may insulate the gate 14 from the second cold source 12. For example, the insulating layer may include a first insulating layer 161, and a second insulating layer 162 covering the first insulating layer 161, the first insulating layer 161 may be made of a silicon oxide material, the second insulating layer 162 may be made of a silicon oxide material, and of course, the first insulating layer 161 and the second insulating layer 162 may be made of other materials, which is not limited herein. In the embodiment of the application, the insulating layer covering the top surface and the side surface of the gate 14 can insulate the gate 14 from the first cold source 11 and the second cold source 12, and prevent the gate 14 from shorting with the first cold source 11 or the second cold source 12.
In addition, the first cold source and the second cold source may also adopt a laterally stacked symmetrical structure, as shown in fig. 7, fig. 7 is another schematic cross-sectional view of the field effect transistor provided in the embodiment of the present application, where the first cold source 11, the channel 13 and the second cold source 12 are located in the same semiconductor substrate 10, alternatively, the semiconductor substrate 10 may be a silicon-based semiconductor material, and the semiconductor substrate 10 may have: the opposite first surface S1 and second surface S2, for example, the first surface S1 may be an upper surface of the semiconductor substrate 10, and the second surface S2 may be a lower surface of the semiconductor substrate 10. The first cold source 11, the channel 13, and the second cold source 12 may be located at a side of the semiconductor substrate 10 near the first surface S1. The first conductor layer 113 is located on a side of the first doped layer 111 remote from the channel 13, and the second doped layer 112 is located on a side of the first conductor layer 113 remote from the first doped layer 111. The second conductor layer 123 is located on the side of the third doped layer 121 remote from the channel 13, and the fourth doped layer 122 is located on the side of the second conductor layer 123 remote from the third doped layer 121. That is, the first cold source 11 and the second cold source 12 are symmetrically disposed with respect to the channel 13, and the first cold source 11 and the second cold source 12 each adopt a lateral stacked structure.
In the manufacturing process, the first doping layer 111 and the third doping layer 121 can be formed on the surface of the semiconductor substrate 10 by adopting the same doping process, and the second doping layer 112 and the fourth doping layer 122 can be formed on the surface of the semiconductor substrate 10 by adopting the same doping process, so that the manufacturing process of the field effect transistor is simple, the process steps are fewer, and the manufacturing cost is lower.
With continued reference to fig. 7, the surface of the semiconductor substrate 10 is provided with a recess U, and the gate dielectric layer 15 is located in the recess U, and a portion of the gate 14 is embedded in the recess U. In this way, the distance between the grid 14 and the channel 13 in the semiconductor substrate 10 can be made closer, so that the on-off between the first cold source 11 and the second cold source 12 can be controlled conveniently through the grid 14.
In practical implementation, the fet in the embodiment of the present application may also have an asymmetric structure, as shown in fig. 8, fig. 8 is another schematic cross-sectional view of the fet in the embodiment of the present application, where the first cold source 11, the channel 13 and the third doped layer 121 are located inside the same semiconductor substrate 10. Alternatively, the semiconductor substrate 10 may be a silicon-based semiconductor material, and the semiconductor substrate 10 may have: the opposite first surface S1 and second surface S2, for example, the first surface S1 may be an upper surface of the semiconductor substrate 10, and the second surface S2 may be a lower surface of the semiconductor substrate 10. The first conductor layer 113 is located on a side of the first doped layer 111 remote from the channel 13, and the second doped layer 112 is located on a side of the first conductor layer 113 remote from the first doped layer 111. The second conductor layer 121 is located on the surface of the semiconductor substrate 10, for example, the first cold source 11, the channel 13, and the third doped layer 121 may be located on a side of the semiconductor substrate 10 near the first surface S1, the second conductor layer 123 may be located on the first surface S1 of the semiconductor substrate 10, the second conductor layer 123 is in contact with the third doped layer 121, and the fourth doped layer 122 is located on a side of the second conductor layer 123 remote from the third doped layer 121. That is, the first cold source 11 and the second cold source 12 may be asymmetrically disposed. The first cold source 11 may have a lateral stacked structure, and the second cold source 12 may have a vertical stacked structure.
In the manufacturing process, the first doping layer 111 and the third doping layer 122 can be formed on the surface of the semiconductor substrate 10 by adopting the same doping process, so that the process steps can be reduced, and the manufacturing cost is lower. Although the first cold source 11 and the second cold source 12 are asymmetrically arranged in the structure shown in fig. 8, the first cold source 11 and the second cold source 12 have similar structures, and the manufacturing process is relatively easy and the manufacturing cost is relatively low.
Alternatively, the field effect transistor provided in the embodiment of the present application may be a charge trapping field effect transistor, as shown in fig. 9, fig. 9 is another schematic cross-sectional view of the field effect transistor provided in the embodiment of the present application, where the gate dielectric layer may include: a tunneling layer 151 on a side of the gate 14 adjacent to the channel 13, a charge trapping layer 152 between the tunneling layer 151 and the gate 14, and a charge blocking layer 153 between the charge trapping layer 152 and the gate 14.
In the embodiment of the present application, the field effect transistor may also be a ferroelectric field effect transistor, as shown in fig. 10, fig. 10 is another schematic cross-sectional view of the field effect transistor according to the embodiment of the present application, and the gate dielectric layer may include: an interfacial oxide layer 154 on a side of the gate 14 adjacent to the channel 13, and a ferroelectric layer 155 between the interfacial oxide layer 154 and the gate 14.
In addition to the structures shown in fig. 6 to 10, the field effect transistor in the embodiment of the present application may be other types of field effect transistors, and the structures of the types of field effect transistors are described below with reference to the accompanying drawings.
Fig. 11 is a schematic perspective view of a field effect transistor according to an embodiment of the present application, as shown in fig. 11, a first cold source 11, a channel, and a second cold source 12 form a column structure, wherein the channel is located between the first cold source 11 and the second cold source 12. The gate dielectric layer 15 wraps around the outside of the channel, and the gate 14 wraps around the outside of the gate dielectric layer 14. That is, the field effect transistor in the embodiment of the present application may be a vertical structure field effect transistor. The vertical structure field effect transistor has a compact structure, and the second doped layer 112 in the first cold source 11 and the fourth doped layer 122 in the second cold source 12 are respectively located at two ends, so that the first cold source 11 and the second cold source 12 can be conveniently led out. In addition, the grid 14 wraps the outer side of the channel, the overlapping area between the grid 14 and the channel is large, the width-to-length ratio of the channel is increased, and the performance of the field effect transistor is improved.
Fig. 12 is another schematic perspective view of a fet according to an embodiment of the present application, and fig. 13 is a schematic cross-sectional view of fig. 12 at a broken line AA', as shown in fig. 12 and 13, in which the first cold source 11, the channel 13 and the second cold source 12 are located on the same surface of the semiconductor substrate 10, alternatively, the semiconductor substrate 10 may be a silicon-based semiconductor material. The semiconductor substrate 10 may include: the first surface S1 and the second surface S2 disposed opposite to each other, for example, the first surface S1 may be an upper surface of the semiconductor substrate 10, and the second surface S2 may be a lower surface of the semiconductor substrate 10. The first cold source 11, the channel 13, and the second cold source 12 may be located on the first surface S1 of the semiconductor substrate 10. Isolation dielectric layers 18 are provided on the outer sides of the opposite sides of the semiconductor substrate 10. The isolation dielectric layer 18 has a function of protecting the semiconductor substrate 10 and also has a function of insulation.
The second doped layer 112 is in a block shape, and the first conductor layer 113 wraps a part of the second doped layer 112 close to the semiconductor substrate 10, and the first doped layer 111 is located on the surface of the first conductor layer 113 close to one side of the channel 13. The fourth doped layer 122 is in a block shape, the second conductor layer 123 wraps a portion of the fourth doped layer 122 near the semiconductor substrate 10, and the third doped layer 121 is located on a surface of the second conductor layer 123 near a side of the channel 13. That is, the field effect transistor provided in the embodiment of the present application may be a fin field effect transistor. In the fin-type field effect transistor, the gate 14 is located on the surface of the semiconductor substrate 10 on the side where the channel 13 is located, for example, the gate 14 may be located on the first surface S1 of the semiconductor substrate 10, and the gate 14 covers the channel 13, so that the overlapping area between the gate 14 and the channel 13 is larger, the width-to-length ratio of the channel is increased, and the performance of the field effect transistor is improved. The internal structure of the field effect transistor is schematically shown for clarity in fig. 12, with the position of the gate 14 being indicated by a dashed line.
In addition, since the second doped layer 112 is in a block shape and the first conductor layer 113 wraps a portion of the second doped layer 112 close to the semiconductor substrate 10, the top of the second doped layer 112 is not wrapped by the first conductor layer 113, so that the second doped layer 112 is electrically connected to the contact electrode, i.e., the first cold source 11 is conveniently led out. Similarly, the top of the fourth doped layer 122 is not surrounded by the second conductor layer 123, thus facilitating electrical connection of the fourth doped layer 122 to the contact electrode, i.e. facilitating extraction of the second cold source 12.
Fig. 14 is another schematic three-dimensional structure of a field effect transistor according to an embodiment of the present application, as shown in fig. 14, the first cold source 11 and the second cold source 12 are located on a surface of the same semiconductor substrate 10, for example, the first cold source 11 and the second cold source 12 may be located on a first surface S1 of the semiconductor substrate 10. Alternatively, the semiconductor substrate 10 may be a silicon-based semiconductor material. The semiconductor substrate 10 may include: the first surface S1 and the second surface S2 disposed opposite to each other, for example, the first surface S1 may be an upper surface of the semiconductor substrate 10, and the second surface S2 may be a lower surface of the semiconductor substrate 10. Isolation dielectric layers 18 are provided on the outer sides of the opposite sides of the semiconductor substrate 10. The isolation dielectric layer 18 has a function of protecting the semiconductor substrate 10 and also has a function of insulation.
The field effect transistor may include: at least two channels 13 located on one side of the semiconductor substrate 10, for example, these channels 13 may be located on one side of the first surface S1 of the semiconductor substrate 10. At least two channels 13 in the field effect transistor are arranged in sequence in a direction perpendicular to the surface of the semiconductor substrate 10 with a gap between two adjacent channels 13 and a gap between the semiconductor substrate 10 and the nearest channel 13, and the number of channels 13 in the field effect transistor is not limited as shown in fig. 13 by taking the example that the field effect transistor includes three channels 13. The gate 14 is located on the surface of the semiconductor substrate 10 on the side where the channels 13 are provided, for example, the gate 14 may be located on the first surface S1 side of the semiconductor substrate 10, and the gate 14 wraps around each channel 13 in the field effect transistor. Thus, the overlapping area between the grid electrode 14 and the channel 13 is large, the width-to-length ratio of the channel is increased, and the performance of the field effect transistor is improved. In fig. 14, the internal structure of the field effect transistor is schematically shown for clarity, and the position of the gate 14 is shown in dotted lines.
The first doped layer 111 is connected to one end of each channel 13, and the third doped layer 121 is connected to the other end of each channel 13. The first conductor layer 113 is located on a surface of the first doped layer 111 on a side away from the channel 13, and the second doped layer 112 is located on a surface of the first conductor layer 113 on a side away from the first doped layer 111. The second conductor layer 123 is located on the surface of the third doped layer 121 on the side away from the channel 13, and the fourth doped layer 122 is located on the surface of the second conductor layer 123 on the side away from the third doped layer 121. That is, the field effect transistor provided in the embodiment of the present application may be a gate-all-around field effect transistor, in which the second doped layer 112 and the fourth doped layer 122 are located at the outer sides, so as to facilitate the extraction of the first cold source 11 and the second cold source 12.
Of course, the field effect transistor provided in the embodiment of the present application may be of other types, and is not illustrated here.
Based on the same technical concept, the embodiment of the application also provides an integrated circuit, which may include: any one of the field effect transistors described above, and a signal line electrically connected to the field effect transistor. The subthreshold swing of the field effect transistor provided by the embodiment of the application is lower, and can be smaller than 60mV/dec, so that the working voltage of the integrated circuit in the embodiment of the application is lower, and the power consumption of the integrated circuit is lower.
Based on the same technical concept, the embodiment of the present application further provides a method for manufacturing a field effect transistor, and fig. 15 is a flowchart of a method for manufacturing a field effect transistor according to the embodiment of the present application, as shown in fig. 15, where the method may include:
s201, forming a channel, a first doping layer and a third doping layer respectively by adopting a doping process; the first doping layer is in contact with the channel, and the third doping layer is in contact with the channel; the first doping layer and the third doping layer belong to the same doping type;
s202, forming a first conductor layer and a second conductor layer;
s203, forming a second doping layer and a fourth doping layer by adopting a doping process; the first conductor layer is positioned between the first doping layer and the second doping layer, and the second conductor layer is positioned between the third doping layer and the fourth doping layer; the second doped layer and the fourth doped layer belong to the same doping type, and the second doped layer and the first doped layer belong to different doping types.
In the embodiment of the present application, by adopting the above manufacturing method, two cold source electrodes, namely, a first cold source electrode and a second cold source electrode, may be formed in a field effect transistor, where the first cold source electrode includes: the first doping layer, the second doping layer and the first conductor layer, the second cold source electrode comprises: a third doped layer, a fourth doped layer and a second conductor layer. The high-energy electrons can be effectively filtered by adjusting the carrier state density of the first cold source electrode or the second cold source electrode, so that the subthreshold swing of the field effect transistor is reduced, the subthreshold swing of the field effect transistor can be smaller than 60mV/dec, the working voltage of the integrated circuit is further reduced, and the power consumption of the integrated circuit is lower. And by arranging the conductor layers in the first cold source electrode and the second cold source electrode, the tunneling probability of electrons in the first cold source electrode and the second cold source electrode can be improved, and the on-state current of the field effect transistor is further improved.
In fig. 15, S201, S202, and S203 are merely marks for each step, and the order of each step is not limited, and may be adjusted according to the specific structure of the field effect transistor in specific implementation.
Alternatively, in the embodiment of the present application, the first cold source electrode and the second cold source electrode may be symmetrically disposed with respect to the channel, and referring to the structures shown in fig. 6 and 7, since the first doped layer 111 and the third doped layer 121 belong to the same doping type, the same doping process may be used to form the first doped layer 111 and the third doped layer 121, so that the process steps are saved and the manufacturing cost is saved. Similarly, the first conductive layer 113 and the second conductive layer 123 may be formed by the same process, and the second doped layer 112 and the fourth doped layer 122 may be formed by the same doping process.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the scope of the embodiments of the application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims and the equivalents thereof, the present application is also intended to include such modifications and variations.
Claims (23)
- A field effect transistor, comprising: a first cold source, a second cold source, a channel between the first cold source and the second cold source, a gate, and a gate dielectric layer between the channel and the gate;the first cold source electrode comprises: a first doped layer, a second doped layer, and a first conductor layer between the first doped layer and the second doped layer, the first doped layer in contact with the channel;the second cold source electrode comprises: a third doped layer, a fourth doped layer, and a second conductor layer between the third doped layer and the fourth doped layer, the third doped layer in contact with the channel;the first doping layer and the third doping layer belong to the same doping type, and the second doping layer and the fourth doping layer belong to the same doping type; the first doped layer and the second doped layer are of different doping types.
- The field effect transistor of claim 1, wherein the first cold source and the second cold source are symmetrically disposed with respect to the channel.
- The field effect transistor of claim 2 wherein said first doped layer, said channel and said third doped layer are located within the same semiconductor substrate;the first conductor layer is positioned on the surface of the semiconductor substrate, the first conductor layer is in contact with the first doping layer, and the second doping layer is positioned on one side of the first conductor layer away from the first doping layer;the second conductor layer is positioned on the surface of the semiconductor substrate, the second conductor layer is in contact with the third doped layer, and the fourth doped layer is positioned on one side, away from the third doped layer, of the second conductor layer.
- The field effect transistor of claim 2, wherein the first cold source, the channel, and the second cold source are located inside a same semiconductor substrate;the first conductor layer is positioned on one side of the first doped layer away from the channel, and the second doped layer is positioned on one side of the first conductor layer away from the first doped layer;The second conductor layer is located on one side of the third doped layer away from the channel, and the fourth doped layer is located on one side of the second conductor layer away from the third doped layer.
- The field effect transistor of claim 1 wherein said first cold source, said channel and said third doped layer are located within the same semiconductor substrate;the first conductor layer is positioned on one side of the first doped layer away from the channel, and the second doped layer is positioned on one side of the first conductor layer away from the first doped layer;the second conductor layer is positioned on the surface of the semiconductor substrate, the second conductor layer is in contact with the third doped layer, and the fourth doped layer is positioned on one side, away from the third doped layer, of the second conductor layer.
- The field effect transistor of any of claims 1-5, wherein said gate dielectric layer comprises: a tunneling layer located on a side of the gate adjacent to the channel, a charge trapping layer located between the tunneling layer and the gate, and a charge blocking layer located between the charge trapping layer and the gate.
- The field effect transistor of any of claims 1-5, wherein said gate dielectric layer comprises: an interface oxide layer positioned on one side of the gate electrode close to the channel, and a ferroelectric layer positioned between the interface oxide layer and the gate electrode.
- The field effect transistor according to any one of claims 3 to 7, wherein the gate electrode is located on one side of the semiconductor substrate;the field effect transistor further includes: and an insulating layer covering top and side surfaces of the gate, the insulating layer insulating the gate from the first cold source, and the insulating layer insulating the gate from the second cold source.
- The field effect transistor according to any one of claims 3 to 8, wherein a surface of the semiconductor substrate is provided with a groove;the grid dielectric layer is positioned in the groove, and a part of the grid is embedded into the groove.
- The field effect transistor of claim 2, wherein the first cold source, the channel, and the second cold source form a columnar structure;the grid electrode dielectric layer wraps the outer side of the channel, and the grid electrode wraps the outer side of the grid electrode dielectric layer.
- The field effect transistor of claim 2, wherein the first cold source, the channel, and the second cold source are located on a surface of a same semiconductor substrate;the second doped layer is in a block shape, and the first conductor layer wraps a part of the second doped layer close to the semiconductor substrate; the first doping layer is positioned on the surface of the first conductor layer, which is close to one side of the channel;The fourth doped layer is in a block shape, and the second conductor layer wraps a part of the fourth doped layer close to the semiconductor substrate; the third doped layer is positioned on the surface of the second conductor layer, which is close to one side of the channel.
- The field effect transistor according to claim 11, wherein the gate is located on a surface of the semiconductor substrate on a side where the channel is provided, and the gate covers the channel.
- The field effect transistor of claim 2, wherein the first cold source and the second cold source are located on a surface of a same semiconductor substrate;the field effect transistor includes: at least two channels located on one side of the semiconductor substrate; the at least two channels are sequentially arranged in a direction perpendicular to the surface of the semiconductor substrate, a gap is formed between every two adjacent channels, and a gap is formed between the semiconductor substrate and the nearest channel;the first doping layer is connected with one end of each of the at least two channels, and the third doping layer is connected with the other end of each of the at least two channels;The first conductor layer is positioned on the surface of the first doped layer, which is far away from the side of the channel, and the second doped layer is positioned on the surface of the first conductor layer, which is far away from the side of the first doped layer;the second conductor layer is positioned on the surface of the third doped layer, which is far away from the side of the channel, and the fourth doped layer is positioned on the surface of the second conductor layer, which is far away from the side of the third doped layer.
- The field effect transistor of claim 13, wherein said gate is located on a surface of said semiconductor substrate on a side where said channels are provided, and wherein said gate wraps around each of said channels of said at least two channels.
- The field effect transistor according to any one of claims 1 to 14, wherein the first doped layer is an N-type doped layer and the second doped layer is a P-type doped layer.
- The field effect transistor according to any one of claims 1 to 14, wherein the first doped layer is a P-type doped layer and the second doped layer is an N-type doped layer.
- The field effect transistor according to any one of claims 1 to 16, wherein the first conductor layer includes: a metal material, a semi-metal material, or a metal silicide material;The second conductor layer includes: a metallic material, a semi-metallic material, or a metal silicide material.
- The field effect transistor of claim 17, wherein the metallic material comprises: at least one of aluminum, gold, silver, platinum, palladium, cobalt, tungsten, or ruthenium.
- The field effect transistor of claim 17, wherein the semi-metallic material comprises: at least one of arsenic, antimony, bismuth, tin or graphite.
- The field effect transistor of claim 17, wherein,the metal silicide material includes: niSi 2 、 TiSi 2 Or CoSi.
- An integrated circuit, comprising: the field effect transistor according to any one of claims 1 to 20, and a signal line electrically connected to the field effect transistor.
- A method of fabricating a field effect transistor, comprising:forming a channel, a first doping layer and a third doping layer respectively by adopting a doping process; the first doping layer is in contact with the channel, and the third doping layer is in contact with the channel; the first doping layer and the third doping layer belong to the same doping type;forming a first conductor layer and a second conductor layer;Forming a second doping layer and a fourth doping layer by adopting a doping process; the first conductor layer is positioned between the first doping layer and the second doping layer, and the second conductor layer is positioned between the third doping layer and the fourth doping layer; the second doping layer and the fourth doping layer belong to the same doping type, and the second doping layer and the first doping layer belong to different doping types.
- The method of claim 22, wherein forming the channel, the first doped layer, and the third doped layer by a doping process comprises:forming the first doping layer and the third doping layer by adopting the same doping process;the forming a second doped layer and a fourth doped layer by adopting a doping process comprises the following steps:and forming the second doping layer and the fourth doping layer by adopting the same doping process.
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