CN116825805A

CN116825805A - Cold source transistor, manufacturing method thereof and integrated circuit

Info

Publication number: CN116825805A
Application number: CN202210286284.XA
Authority: CN
Inventors: 侯朝昭; 张强; 李伟; 许俊豪
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-03-22
Filing date: 2022-03-22
Publication date: 2023-09-29

Abstract

The application provides a cold source transistor, a manufacturing method thereof and an integrated circuit, comprising the following steps: a semiconductor substrate, a source electrode, a drain electrode and a gate electrode; the semiconductor substrate is provided with a source region, a drain region and a channel region positioned between the source region and the drain region, wherein the source is coupled with the source region, the drain is coupled with the drain region, and the grid is arranged on the channel region; the channel region comprises a first doped region and a channel, the first doped region is arranged on one side of the source region, and the channel is arranged on one side of the drain region; the source region comprises a second doped region and a conductor region, and the conductor region is arranged between the first doped region and the second doped region; the drain region comprises a third doped region; the first and third doped regions are of the same doping type and the second and third doped regions are of different doping types. According to the cold source transistor, the grid electrode is arranged on the channel region, and when the Leng Zailiu quantum passes through the Schottky barrier and enters the channel from the first doping region, cold carriers are not subjected to external reheating, so that leakage caused by the warmed cold carriers can be reduced, and subthreshold swing is reduced.

Description

Cold source transistor, manufacturing method thereof and integrated circuit

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to a cold source transistor, a manufacturing method thereof, and an integrated circuit.

Background

The traditional metal-oxide-semiconductor field-effect transistor (MOSFET) is limited by the Boltzmann distribution (maxwell-boltzmann distribution) of carriers, and leakage current can be formed due to thermal excitation, so that the gate control efficiency of the current can not break through the subthreshold swing of 60mV/dec at normal temperature, the subthreshold swing is a performance index for measuring the mutual conversion rate between the on state and the off state of the transistor, the subthreshold swing represents the change amount of gate voltage required by ten times of the change of source leakage current, the S factor is also called as S factor, and the smaller the S factor is, the faster the on-off rate is. Thus, to reduce the subthreshold swing, the threshold voltage of a MOSFET is typically set between 100 and 300 mV.

In the prior art, transistors enabling subthreshold swing less than 60mV/dec are mainly divided into two types, namely a tunneling field effect transistor (T-FET) and a negative capacitance field effect transistor (negative vapacitance FET, NC-FET). The on-state current of the T-FET is too low to be of practical value, and the NC-FET is abandoned by the industry because the instability of the negative capacitance causes serious obstruction to the practical application of the transistor.

At present, a novel super steep threshold swing field effect transistor is as follows: cold source transistors (CSFETs) have been proposed. The technical core of the CSFET is that the distribution of hot carriers is reduced and subthreshold swing is reduced through the regulation and control of the state density of the source carriers, so that the working voltage of an integrated circuit is further reduced.

The above-mentioned calculation of the subthreshold swing of the CSFET is generally based on idealized ballistic transport conditions, but in practical applications, due to coupled scattering transport by electron-phonon interactions (electron-phonon interaction), electron thermalization problems may arise. Therefore, the cold electrons can be partially thermalized before entering the channel from the source end, and the thermalized high-energy electrons can reform leakage current, so that the gate control efficiency of the current is improved. In view of this, it is necessary to provide a novel cold source transistor, which can make its performance more stable on the premise of ensuring that the on-state current is sufficiently large.

Disclosure of Invention

The application provides a cold source transistor, a manufacturing method thereof and an integrated circuit, wherein a grid electrode is arranged on a channel region, so that cold carriers are not reheated by the outside, and therefore, the leakage caused by the warmed cold carriers can be reduced, the subthreshold swing is reduced, and the performance of the cold source transistor is more stable.

In a first aspect, the present application provides a cold source transistor, including: a semiconductor substrate, a source electrode, a drain electrode and a gate electrode; the semiconductor substrate is provided with a source region, a drain region and a channel region positioned between the source region and the drain region, wherein the source is coupled with the source region, the drain is coupled with the drain region, and the grid is arranged on the channel region; the channel region comprises a first doped region and a channel, the first doped region is arranged on one side of the source region, and the channel is arranged on one side of the drain region; the source region comprises a second doped region and a conductor region, and the conductor region is arranged between the first doped region and the second doped region; the drain region comprises a third doped region; the first doped region and the third doped region belong to the same doping type, and the second doped region and the third doped region belong to different doping types.

In the manufacturing process, a doping process can be used to form a source region, a drain region and a channel region between the source region and the drain region on the surface of the semiconductor substrate. Because the first doped region and the third doped region belong to the same doping type, the first doped region and the third doped region can be manufactured by the same doping process, so that the process steps are saved, and the manufacturing cost is saved.

In this aspect, the semiconductor substrate may be a silicon (bulk silicon) substrate structure. And may also be one or more of semiconductor materials such as graphene (dirac cone structure), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), indium gallium arsenide (InGaAs), etc. The cold source transistor is equivalent to a switching device, and in practical application, in the off state of the cold source transistor, the source and the drain are in an insulating state, and electrons in the source region cannot reach the drain region through the channel region. By applying a gate voltage to the gate, the cold source transistor is turned on, and the source and the drain are turned on. When the gate voltage is higher than the threshold voltage, the source and the drain are conducted. When the gate voltage is lower than the threshold voltage, the cold source transistor is in a subthreshold state, and a trace leakage current exists between the source and the drain.

Ideally, the energy band of the second doped region moves up relative to the energy band of the first doped region, and the energy band of the first doped region moves down relative to the energy band of the second doped region, so that the energy band stops moving relatively when the energy band of the second doped region is equal to the energy band of the first doped region, and the PN junction formed between the second doped region and the first doped region reaches an equilibrium state. In the PN junction reaching the equilibrium state, an overlapping region exists between the valence band of the second doped region and the conduction band of the first doped region, electrons can tunnel from the second doped region to the first doped region, and electrons cannot tunnel in the region where the forbidden band is located. And because the overlapping area capable of generating electron tunneling only occupies a small part of area, and the forbidden band of electrons incapable of tunneling occupies a large part of area, the PN junction can effectively inhibit high-energy carriers excited by heating energy, reduce electric leakage caused by thermal excitation, and further reduce subthreshold swing. In order to improve the tunneling efficiency, a conductor region is arranged between the second doped region and the first doped region, so that the second doped region and the conductor region form metal and semiconductor contacts, and a schottky barrier is formed at the contact surface between the second doped region and the conductor region. When Leng Zailiu carriers can cross the schottky barrier, the number of carriers entering the channel region is large and can rapidly pass through forming a large current, and an ultra-low sub-threshold swing is exhibited. Therefore, the tunneling probability can be greatly improved, and the on-state current of the cold source transistor is improved.

However, in actual situations, when the subthreshold swing of the cold source transistor in the related art is calculated, the problem of thermalization of electrons is not considered only based on ballistic transport consideration. In practice, however, some thermalization problems may occur before the electrons pass from the source region to the channel region, since the electrons are actually affected by various types of scattering. In order to solve the problem, the gate electrode of the cold source transistor is arranged on the channel region, so that when Leng Zailiu passes through the PN junction and the Schottky barrier and enters the channel from the first doping region, cold carriers are not reheated by the outside, and therefore, the leakage caused by the warmed cold carriers can be reduced, and the subthreshold swing is reduced.

In one embodiment of the present application, the cold source transistor may be a P-type cold source transistor, the dopant of the first doped region is a P-type dopant, the dopant of the second doped region is an N-type dopant of a first concentration, the dopant in the channel is an N-type or P-type dopant of a second concentration, and the first concentration is higher than the second concentration.

In another embodiment of the present application, the cold source transistor may be an N-type cold source transistor, the dopant of the first doped region is an N-type dopant, the dopant of the second doped region is a P-type dopant with a third concentration, the dopant in the channel is an N-type or P-type dopant with a fourth concentration, and the third concentration is higher than the fourth concentration.

By arranging doped regions with different doping types in the source region to the channel region, an energy gap is formed, and high-energy electrons can be effectively filtered by adjusting the carrier state density in the source region, so that the energy band of the carriers is reduced, in other words, the working parameters of the cold source transistor in the embodiment of the application behave similarly to those of the cold source transistor working in a low-temperature environment. The thickness of the conductor region is small, which may be 3-5 nm, to ensure a sufficiently high transmission and a low thermalization rate.

In the cold source transistor provided by the embodiment of the present application, the conductor region includes a material for providing cold carriers, and the material for providing cold carriers may include at least one of the following: metallic materials, semi-metallic materials, metal silicide materials, topological insulators, two-dimensional transition metal sulfides, and two-dimensional transition metal carbides.

The metal material includes: at least one of aluminum, gold, silver, platinum, nickel, palladium, cobalt, tungsten, or ruthenium. The semi-metallic material refers to a material having a narrow separation between a conduction band and a valence band. According to the band theory, the separation between conduction and valence bands ranges from narrow to wide, and solids can be divided into metals, semi-metals, semiconductors, and insulators in order. That is, the separation between the conduction band and the valence band of the semi-metallic material is smaller than the separation between the conduction band and the valence band of the semiconductor material and larger than the separation between the conduction band and the valence band of the metallic material. For semiconductors and insulators, the separation between the conduction and valence bands is relatively large, such that the density of states of electrons near the fermi level is equal to zero, becoming the bandgap, with the bandgap of the insulator being larger than that of the semiconductor. The fermi level of the metal is in the conduction band, with a sufficiently high electron density in the vicinity that the current can conduct well. In contrast, in the case of a semimetal material, since the interval between the conduction band and the valence band of the semimetal material is sufficiently small so that the density of states of electrons in the vicinity of the fermi level is close to zero but is not zero, the semimetal material has no band gap. Semi-metallic materials are in the periodic table at the transition from metallic to non-metallic, with physical and chemical properties intermediate between metallic and non-metallic. For example, semi-metallic materials include: at least one of arsenic, antimony, bismuth, tin or graphite.

The metal silicide material may be one or more of nickel silicide, platinum silicide, palladium silicide, iridium silicide. A topological insulator is an internal insulating material whose interface allows charge movement. Inside the topological insulator, the electron band structure is similar to a conventional insulator, with its fermi level between the conduction and valence bands. There are specific quantum states at the surface of the topological insulator that lie within the band gap of the bulk band structure, allowing conduction.

In one embodiment of the present application, a gate dielectric layer may also be included between the gate and the channel region. When the cold source transistor provided by the application is a charge trapping cold source transistor, the gate dielectric layer comprises: the device comprises a tunneling layer, a charge trapping layer and a charge blocking layer, wherein the tunneling layer is positioned on one side of the gate close to the channel region, the charge trapping layer is positioned between the tunneling layer and the gate, and the charge blocking layer is positioned between the charge trapping layer and the gate.

When the cold source transistor provided by the application is a ferroelectric cold source transistor, the gate dielectric layer comprises: an interface oxide layer positioned on one side of the gate electrode close to the channel region, and a ferroelectric layer positioned between the interface oxide layer and the gate electrode.

In an embodiment of the present application, in the cold source transistor provided by the present application, a gate is located on one side of a semiconductor substrate, and the cold source transistor may further include: and an insulating layer covering the top and side surfaces of the gate electrode, wherein the insulating layer can insulate the gate electrode from the source electrode, and the insulating layer can insulate the gate electrode from the drain electrode. For example, the insulating layer may include a first insulating layer, and a second insulating layer covering the first insulating layer, where the first insulating layer may be made of a silicon oxide material, and the second insulating layer may be made of a silicon oxide material, and of course, the first insulating layer and the second insulating layer may be made of other materials, which is not limited herein. In the embodiment of the application, the grid electrode and the source electrode and the drain electrode can be insulated by arranging the insulating layer which covers the top surface and the side surface of the grid electrode, so that the short circuit between the grid electrode and the source electrode or the drain electrode is prevented.

In a second aspect, the present application provides an integrated circuit, which may include: the cold source transistor provided in the first aspect, and a signal line electrically connected to the cold source transistor. Because the subthreshold swing of the cold source transistor provided by the embodiment of the application is lower, the working voltage of the integrated circuit in the embodiment of the application is also lower, and the power consumption of the integrated circuit can be further reduced.

In a third aspect, the present application further provides a method for manufacturing a cold source transistor, where the method includes:

providing a semiconductor substrate; forming a source region, a drain region and a channel region between the source region and the drain region on a semiconductor substrate, wherein the channel region comprises a first doped region and a channel, the first doped region is arranged on one side of the source region, and the channel is arranged on one side of the drain region; the source region comprises a second doped region and a conductor region, and the conductor region is arranged between the first doped region and the second doped region; the drain region comprises a third doped region, the first doped region and the third doped region belong to the same doping type, and the second doped region and the third doped region belong to different doping types; a grid electrode is arranged on the semiconductor substrate and is arranged on the channel region; a source is provided in the source region, and a drain is provided in the drain region.

In one embodiment of the present application, a doping process is used to form a first doped region and a third doped region, respectively, comprising: and forming a first doped region and a third doped region by adopting the same doping process.

In one embodiment of the present application, disposing a gate electrode on a semiconductor substrate includes: providing an interface oxide layer on a semiconductor substrate; disposing a ferroelectric layer on the interfacial oxide layer; a gate is disposed over the ferroelectric layer.

In one embodiment of the present application, disposing a gate electrode on a semiconductor substrate includes: providing a tunneling layer on the channel region; a charge trapping layer on the tunneling layer; providing a charge blocking layer over the charge trapping layer; a gate is disposed over the charge blocking layer.

In one embodiment of the present application, the source region and the drain region may be symmetrically disposed with respect to the channel, and the first doped region and the third doped region are of the same doping type, and the second doped region and the third doped region are of different doping types, so that the first conductor region and the second conductor region are made of the same material. When the device is specifically used, the source electrode and the drain electrode do not need to be distinguished, and when the first electrode is the source electrode, the second electrode is the drain electrode, so that the device has wider use scene and is convenient to maintain.

Drawings

Fig. 1 is a schematic diagram of a cold source transistor according to the present application;

fig. 2A is a schematic structural diagram of a P-type cold source transistor according to the present application;

fig. 2B is a schematic structural diagram of an N-type cold source transistor according to the present application;

FIG. 3A is a schematic diagram of an energy level structure of a cold source transistor in an ideal state;

fig. 3B is a schematic diagram of an energy level structure of the cold source transistor in an actual state;

FIG. 4 is a schematic diagram showing the current-voltage transfer characteristic of different transistors;

fig. 5A is a schematic diagram of a second structure of the cold source transistor provided by the present application;

fig. 5B is a schematic diagram III of a cold source transistor according to the present application;

fig. 6 is a schematic diagram of a cold source transistor according to the present application;

fig. 7 is a schematic diagram of a cold source transistor according to the present application;

fig. 8 is a flowchart of a method for manufacturing a cold source transistor according to the present application.

Reference numerals:

100-a cold source transistor; 11-a semiconductor substrate; 12-source; 13-drain electrode; 14-grid electrode; 111-source 112-drain; 113-a channel region; 1111-a second doped region; 1112-conductor regions; 1121-a third doped region; 1131-a first doped region; 1132-channel; 1133-fourth doped region; 15-a gate dielectric layer; 151-tunneling layer; 152-a charge-trapping layer; 153-charge blocking layer; 154—an interfacial oxide layer; 155-a ferroelectric layer; 161-a first insulating layer; 162-a second insulating layer; 171-a first electrode; 172-a second electrode; 1710-first region; 1720—second region; 1711-a first conductor region; 1721-second conductor region.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted. The words expressing the positions and directions described in the present application are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present application. The drawings of the present application are merely schematic representations of relative positional relationships and are not intended to represent true proportions.

The terminology used in the following examples is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include, for example, "one or more" such forms of expression, unless the context clearly indicates to the contrary.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

The embodiment of the application provides a cold source transistor, a manufacturing method thereof and an integrated circuit, wherein the cold source transistor can be various types of transistors such as a planar field effect transistor, a thin film transistor (thin film transistor), a double gate field effect transistor, a triple gate field effect transistor (gate-all-around field effect transistor, GAAFET), a fin field effect transistor (fin-effect transistor, finFET), a vertical structure metal oxide semiconductor field effect transistor (vertical MOSFET), a floating gate metal oxide semiconductor field effect transistor (floating gate MOSFET), a charge trapping metal oxide semiconductor field effect transistor (charge trapping MOSFET), a ferroelectric field effect transistor (FeFET) and the like, and the types of the cold source transistors are not particularly limited. The cold source transistor provided by the application can be applied to an integrated circuit, and the integrated circuit can be an integrated circuit for realizing various functions, such as a logic integrated circuit, a memory (e.g. Flash, DRAM and the like) integrated circuit, an analog integrated circuit, a sensing integrated circuit and the like. Of course, the cold source transistor in the embodiment of the present application may also be applied to other types of integrated circuits, and will not be described in detail herein.

The cold source transistor provided by the embodiment of the application can also be applied to the terminal, and the subthreshold swing of the cold source transistor is low, so that the distribution of hot carriers can be reduced by applying the terminal of the cold source transistor, thereby reducing the working voltage of the terminal and further obviously reducing the power consumption of the terminal. Wherein carriers refer to particles of a substance with charges, such as electrons and ions, which can move freely, and the carriers can move directionally under the action of an electric field. In metals, the carriers are electrons. In a semiconductor, carriers include electrons and holes. The carrier in the high energy state has more energy and can easily generate transition, and the carrier in the low energy state has lower energy and is not easy to generate transition. The Leng Zailiu carrier corresponds to a carrier after "cutting" a part of carriers having a higher energy state.

Fig. 1 is a schematic structural diagram of a cold source transistor according to an embodiment of the present application, and referring to fig. 1, a cold source transistor 100 includes: a semiconductor substrate 11, a source electrode 12, a drain electrode 13, and a gate electrode 14;

semiconductor substrate 11 has a source region 111, a drain region 112, and a channel region 113 between source region 111 and drain region 112, source 12 is coupled to source region 111, drain 13 is coupled to drain region 112, and gate 14 is disposed on channel region 113; the source region 111 includes a second doped region 1111 and a conductor region 1112, and the channel region 113 includes a first doped region 1131 and a channel 1132; the first doped region 1131 is on the source region 111 side and the channel 1132 is on the drain region 112 side; drain region 112 includes a third doped region 1121, conductor region 1112 disposed between first doped region 1131 and second doped region 1111; the first doped region 1131 and the third doped region 1121 are of the same doping type, and the second doped region 1111 and the third doped region 1121 are of different doping types. Alternatively, the channel 1132 may be undoped or lightly doped. When the channel 1132 is lightly doped, the channel 1132 may include an N-type lightly doped layer or a P-type lightly doped layer.

In a specific implementation, in the cold source transistor provided in the embodiment of the present application, the semiconductor substrate 11 may be a silicon (bulk silicon) substrate structure. And may also be one or more of semiconductor materials such as graphene (dirac cone structure), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), indium gallium arsenide (InGaAs), etc.

The cold source transistor 100 corresponds to a switching device, and in practical applications, in the off state of the cold source transistor 100, the source 12 and the drain 13 are insulated from each other, and electrons in the source region 111 cannot reach the drain region 112 through the channel region 113. By applying a gate voltage to the gate 14, the cold source transistor 100 is turned on, and the source 12 and the drain 13 are turned on. When the gate voltage is higher than the threshold voltage, conduction is provided between the source 12 and the drain 13. When the gate voltage is lower than the threshold voltage, the cold source transistor 100 is in a subthreshold state, and a trace leakage current exists between the source 12 and the drain 13.

Fig. 2A and fig. 2B are simplified schematic structural diagrams of different types of cold source transistors according to an embodiment of the present application, and referring to fig. 2A, in an embodiment of the present application, the cold source transistor 100 is a P-type cold source transistor, the dopant in the first doped region 1131 is a P-type dopant, the dopant in the second doped region 1111 is a first concentration of N-type dopant, the dopant in the channel 1132 is a second concentration of N-type or P-type dopant, and the first concentration is higher than the second concentration. The first concentration may be, for example, 1X 10 ²⁰ cm- ³ ～1×10 ²¹ cm- ³ The second concentration may be 1×10 ¹⁵ cm- ³ ～1×10 ¹⁸ cm- ³ 。

Referring to fig. 2B, in another embodiment of the present application, the cold source transistor 100 is an N-type cold source transistor, the dopant in the first doped region 1131 is an N-type dopant, the dopant in the second doped region 1111 is a P-type dopant with a third concentration, the dopant in the channel is an N-type or P-type dopant with a fourth concentration, and the third concentration is higher than the fourth concentration. The third concentration may be, for example, 1X 10 ²⁰ cm- ³ ～1×10 ²¹ cm- ³ The fourth concentration may be 1×10 ¹⁵ cm- ³ ～1×10 ¹⁸ cm- ³ 。

Wherein the conductor region may include therein a material for providing cold carriers, the material for providing cold carriers may include at least one of: metallic materials, semi-metallic materials, metal silicide materials, topological insulators, two-dimensional transition metal sulfides, and two-dimensional transition metal carbides.

The metal material includes: at least one of aluminum (Al), gold (Au), silver (Ag), platinum (Pt), nickel (Ni), palladium (Pd), cobalt (Co), tungsten (W), or ruthenium (Ru). The semi-metal (semi-metal) material refers to a material having a narrow separation between a conduction band and a valence band. According to the band theory, the separation between conduction and valence bands ranges from narrow to wide, and solids can be divided into metals, semi-metals, semiconductors, and insulators in order. That is, the separation between the conduction band and the valence band of the semi-metallic material is smaller than the separation between the conduction band and the valence band of the semiconductor material and larger than the separation between the conduction band and the valence band of the metallic material. For semiconductors and insulators, the separation between conduction and valence bands is relatively large, such that the density of states of electrons near the fermi level is equal to zero, becoming the bandgap, with the bandgap of the insulator being larger than that of the semiconductor. The fermi level of the metal is in the conduction band, with a sufficiently high electron density in the vicinity that the current can conduct well. In contrast, in the case of a semimetal material, since the interval between the conduction band and the valence band of the semimetal material is sufficiently small so that the density of states of electrons in the vicinity of the fermi level is close to zero but is not zero, the semimetal material has no band gap. Semi-metallic materials are in the periodic table at the transition from metallic to non-metallic, with physical and chemical properties intermediate between metallic and non-metallic. For example, semi-metallic materials include: at least one of arsenic, antimony, bismuth, tin or graphite.

The metal silicide material may be nickel silicide (NiSi ₂ ) Platinum silicide (Pt) ₂ Si), palladium silicide (Pd ₂ Si), iridium silicide (IrSi). A topological insulator is an internal insulating material whose interface allows charge movement. The fermi level is the highest level of electrons at absolute zero. Inside the topological insulator, the electron band structure is similar to a conventional insulator, with its fermi level between the conduction and valence bands. There are specific quantum states at the surface of the topological insulator that lie within the band gap of the bulk band structure, allowing conduction. The two-dimensional transition metal sulfide and the two-dimensional transition metal carbide may be Cd ₃ C ₂ 、VTe ₂ 、TaTe ₂ 。

As a possible implementation manner, based on the P-type cold source tube and the N-type cold source tube defined in fig. 2A and 2B, when the cold source transistor is a P-type cold source tube, the conductor region may be made of a material with a work function greater than 4.5eV, and when the cold source transistor is an N-type cold source tube, the conductor region may be made of a material with a work function less than 4.5 eV. Work function refers to the minimum energy required to move an electron from the inside of a solid just to the surface of the object. The work function for metals is one half the ionization energy of the free atoms of the metal. The work function for a semiconductor is the difference between the energy of the stationary electrons in vacuum and the energy of the fermi level of the semiconductor.

By providing doped regions with different doping types in the source region 111 to the channel region 113, an energy gap is formed, and by adjusting the carrier state density in the source region 111, high-energy electrons can be effectively filtered, so that the energy band of carriers is reduced, in other words, the working parameters of the cold source transistor 100 in the embodiment of the application behave similarly to those of the cold source transistor working in a low-temperature environment. Illustratively, the thickness of the conductor region is small, and may be 3 to 5nm, to ensure sufficiently high transmission and low thermalization rate, while the thickness of the first doped region may be 5 to 10nm.

Taking an N-type cold source tube as an example, fig. 3A is a schematic diagram of an energy level structure of a cold source transistor in an ideal state. Referring to fig. 3A, the energy bands of the second doped region 1111 (P-type dopant) and the first doped region 1131 (N-type dopant) include a conduction band Ec, a forbidden band and a valence band Ev, wherein the conduction band Ec is above the forbidden band and the valence band Ev is below the forbidden band. In the cold source transistor, the energy band of the injected carriers (i.e., arrow W in fig. 3A ₁ The region shown) is above the conduction band Ec, i.e., the energy of injected carriers is high.

Since the energy band of the second doped region 1111 moves up relative to the energy band of the first doped region 1131, and the energy band of the first doped region 1131 moves down relative to the energy band of the second doped region 1111, the energy band of the second doped region 1111 and the energy band of the first doped region 1131 stop moving relatively when the energy bands are equal, and the PN junction formed between the second doped region 1111 and the first doped region 1131 reaches an equilibrium state. In the PN junction reaching the equilibrium state, there is an overlap region between the valence band of the second doped region 1111 and the conduction band of the first doped region 1131, in which electrons can tunnel from the second doped region 1111 to the first doped region 1131, and electrons cannot tunnel in the region where the forbidden band is located. Thus, in FIG. 3A, W ₁ The region shown is the energy band of the filtered high energy carriers, W ₂ The region shown is the energy band of injected carriers. Because the overlapping area capable of generating electron tunneling only occupies a small part of the area, and the forbidden band of electrons incapable of tunneling occupies a large part of the area, the PN junction can effectively inhibit high-energy carriers excited by heat energy, and reduce electric leakage caused by heat excitation, thereby reducing subthreshold swing (such as less than 60 mV/dec).

However, the on-state current of the cold source transistor cannot meet the requirement because the probability of electron tunneling in the PN junction is small. In order to increase the tunneling efficiency, the electric field at the tunneling junction is increased and the tunneling width is reduced. A conductor region 1112 is disposed between the second doped region 1111 and the first doped region 1131, and the second doped region 1111 and the conductor region 1112 form a metal-semiconductor contact, which means that a schottky barrier is formed at the contact surface between the metal and the semiconductor contact. Electrons tunnel from the second doped region 1111 side to the conductor region 1112 and further to the first doped region 1131 side, at this time, since the Leng Zailiu electrons assume the distribution shown in fig. 3A, when the Leng Zailiu electrons can cross the schottky barrier, the number of carriers entering the channel region 113 is large and can rapidly pass through to form a large current, and an ultra-low subthreshold swing is exhibited. Therefore, the tunneling probability can be greatly improved, and the on-state current of the cold source transistor is improved.

When the subthreshold swing of the cold source transistor in the related art is calculated, the problem of thermalization of electrons is not considered only based on ballistic transport. Ballistic transport (ballistic transport) means that the carriers in the medium experience little scattering during transport. The movement of the electrons only obeys newton's law, since there is no scattering effect. In practice, however, some thermalization problems may occur before the electrons pass from the source region 111 to the channel region 113, since the electrons are actually subject to various types of scattering.

Taking an N-type cold source tube as an example, fig. 3B is a schematic diagram of an energy level structure of the cold source transistor in an actual state. Referring to FIG. 3B, electrons can be taken from the second dopant in the region where the valence band Ev of the second dopant region 1111 overlaps the conduction band Ec of the first dopant region 1131The impurity region 1111 is tunneled to the first doping region 1131, and electrons cannot be tunneled in the region where the forbidden band is located. In FIG. 3B, W ₁ The region shown is the energy band of the filtered high energy carriers, W ₂ The region shown is the energy band of injected carriers. However, due to various scattering effects, electrons passing through the first doped region 1131 are reheated, and the off-state current is increased again, so that the ultra-steep subthreshold swing cannot be represented.

In the cold source transistor 100 provided in the embodiment of the present application, the gate 14 is disposed on the channel region 113 (the first doped region 1131 and the channel 1132), so that when the Leng Zailiu electrons cross the schottky barrier and enter the channel 1132 from the first doped region 1131, the cold carriers are not re-heated by the outside, so that the leakage caused by the heated cold carriers can be reduced, the subthreshold swing can be reduced, and optionally, the gate 14 can also cover the channel region 113 to achieve a better effect of preventing the cold carriers from being heated.

Referring to fig. 4, fig. 4 is a schematic diagram showing current-voltage transfer characteristics of different transistors. The abscissa is the gate voltage of the transistor, the ordinate is the subthreshold swing, and the steeper the curve in the relation of drain current and gate voltage is, the smaller the subthreshold swing is. As can be seen from fig. 4, conventional field effect transistors cannot achieve sub-threshold swings below 60 mV/dec; the cold source transistor has a problem of thermalization, and the subthreshold swing does not perform well. Compared with the traditional field effect transistor and cold source transistor, the cold source transistor 100 provided by the embodiment of the application has larger current density, does not have the problem of thermalization, has simpler process and can realize lower subthreshold swing in a larger current range.

In some embodiments, as shown in fig. 5A and 5B, a gate dielectric layer 15 may also be included between the gate 14 and the channel region 113.

As shown in fig. 5A, when the cold source transistor 100 provided in the embodiment of the present application is a charge trapping cold source transistor, the gate dielectric layer 15 includes: a tunneling layer 151 on a side of the gate 14 adjacent to the channel region 113, a charge trapping layer 152 between the tunneling layer 151 and the gate 14, and a charge blocking layer 153 between the charge trapping layer 152 and the gate 14.

As shown in fig. 5B, when the cold source transistor 100 provided in the embodiment of the present application is a ferroelectric cold source transistor, the gate dielectric layer 15 includes: an interfacial oxide layer 154 on a side of the gate 14 adjacent to the channel region 113, and a ferroelectric layer 155 between the interfacial oxide layer 154 and the gate.

During fabrication, a doping process may be used to form source region 111, drain region 112, and channel region 113 between source region 111 and drain region 112 at the surface of semiconductor substrate 11. Since the first doped region 1131 and the third doped region 1121 belong to the same doping type, the first doped region 1131 and the third doped region 1121 can be manufactured by the same doping process, so that the process steps are saved, and the manufacturing cost is saved.

As shown in fig. 6, as a possible implementation manner, in the cold source transistor 100 provided by the embodiment of the present application, the gate 14 is located on one side of the semiconductor substrate 11, where the cold source transistor may further include: an insulating layer covering the top and side surfaces of the gate 14, the insulating layer may insulate the gate 14 from the source 12, and the insulating layer may insulate the gate 14 from the drain 13. For example, the insulating layer may include a first insulating layer 161, and a second insulating layer 162 covering the first insulating layer 161, the first insulating layer 161 may be made of a silicon oxide material, the second insulating layer 162 may be made of a silicon oxide material, and of course, the first insulating layer 161 and the second insulating layer 162 may be made of other materials, which is not limited herein. In the embodiment of the application, the insulating layer covering the top surface and the side surface of the gate 14 can insulate the gate 14 from the source 12 and the drain 13, and prevent the gate 14 from shorting with the source 12 or the drain 13.

In practical applications, a recess may be provided in the surface of the semiconductor substrate 11, the gate dielectric layer 15 being located in the recess, and a portion of the gate 14 being embedded in the recess. In this way, the gate 14 can be made closer to the channel region 113 in the semiconductor substrate 11, thereby facilitating control of the on-off between the source 12 and the drain 13 by the gate.

As an alternative embodiment, referring to fig. 7, the cold source transistor 100 in the present application may also have a symmetrical structure. The cold source transistor 100 includes: the semiconductor substrate 11, the first electrode 171, the second electrode 172, the gate 14, and the semiconductor substrate 11 have a first region 1710, a second region 1720, and a channel region 113 located between the first region 1710 and the second region 1720, the first electrode 171 is coupled to the first region 1710, the second electrode 172 is coupled to the second region 1720, the gate 14 is disposed on the channel region 113, the channel region 113 includes a first doped region 1131, a channel 1132, and a fourth doped region 1133, the first doped region 1131 and the fourth doped region 1133 are symmetrically disposed with respect to the channel 1132, the first region 1710 includes a second doped region 1111 and a first conductor region 1711 for distinguishing the structure, and the drain region 112 includes a third doped region 1121 and a second conductor region 1721. The first doped region 1131 and the third doped region 1121 are of the same doping type, the second doped region 1111 and the third doped region 1121 are of different doping types, the doping type of the first doped region 1131 and the fourth doped region 1133 is the same, and the material of the first conductor region 1711 and the second conductor region 1721 is the same. In specific use, the source and the drain may not be needed to be distinguished, when the first electrode 171 is a source, the second electrode 172 is a drain, and when the first electrode 171 is a drain, the second electrode 172 is a source, so that the use scene is wider and the maintenance is convenient. Various structures, materials and parameter properties of the first region 1710 and the second region 1720 may be described with reference to the above embodiments for each doped region in the source region 111, which is not repeated here.

Based on the same technical concept, the embodiment of the application also provides an integrated circuit, which may include: any one of the cold source transistors, and a signal line electrically connected to the cold source transistor. Because the subthreshold swing of the cold source transistor 100 provided by the embodiment of the application is lower, the working voltage of the integrated circuit in the embodiment of the application is also lower, and the power consumption of the integrated circuit can be further reduced.

Based on the same technical concept, the embodiment of the application further provides a method for manufacturing a cold source transistor, and fig. 8 is a flowchart of a method for manufacturing a cold source transistor provided by the embodiment of the application, as shown in fig. 8, the method may include:

s801: providing a semiconductor substrate; wherein the substrate structure may be a silicon (bulk silicon) substrate structure. And may also be one or more of semiconductor materials such as graphene (dirac cone structure), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), indium gallium arsenide (InGaAs), etc.

S802: forming a source region, a drain region and a channel region between the source region and the drain region on a semiconductor substrate, wherein the channel region comprises a first doped region and a channel; the first doped region is arranged on one side of the source region, and the channel is arranged on one side of the drain region; the source region comprises a second doped region and a conductor region, the conductor region is arranged between the first doped region and the second doped region, the drain region comprises a third doped region, the first doped region and the third doped region belong to the same doping type, and the second doped region and the third doped region belong to different doping types; the conductor region may include therein a material for providing cold carriers, the material for providing cold carriers including at least one of: the thickness of the first doped region may be 5 to 10nm. The thickness of the conductor region may be 3 to 5nm.

S803: a gate is disposed on the semiconductor substrate, the gate being disposed on the channel region.

S804: a source is provided in the source region, and a drain is provided in the drain region.

As an alternative embodiment, disposing a gate on the semiconductor substrate may specifically include: providing an interface oxide layer on the semiconductor substrate; disposing a ferroelectric layer on the interfacial oxide layer; a gate is disposed on the ferroelectric layer.

As an optional implementation manner, disposing a gate on the semiconductor substrate specifically includes: providing a tunneling layer on the semiconductor substrate; a charge trapping layer on the tunneling layer; providing a charge blocking layer over the charge trapping layer; the gate is disposed on the charge blocking layer.

In the embodiment of the application, the source electrode and the drain electrode can be formed in the cold source transistor by adopting the manufacturing method, wherein the channel region comprises a first doping region and a channel, the source region comprises a second doping region and a conductor region, and the drain region comprises a third doping region, and the grid electrode is arranged on the channel region, so that when Leng Zailiu electrons cross a Schottky barrier, cold carriers are not subjected to external reheating after entering the channel from the first doping region, and therefore, the leakage caused by the warmed cold carriers can be reduced, and the subthreshold swing is reduced. The subthreshold swing can be smaller than 60mV/dec, so that the working voltage of the integrated circuit is reduced, and the power consumption of the integrated circuit is lower. And the tunneling probability of electrons can be improved through the conductor region arranged in the source region, so that the on-state current of the cold source transistor is improved.

In fig. 8, steps S801, S802, S803, and S804 are merely identified, and the order of the steps is not limited, and may be adjusted according to the specific structure of the cold source transistor in specific implementation.

Alternatively, in the embodiment of the present application, the source region and the drain region may be symmetrically disposed with respect to the channel, referring to the structure shown in fig. 7, since the first doped region and the third doped region belong to the same doping type, the second doped region and the third doped region belong to different doping types, the doping types of the first doped region and the fourth doped region are the same, and the materials of the first conductor region and the second conductor region are the same. When the device is specifically used, the source electrode and the drain electrode do not need to be distinguished, and when the first electrode is the source electrode, the second electrode is the drain electrode, so that the device has wider use scene and is convenient to maintain.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the scope of the embodiments of the application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims and the equivalents thereof, the present application is also intended to include such modifications and variations.

Claims

1. A cold source transistor, comprising: a semiconductor substrate, a source electrode, a drain electrode and a gate electrode;

the semiconductor substrate is provided with a source region, a drain region and a channel region positioned between the source region and the drain region, the source is coupled with the source region, the drain is coupled with the drain region, and the grid is arranged on the channel region;

the channel region comprises a first doped region and a channel, the first doped region is arranged on one side of the source region, and the channel is arranged on one side of the drain region;

the source region comprises a second doped region and a conductor region, and the conductor region is arranged between the first doped region and the second doped region;

the drain region comprises a third doped region;

the first doped region and the third doped region belong to the same doping type, and the second doped region and the third doped region belong to different doping types.

2. The cold source transistor of claim 1, wherein the dopant of the first doped region is a P-type dopant, the dopant of the second doped region is a first concentration of N-type dopant, the dopant in the channel is a second concentration of N-type or P-type dopant, and the first concentration is higher than the second concentration.

3. The cold source transistor of claim 1, wherein the dopant of the first doped region is an N-type dopant, the dopant of the second doped region is a P-type dopant of a third concentration, the dopant in the channel is an N-type or P-type dopant of a fourth concentration, and the third concentration is higher than the fourth concentration.

4. A cold source transistor according to any one of claims 1-3, characterized in that the conductor region comprises a material for providing cold carriers.

5. The cold source transistor of claim 4, wherein the cold carrier-providing material comprises at least one of:

metallic materials, semi-metallic materials, metal silicide materials, topological insulators, two-dimensional transition metal sulfides, and two-dimensional transition metal carbides.

6. The cold source transistor of claim 5, wherein the metallic material comprises: at least one of aluminum, gold, silver, platinum, nickel, palladium, cobalt, tungsten, or ruthenium.

7. The cold source transistor of claim 5, wherein the semi-metallic material comprises: at least one of arsenic, antimony, bismuth, tin or graphite.

8. The cold source transistor according to any one of claims 1 to 7, wherein the thickness of the first doped region is 5 to 10nm.

9. Cold source transistor according to any of claims 1-8, characterized in that the thickness of the conductor region is 3-5 nm.

10. The cold source transistor of any one of claims 1-9, further comprising a gate dielectric layer between the gate and the channel region.

11. The cold source transistor of any one of claims 1-10, wherein the gate dielectric layer comprises: a tunneling layer located on a side of the gate adjacent to the channel region, a charge trapping layer located between the tunneling layer and the gate, and a charge blocking layer located between the charge trapping layer and the gate.

12. The cold source transistor of any one of claims 1-11, wherein the gate dielectric layer comprises: an interface oxide layer positioned on one side of the gate electrode close to the channel region, and a ferroelectric layer positioned between the interface oxide layer and the gate electrode.

13. The cold source transistor according to any one of claims 1 to 12, wherein the cold source transistor further comprises: an insulating layer covering top and side surfaces of the gate electrode, the insulating layer insulating the gate electrode from the source electrode, and the insulating layer insulating the gate electrode from the drain electrode.

14. An integrated circuit, comprising: the cold source transistor according to any one of claims 1 to 13, and a signal line electrically connected to the cold source transistor.

15. The manufacturing method of the cold source transistor is characterized by comprising the following steps of:

providing a semiconductor substrate;

forming a source region, a drain region and a channel region between the source region and the drain region on the semiconductor substrate, wherein the channel region comprises a first doped region and a channel, the first doped region is arranged on one side of the source region, and the channel is arranged on one side of the drain region; the source region comprises a second doped region and a conductor region, and the conductor region is arranged between the first doped region and the second doped region; the drain region comprises a third doped region, the first doped region and the third doped region belong to the same doping type, and the second doped region and the third doped region belong to different doping types;

Providing a gate on the semiconductor substrate, the gate being provided on the channel region;

and a source electrode is arranged in the source region, and a drain electrode is arranged in the drain region.

16. The method of claim 15, wherein forming the first doped region and the third doped region by a doping process comprises:

and forming the first doped region and the third doped region by adopting the same doping process.

17. The method according to claim 15 or 16, wherein a gate is provided on the semiconductor substrate, comprising:

providing an interface oxide layer on the semiconductor substrate;

disposing a ferroelectric layer on the interfacial oxide layer;

a gate is disposed on the ferroelectric layer.

18. The method according to claim 15 or 16, wherein a gate is provided on the semiconductor substrate, comprising:

providing a tunneling layer on the semiconductor substrate;

a charge trapping layer on the tunneling layer;

providing a charge blocking layer over the charge trapping layer;

the gate is disposed on the charge blocking layer.