CN114300540A - Source-drain asymmetric gate-all-around reconfigurable field effect transistor - Google Patents
Source-drain asymmetric gate-all-around reconfigurable field effect transistor Download PDFInfo
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- CN114300540A CN114300540A CN202210004745.XA CN202210004745A CN114300540A CN 114300540 A CN114300540 A CN 114300540A CN 202210004745 A CN202210004745 A CN 202210004745A CN 114300540 A CN114300540 A CN 114300540A
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Abstract
The invention discloses a source-drain asymmetric ring gate reconfigurable field effect transistor, which comprises nanosheet or nanowire channels, gate oxides, control gates, polarity gates, side walls, a source and a substrate, wherein the nanosheet or nanowire channels are vertically arranged, the gate oxides are wrapped outside the channels and are positioned below the gates and the gate isolations, the control gates and the polarity gates are respectively and symmetrically arranged on the outer sides of the gate oxides, the gate isolations are wrapped outside the channels and are used for isolating the control gates and the polarity gates, the side walls are arranged at the left end and the right end of the channels and are wrapped outside the channels, the source is arranged at one end of each channel, the drain and the other end of each channel extend towards the inside of the source side wall, and the substrate is arranged at the bottom. Compared with the existing source-drain symmetrical device, the source extending towards the inside of the source side wall increases the contact area between the source end and the channel, the tunneling probability of a current carrier line is increased, and the on-state current is improved. When the switch is switched off, the drain end structure is the same as the non-overlapping area of the drain structure of the source-drain symmetrical device, and the off-state current is basically kept unchanged, so that the switch has more ideal current switching ratio and faster logic response.
Description
Technical Field
The invention belongs to the field of field effect transistors in semiconductor devices, and particularly relates to a source-drain asymmetric ring gate reconfigurable field effect transistor.
Background
The shrinking of transistor dimensions has witnessed the development of semiconductor technology, with the continuous advance of process nodes, the degradation of the performance of traditional bulk silicon devices is becoming more and more non-negligible, and economic constraints and process barriers also pose a great challenge to the continuation of moore's law, and many new device structures are proposed one after another in order to meet the requirements of the times. Among them, the nano-sheet Gate-All-Around Field-Effect Transistor (nano sheet Gate-All-Around Field-Effect Transistor) and the nano-wire Gate-All-Around Field-Effect Transistor (nano wire Gate-All-Around Field-Effect Transistor) have excellent Gate control capability and excellent electrostatic integrity, and become one of the structures with 5 nm and below and having attractive force. By vertically arranging the nano-sheet or nano-wire channel, larger saturation current can be obtained on the basis of a certain area, the integration level of the device is improved, and the contradiction between power consumption and performance is solved.
Meanwhile, a Reconfigurable Field Effect Transistor (RFET) receives attention because it has a structural advantage that it can realize a complicated logic circuit with a lower number of transistors. By arranging two independent grids, the device can be flexibly switched between an N type and a P type, the bias voltage of the polar grid determines the carrier type of tunneling in Schottky junctions at two ends, the control grid influences the on-off of the device, and compared with a CMOS-based circuit, the CMOS-based circuit has better function selectivity. However, the dependence of tunneling mechanism still makes the on-state current density of the device smaller, and the application is more limited.
Disclosure of Invention
The invention aims to solve the problem that the on-state current of the existing source-drain symmetrical ring gate reconfigurable field effect transistor is small, and provides a source-drain asymmetrical ring gate reconfigurable field effect transistor.
In order to achieve the purpose, the invention adopts the following technical scheme:
a source-drain asymmetric gate-all-around reconfigurable field effect transistor is characterized in that: it includes:
a plurality of vertically arranged channels;
a source arranged at the left end of the channels and extending towards the inside of the source side wall;
the drain is arranged at the right ends of the channels;
the grid oxide is wrapped on the outer side of each channel and is in isolated contact with the control grid, the polar grid and the grid;
the control grid and the polar grid are symmetrically arranged and wrapped on the outer side of the grid oxide;
the grid isolation is wrapped at the outer side of the channel and arranged between the control grid and the polar grid;
the source side wall is arranged on the left side of the control grid and the right side of the source and wraps the channel;
the drain side wall is arranged on the right side of the polar grid and the left side of the drain and wraps the channel;
a substrate disposed at the bottom of the structure;
the channel is a silicon nano sheet, a germanium-silicon nano sheet, a gallium arsenide nano sheet, a zinc oxide nano sheet or a silicon nano wire, a germanium-silicon nano wire, a gallium arsenide nano wire or a zinc oxide nano wire;
the source and the drain extending towards the inner part of the source side wall are one or a combination of more of titanium silicide, nickel silicide, cobalt silicide, titanium nitride and tantalum nitride;
the grid oxide is silicon dioxide or hafnium oxide;
the control grid and the polar grid are aluminum, copper, polysilicon or titanium nitride formed after photoetching and etching;
the grid isolation is silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, phosphorosilicate glass or borophosphosilicate glass deposited on the outer side of the channel and between the control grid and the polar grid;
the source side wall and the drain side wall are made of silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass or borophosphosilicate glass;
the substrate is bulk silicon, silicon on an insulating layer or germanium on the insulating layer;
the length of the source extending towards the interior of the source side wall is less than that of the source side wall, and the height of the source extending is equal to that of the source side wall; the height of the grid isolation is equal to the sum of the heights of the control grid and the grid oxide and equal to the sum of the heights of the polar grid and the grid oxide;
compared with a common source-drain symmetrical device, the source-drain asymmetrical ring gate reconfigurable field effect transistor provided by the invention has the following advantages:
the off-state current is kept unchanged, meanwhile, the on-state current of the device is increased, and the current switching ratio is improved;
the switching delay time is reduced, the load driving capability is stronger, and the logic processing capability is stronger;
the application range is wide, and the method is suitable for the fields of high power, radio frequency, microwave and the like which need large current.
Drawings
FIG. 1 is a schematic structural diagram of an embodiment of the present invention, which uses a nanosheet as an example;
FIG. 2 is a cross-sectional view taken at A-A in FIG. 1;
FIGS. 3 (a), (B), and (C) are sectional views taken at B-B, C-C, and D-D in FIG. 1, respectively;
FIG. 4 is an energy band diagram of a conventional source-drain symmetric device characterizing N-type and P-type electrical characteristics along a center of a channel in a lateral direction;
FIG. 5 is an energy band diagram illustrating N-type and P-type electrical properties along the center of a channel transverse channel using nanosheets as an example in accordance with the present invention;
FIG. 6 is an energy band diagram of a channel with nanosheets as an example to characterize N-type electrical properties along the longitudinal position of the channel in accordance with the present invention;
FIG. 7 is an energy band diagram of a channel with nanosheets as an example to characterize P-type electrical properties along the longitudinal position of the channel in accordance with the present invention;
FIG. 8 is a graph of transfer characteristics for the present invention and a prior art source drain symmetric device;
FIG. 9 is a graph of the output characteristics of the present invention and a conventional source-drain symmetric device;
fig. 10 is a flow chart of the preparation process of the present invention using nano-sheet as an example.
Detailed Description
The invention is described in detail below with reference to the accompanying drawings and examples using nanosheets as examples.
Referring to fig. 1-3, the source-drain asymmetric ring gate reconfigurable field effect transistor is characterized in that a source composed of metal silicide extends a certain length towards the inside of a source side wall at a nano-sheet channel close to one end of a control gate, the extended length is smaller than the length of the source side wall, and the height of the extended portion is equal to the height of the source side wall.
The source-drain asymmetric ring gate reconfigurable field effect transistor comprises a plurality of vertically arranged channels 1; a source 2 arranged at the left end of the plurality of channels 1 and extending towards the inside of the source side wall 8; a drain 3 arranged at the right end of the plurality of channels 1; a gate oxide 4 wrapped around the outside of each channel 1 and in contact with the control gate 5, the polarity gate 6 and the gate isolation 7; the control grid 5 and the polarity grid 6 are symmetrically arranged and wrapped on the outer side of the grid oxide 4; the grid isolation 7 is wrapped on the outer side of the channel 1 and arranged between the control grid 5 and the polar grid 6; the source side wall 8 is arranged on the left side of the control grid 5 and the right side of the source 2 and wraps the channel 1; the drain side wall 9 is arranged on the right side of the polar grid 6 and the left side of the drain 3 and wraps the channel 1; a substrate 10 provided at the bottom of the above structure;
the channel 1 is a silicon nanosheet, a germanium-silicon nanosheet, a gallium arsenide nanosheet, a zinc oxide nanosheet or a silicon nanowire, a germanium-silicon nanowire, a gallium arsenide nanowire or a zinc oxide nanowire;
the source 2 and the drain 3 extending towards the inside of the source side wall 8 are one or a combination of more of titanium silicide, nickel silicide, cobalt silicide, titanium nitride and tantalum nitride;
the gate oxide 4 is silicon dioxide or hafnium oxide;
the control grid 5 and the polar grid 6 are aluminum, copper, polysilicon or titanium nitride formed after photoetching and etching;
the grid isolation 7 is silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, phosphorosilicate glass or borophosphosilicate glass deposited on the outer side of the channel 1 and between the control grid 5 and the polar grid 6;
the source side wall 8 and the drain side wall 9 are made of silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass or borophosphosilicate glass;
the substrate 10 is bulk silicon, silicon-on-insulator or germanium-on-insulator.
The tunneling of the current carrier in the source-drain symmetrical device occurs in the direction vertical to the electric field of the grid electrode, the tunneling is point tunneling and only occurs at the junction of the grid electrode and the source electrode, and the on-state current is limited by the contact area. The invention adopts a source-drain asymmetric structure, and the source structure extending into the side wall makes the current carrier possible to generate linear tunneling along the direction parallel to the grid electric field. The tunneling area of the device is increased due to the increase of the tunneling of the current carrier lines, so that the on-state current density is increased, the tunneling area of the current carrier can be regulated and controlled according to requirements, the proportion of the tunneling part of the device lines is increased, and the on-state current can be effectively increased. The leakage current of the invention is basically kept unchanged when the device is turned off, so the device has more ideal current switching ratio, and the operation delay time of the logic gate current is shortened under the condition of ensuring that the static power consumption is unchanged.
Fig. 5 and fig. 4 show that the band diagrams of the device of the present invention are different from those of the prior art source-drain symmetric device at the position along the lateral direction of the channel in the on state. The first channel, the second channel and the third channel respectively correspond to three nanosheet channels from top to bottom in the structure diagram of FIG. 1, wherein ECRepresents the conduction band energy level, EVRepresents the valence band energy level, EfnRepresents an electron quasi-Fermi level, EfpRepresents a hole quasi-fermi level, as follows. Shown as channel 1 band diagram. It can be seen that the carriers in the source-drain symmetric device are mainly transported by transverse point tunneling, compared with the method, the height of the transverse tunneling barrier is kept unchanged, the width of the barrier is increased, the tunneling probability is reduced, and the point tunneling current is only one third of the point tunneling currentOne, the first step. The point tunneling of carriers in the present invention contributes less to the on-state current.
Fig. 6 and 7 show band diagrams at positions along the longitudinal direction of the channel when the invention is used in the on-state as an N-type and P-type device, respectively. Along the direction vertical to the channel, the second channel has a lower tunneling probability of carriers but still higher than the point tunneling probability of the source-drain symmetric device because the upper surface and the lower surface are both under the action of the electric field and the acting force of the energy band offsets the part. Under the action of a vertical electric field, the energy band of the first channel and the third channel is bent to form a steep potential barrier, and carriers can generate vertical line tunneling and transit from the surface of the channel to the center to form large on-state current. The on-state current is thus greatly promoted by linear tunneling of carriers in addition to being formed by point tunneling of carriers, and the latter occupies a major part.
FIGS. 8-9 provide transfer and output characteristics, V, for a device symmetric to the source and drain of the present inventionCGRepresenting control gate voltage, VPGRepresenting a polar gate voltage. When the device presents N-type characteristics, the on-state current of the invention is 8.93 multiplied by 10-6A, off-state current of 1.53X 10-14A, the current switching ratio is 5.84 multiplied by 108(ii) a When the device adopts a symmetrical structure, the on-state current is 1.78 multiplied by 10-6A, off-state current of 1.86X 10-14A, current on-off ratio of 9.57X 107. When the device presents P-type characteristics, the on-state current of the invention is 2.37 multiplied by 10-5A, off-state current 1.72X 10-13A, current switching ratio of 1.38 × 108(ii) a When the device adopts a symmetrical structure, the on-state current is 1.34 multiplied by 10-6A, off-state current of 1.47X 10-14A, current on-off ratio of 9.12 × 107. The switch of the source-drain asymmetric ring gate device is improved by one order of magnitude compared with a symmetric device.
Referring to fig. 10, the manufacturing process of the present invention is as follows:
(1) obtaining a silicon substrate 10 by ion implantation and annealing;
(2) growing germanium-silicon, germanium-silicon and silicon stacked films on a silicon substrate 10 in sequence by adopting a molecular beam epitaxy technology;
(3) etching a fin-shaped channel on the silicon substrate 10 by using the side wall as a hard mask by adopting a Self-Aligned Double Patterning technology (Self-Aligned Double Patterning), and performing primary thermal annealing;
(4) depositing polysilicon by chemical vapor deposition, and performing photoetching to form a virtual control gate and a virtual polarity gate;
(5) the chemical vapor deposition technology is adopted, and the deposition source electrical isolation side wall 8 and the leakage electrical isolation side wall 9 are isolated from the virtual grid;
(6) adopting a reactive ion etching technology to anisotropically etch the germanium-silicon stacked layers at the source end and the drain end, wherein the etching length is consistent with the length of the drain side wall 9;
(7) depositing dielectric medium between the nano sheets by adopting a chemical vapor deposition technology to form a source side wall 8 and a drain side wall 9;
(8) adopting a reactive ion etching technology to anisotropically etch the inside of the source side wall 8, wherein the etching length is less than the length of the source side wall 8, and the region of the source 2 extending towards the inside of the source side wall 8 is exposed;
(9) preparing a metal silicide source 2 and a metal silicide drain 3 by adopting a physical vapor deposition technology, filling a gap inside a source side wall 8, and performing rapid annealing;
(10) anisotropically etching the virtual grid and isolating the virtual grid by adopting a reactive ion etching technology, leaving a silicon-germanium-silicon stacked layer, then etching a germanium-silicon material, and releasing the nanosheet channel 1;
(11) deposition of HfO into the nanosheet gap2And an anisotropic etching is adopted for back etching to form a gate oxide 4;
(12) depositing a dielectric medium in the nanosheet gaps by adopting a chemical vapor deposition technology, and photoetching to form a gate isolation 7;
(13) and depositing and etching the control grid 5 and the polar grid 6 by adopting an atomic layer deposition technology, and performing one-time rapid thermal annealing after the deposition is finished to form the structure shown in the figure 1.
The control grid 5, the polar grid 6, the source 2 and the drain 3 are led out through a tungsten plug, all electrodes are flattened by adopting a chemical mechanical polishing technology, and the devices are connected together through metal connecting wires by adopting a CMOS (complementary metal oxide semiconductor) super-large scale circuit subsequent damascene process.
Claims (3)
1. A gate-all-around reconfigurable field effect transistor with asymmetric source and drain, comprising:
a plurality of vertically arranged channels (1);
the source (2) is arranged at the left end of the channels (1) and extends towards the interior of the source side wall (8);
a drain (3) arranged at the right end of the plurality of channels (1);
a gate oxide (4) wrapped around the outside of each channel (1) and in contact with the control gate (5), the polarity gate (6) and the gate isolation (7);
the control grid (5) and the polar grid (6) are symmetrically arranged and wrapped on the outer side of the grid oxide (4);
the grid isolation (7) is wrapped on the outer side of the channel (1) and arranged between the control grid (5) and the polar grid (6);
the source side wall (8) is arranged on the left side of the control grid (5) and the right side of the source (2) and wraps the channel (1);
the drain side wall (9) is arranged on the right side of the polar grid (6) and the left side of the drain (3) and wraps the channel (1);
a substrate (10) disposed at the bottom of the structure.
2. The source-drain asymmetric ring gate reconfigurable field effect transistor according to claim 1, wherein the channel (1) is a silicon nanosheet, a germanium-silicon nanosheet, a gallium arsenide nanosheet, a zinc oxide nanosheet or a silicon nanowire, a germanium-silicon nanowire, a gallium arsenide nanowire or a zinc oxide nanowire;
the source (2) and the drain (3) are one or a combination of more of titanium silicide, nickel silicide, cobalt silicide, titanium nitride and tantalum nitride;
the grid oxide (4) is silicon dioxide or hafnium oxide;
the control grid (5) and the polar grid (6) are aluminum, copper, polysilicon or titanium nitride formed after photoetching and etching;
the grid isolation (7) is silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, phosphorosilicate glass or borophosphosilicate glass deposited on the outer side of the channel (1) and between the control grid (5) and the polar grid (6);
the source side wall (8) and the drain side wall (9) are made of silicon dioxide, silicon nitride, silicon oxynitride, phosphorosilicate glass or borophosphosilicate glass;
the substrate (10) is bulk silicon, silicon-on-insulator or germanium-on-insulator.
3. The source-drain asymmetric ring gate reconfigurable field effect transistor according to claim 1, characterized in that the length of the source (2) extending towards the inside of the source side wall (8) is less than the length of the source side wall (8), and the height of the source (2) extending is equal to the height of the source side wall (8); the height of the gate isolation (7) is equal to the sum of the heights of the control gate (5) and the gate oxide (4) and equal to the sum of the heights of the polarity gate (6) and the gate oxide (4).
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116190426A (en) * | 2023-04-23 | 2023-05-30 | 之江实验室 | Nanosheet transistor and reconstruction and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116190426A (en) * | 2023-04-23 | 2023-05-30 | 之江实验室 | Nanosheet transistor and reconstruction and preparation method thereof |
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