CN117202499A - Circuit board and packaging device - Google Patents
Circuit board and packaging device Download PDFInfo
- Publication number
- CN117202499A CN117202499A CN202210796869.6A CN202210796869A CN117202499A CN 117202499 A CN117202499 A CN 117202499A CN 202210796869 A CN202210796869 A CN 202210796869A CN 117202499 A CN117202499 A CN 117202499A
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- bonding
- transistor
- triode
- bonding pad
- circuit board
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- 238000004806 packaging method and process Methods 0.000 title abstract description 9
- 238000003466 welding Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 abstract description 13
- 238000010586 diagram Methods 0.000 description 10
- 238000005476 soldering Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The invention discloses a circuit board and a packaging device, wherein the circuit board comprises a device mounting surface, at least two triode welding areas are arranged on the device mounting surface, and at least one bonding pad of one triode welding area is arranged on one side of any bonding pad of the other triode welding area and is close to the bonding pad and the body arrangement area of the other triode welding area in the two triode welding areas which are adjacently arranged on a substrate. The circuit board provided by the invention reduces the surface area of the circuit board occupied by two adjacent triodes, so that a certain space is saved when a plurality of triodes are arranged on the circuit board, and other parts are conveniently laid out on the circuit board.
Description
Technical Field
The invention relates to the technical field of electronic component mounting and connection, in particular to a circuit board and a packaging device.
Background
The SMT patch is a circuit mounting technology for mounting pins of an electronic component on package pads on a surface of a circuit board substrate by a reflow soldering or dip soldering method, and the process mainly includes: solder paste printing, part mounting, reflow soldering, AOI optical detection, maintenance and board separation.
In the existing SMT (surface mounted technology) patch method of the triodes, the required mounting area of each triode is mainly composed of the area occupied by the triode body and the connected bonding pad, and in the existing patch method, a plurality of triodes are arranged on the surface of a substrate in a longitudinal or transverse straight line, so that the patch of the triodes occupies a larger area of the substrate, and the layout of integral parts on the substrate is not facilitated.
Disclosure of Invention
The invention mainly aims to provide a circuit board and aims to solve the technical problem that the layout of parts is affected due to the fact that a triode arrangement structure on the circuit board occupies too much area of the circuit board in the prior art.
In order to achieve the above object, the present invention provides a circuit board, comprising:
the device mounting surface is provided with at least two triode welding areas, the triode welding areas comprise a first bonding pad, two second bonding pads and a body setting area, the first bonding pad is arranged on one side of the body setting area, and the two second bonding pads are arranged on the other side of the body setting area at intervals; wherein the method comprises the steps of
And in the two triode welding areas which are adjacently arranged, at least one bonding pad of one triode welding area is arranged at one side of any bonding pad of the other triode welding area and is close to the bonding pad and the body setting area of the other triode welding area.
In some embodiments of the present invention, in the two adjacent triode bonding regions, the first bonding pad of one triode bonding region is disposed at one side of the first bonding pad of the other triode bonding region and is close to the body disposing region of the other triode bonding region.
In some embodiments of the present invention, in the two adjacent transistor bonding areas, a first bonding pad of one transistor bonding area is disposed at one side of any one second bonding pad of the other transistor and is close to the body disposing area of the other transistor bonding area.
In some embodiments of the present invention, in the two adjacent triode bonding regions, the first bonding pad of one triode bonding region is disposed between the two second bonding pads of the other triode bonding region and is close to the body disposing region of the other triode bonding region.
In some embodiments of the present invention, in the two adjacent triode bonding regions, the first bonding pad of one triode bonding region is disposed on a side of the second bonding pad of the other triode bonding region facing away from the other second bonding pad of the other triode bonding region and is close to the body disposition region of the other triode bonding region.
In some embodiments of the present invention, one second bonding pad of any one of the two adjacent transistor bonding pads is disposed between the two second bonding pads of the other transistor bonding pad and is close to the body disposition region of the other transistor bonding pad.
In some embodiments of the present invention, a distance between two second pads of the triode region is greater than a width of the first pad;
and the distance between the two second bonding pads of the triode welding zone is larger than the width of the second bonding pads.
In some embodiments of the present invention, in two adjacent triode bonding regions, a spacing between a bonding pad of one triode bonding region and a bonding pad of the other triode bonding region adjacent thereto is greater than or equal to 0.2mm.
In some embodiments of the present invention, the first bonding pad of the triode region is equidistant from the two second bonding pads of the triode region.
The invention also provides a packaging device, which comprises the circuit board and a triode, wherein the triode comprises a body, a first pin and two second pins, the first pin and the two second pins are arranged on the body, and the triode is arranged in the triode welding area; wherein the method comprises the steps of
The first pins are welded on the first bonding pads, and the second pins are welded on the corresponding second bonding pads.
According to the circuit board and the packaging device, at least one bonding pad of one triode bonding pad is arranged on one side of any bonding pad of the other triode bonding pad and is close to the body arrangement area of the triode bonding pad in the two adjacent triode bonding areas of the device mounting surface of the circuit board, namely, the pin area of the other triode is arranged in a blank area defined by the pins and the side edges of the other triode, so that the distance between bodies of the two adjacent triodes is shortened, the surface area of the circuit board occupied by the two adjacent triodes is reduced, a certain space is saved when a plurality of triodes are arranged on the circuit board, and other parts are conveniently distributed on the circuit board.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an arrangement of transistors on a packaged device according to the prior art;
fig. 2 is a schematic structural diagram of another arrangement of transistors on a packaged device according to the prior art;
fig. 3 is a schematic structural diagram of a circuit board according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of a circuit board according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of a circuit board according to an embodiment of the invention;
fig. 6 is a schematic structural diagram of a circuit board according to an embodiment of the invention
Fig. 7 is a schematic structural diagram of a packaged device according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a packaged device according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a packaged device according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a packaged device according to an embodiment of the present invention.
Reference numerals: 100. a first triode; 200. a second triode; 300-a, first pin; 300-b, first bonding pad; 400-a, second pins; 400-b, second bonding pad; 500. a substrate; 600. a first triode welding zone; 700. a second triode welding zone; 800 body setup area.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
In the present invention, unless specifically stated and limited otherwise, the terms "connected," "affixed," and the like are to be construed broadly, and for example, "affixed" may be a fixed connection, a removable connection, or an integral body; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and/or" as it appears throughout includes three parallel schemes, for example "A and/or B", including the A scheme, or the B scheme, or the scheme where A and B are satisfied simultaneously. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
As shown in fig. 1-2, in the prior art, the transistors on the circuit board are arranged at intervals of straight columns or intervals of straight rows, and a plurality of unused blank areas exist between the first transistor 100 and the second transistor 200, so that the transistors are arranged on the circuit board according to the above manner to cause a plurality of unused areas on the transistors, and in order to ensure normal operation of the transistors, other parts cannot be arranged in the blank areas, that is, the circuit board occupied by the above transistor arrangement manner is large, so that the layout of other parts on the whole circuit board is difficult.
In order to solve the above problems, the present invention provides a circuit board, referring to fig. 3-6, a device mounting surface, the device mounting surface having at least two transistor bonding areas, the transistor bonding areas including a first bonding pad 400-a, two second bonding pads 400-b and a body arrangement area 800, the first bonding pad 400-a being arranged at one side of the body arrangement area 800, the two second bonding pads 400-b being arranged at a distance from one another side of the body arrangement area 800.
And in the two adjacent triode welding areas, at least one bonding pad of one triode welding area is arranged at one side of any bonding pad of the other triode welding area and is close to the body setting area 800 of the other triode welding area.
It should be noted that: the first bonding pad 400-a and the second bonding pad 400-b in the triode bonding region are respectively connected with three pins of the triode in a bonding mode, wherein the first bonding pad 400-a can be opposite to the second bonding pad 400-b, and the first bonding pad 400-a can be arranged on the adjacent side of the second bonding pad 400-b.
It will be appreciated that: at least one bonding pad of one triode bonding area is arranged on one side of any bonding pad of the other triode bonding area and is close to the body arrangement area 800 of the triode bonding area, namely, a pin area of the other triode is arranged in a blank area defined by pins and sides of the other triode, so that the distance between bodies of two adjacent triodes is shortened, the surface area of a circuit board occupied by the two adjacent triodes is reduced, a certain space is saved when a plurality of triodes are arranged on the circuit board, and other parts are conveniently distributed on the circuit board.
Based on the above-mentioned technical solution, a further implementation manner can be adopted by those skilled in the art, referring to fig. 3, the device mounting surface has a first triode bonding region 600 and a second triode bonding region 700 adjacent to each other, wherein the first bonding pad 400-a of the first triode bonding region 600 is disposed at one side of the first bonding pad 400-a of the second triode bonding region 700 and is close to the body-disposed region 800 of the second triode bonding region 700.
Based on the above-mentioned technical solution, a further implementation manner can be adopted by those skilled in the art, referring to fig. 4, the device mounting surface has a first triode bonding region 600 and a second triode bonding region 700 adjacent to each other, wherein a first bonding pad 400-a of the first triode bonding region 600 is disposed between two second bonding pads 400-b of the second triode bonding region 700 and is close to a body placement region 800 of the second triode bonding region 700.
Based on the above-mentioned technical solution, a further implementation manner can be adopted by those skilled in the art, referring to fig. 5, the device mounting surface has a first triode bonding region 600 and a second triode bonding region 700 adjacent to each other, wherein a first bonding pad 400-a of the first triode bonding region 600 is disposed outside one second bonding pad 400-b of the second triode bonding region 700 and is close to a body setup region 800 of the second triode bonding region 700.
Based on the above technical solution, as shown in fig. 6, the device mounting surface has adjacent first transistor bonding pad 600 and second transistor bonding pad 700, one second bonding pad 400-b of the first transistor bonding pad 600 is disposed between two second bonding pads 400-b of the second transistor bonding pad 700 and is close to the body setting region 800 of the second transistor, and one second bonding pad 400-b of the second transistor bonding pad 700 is disposed between two second bonding pads 400-b of the first transistor bonding pad 600 and is close to the body setting region 800 of the first transistor bonding pad 600.
Based on the above technical scheme, the interval between the two second bonding pads 400-b of the triode region is larger than the width of the first bonding pad 400-a.
The spacing between the two second pads 400-b of the transistor bonding pad is greater than the width of the second pads 400-b.
It will be appreciated that the spacing between the second pads 400-b is greater than the widths of the first pads 400-a and the second pads 400-b, facilitating placement of either the first pads 400-a or the second pads 400-b between the two second pads 400-b.
Based on the above technical solutions, one skilled in the art may further adopt an embodiment that the device mounting surface has two adjacent triode bonding regions, and a space between a bonding pad of one triode bonding region and a bonding pad adjacent to the other triode bonding region is greater than or equal to 0.2mm.
It will be appreciated that: the green oil bridge between adjacent bonding pads can be ensured to be normally connected by the spacing between adjacent bonding pads of different triodes being more than or equal to 0.2mm.
Based on the above-mentioned technical solutions, one skilled in the art may further adopt an embodiment that the pitches between the first pad 400-a to the two second pads 400-b of the triode region are equal.
It will be appreciated that: the distances from the two second bonding pads 400-b to the first bonding pads 400-a of the same triode are equal, so that multiple arrangement modes of the triodes in the arrangement process can be ensured to be used simultaneously as much as possible, the occupied space is saved as much as possible, and the space utilization rate is improved.
The invention also provides a packaging device, which comprises the circuit board, and because the packaging device adopts part or all of the technical schemes of the embodiments, the packaging device has at least all of the beneficial effects brought by the technical schemes of the embodiments, and the description is omitted herein.
As shown in fig. 7-10, the package device includes a substrate 500 and at least two transistors, and the at least two transistors are disposed on a circuit board.
The triode body has a first side and a second side, the first side is provided with a first pin 300-a, and the second side is provided with two second pins 400-a arranged at intervals.
Of the two transistors adjacently disposed on the substrate 500, at least one pin of one transistor is disposed on one side of any pin of the other transistor and is close to the first side or the second side of the transistor.
It should be noted that: the transistor is soldered on the substrate 500 through a pin pad, and the general pin pad has the same shape as the pin, and has a size 1.5-2.5 times that of the pin, and one pin of the transistor is disposed on one side of one pin of another transistor, and in essence, one pin pad of the transistor is disposed on one side of one pin pad of another transistor.
I.e. the first pin 300-a of the transistor corresponds to the first bonding pad 300-b and the two second pins 400-a of the transistor correspond to the two second bonding pads 400-b, respectively.
In some embodiments, the first side and the second side of the body of the transistor are disposed opposite.
In some embodiments, the first side and the second side of the body of the transistor are disposed adjacent.
It will be appreciated that: through setting up the pin region of another triode in the blank region that pin and side limit of another triode were defined, draw the interval between the body of two adjacent triodes to reduced the surface area of the circuit board that two adjacent triodes occupy, thereby saved certain space when a plurality of triodes arrange, be convenient for other parts overall arrangement on the circuit board.
Based on the above technical solution, as shown in fig. 7, a further embodiment can be adopted by a person skilled in the art, the substrate 500 is provided with the adjacent first transistor 100 and second transistor 200, and the first pin 300-a of the first transistor 100 is disposed on one side of the first pin 300-a of the second transistor 200 and is close to the first side of the second transistor 200.
That is, the first bonding pad 300-b of the first transistor 100 is disposed at one side of the first bonding pad 300-b of the second transistor 200 and the first bonding pad 300-b of the first transistor 100 is close to the first side of the second transistor 200.
Based on the above technical solution, as shown in fig. 8, a further embodiment can be adopted by a person skilled in the art, wherein the substrate 500 is provided with the adjacent first transistor 100 and second transistor 200, and the first pin 300-a of the first transistor 100 is disposed between the two second pins 400-a of the second transistor 200 and is close to the second side of the second transistor 200.
That is, the first bonding pad 300-b of the first transistor 100 is disposed between the two second bonding pads 400-b of the second transistor 200 and the first bonding pad 300-b of the first transistor 100 is close to the second side of the second transistor 200.
Based on the above technical solution, as shown in fig. 9, a further embodiment can be adopted by a person skilled in the art, wherein the substrate 500 is provided with the adjacent first transistor 100 and second transistor 200, and the first pin 300-a of the first transistor 100 is disposed outside the second pin 400-a of the second transistor 200 and is close to the second side of the second transistor 200.
That is, the first bonding pad 300-b of the first transistor 100 is disposed outside the second bonding pad 400-b of the second transistor 200 and the first bonding pad 300-b of the first transistor 100 is close to the second side of the second transistor 200.
Based on the above technical solution, as shown in fig. 10, the substrate 500 is provided with the adjacent first transistor 100 and second transistor 200, the second side of the first transistor 100 and the second side of the second transistor 200 are opposite, one second pin 400-a of the first transistor 100 is disposed between two second pins 400-a of the second transistor 200, and one second pin 400-a of the second transistor 200 is also disposed between two second pins 400-a of the first transistor 100, and two second pins 400-a of the first transistor 100 are close to the second side of the second transistor 200.
That is, one second pad 400-b of the first transistor 100 is disposed between two second pads 400-b of the second transistor 200, one second pad 400-b of the second transistor 200 is disposed between two second pads 400-b of the second transistor 200, and two second pads 400-b of the second transistor 200 are adjacent to the second side of the first transistor 100.
Based on the above technical scheme, the distance between the two second pins 400-a of the triode is larger than the width of the second bonding pad 400-b of the triode and is also larger than the width of the first bonding pad 300-b of the triode.
Based on the above technical solution, one skilled in the art may further adopt an implementation manner that the distances between the first pin 300-a of the transistor and the two second pins 400-a of the same transistor are equal.
It will be appreciated that: the distances from the two second pins 400-a to the first pins 300-a of the same triode are equal, so that multiple arrangement modes of the triodes in the arrangement process can be simultaneously utilized as much as possible, the occupied space is saved as much as possible, and the space utilization rate is improved.
The foregoing description is only of the optional embodiments of the present invention, and is not intended to limit the scope of the invention, and all the equivalent structural changes made by the description of the present invention and the accompanying drawings or the direct/indirect application in other related technical fields are included in the scope of the invention.
Claims (10)
1. A circuit board, comprising:
the device mounting surface is provided with at least two triode welding areas, the triode welding areas comprise a first bonding pad, two second bonding pads and a body setting area, the first bonding pad is arranged on one side of the body setting area, and the two second bonding pads are arranged on the other side of the body setting area at intervals; wherein the method comprises the steps of
And in the two triode welding areas which are adjacently arranged, at least one bonding pad of one triode welding area is arranged at one side of any bonding pad of the other triode welding area and is close to the bonding pad and the body setting area of the other triode welding area.
2. The circuit board of claim 1, wherein the first bonding pad of one of the two adjacent transistor bonding pads is disposed on one side of the first bonding pad of the other transistor bonding pad and is adjacent to the body-disposed region of the other transistor bonding pad.
3. The circuit board of claim 1, wherein a first bonding pad of one of the two transistor bonding areas disposed adjacently is disposed at one side of any one of the second bonding pads of the other transistor and is adjacent to the body-disposed area of the other transistor bonding area.
4. The circuit board of claim 3, wherein said first bonding pad of one of said transistor bonding pads is disposed between said second bonding pads of the other of said transistor bonding pads and adjacent to said body-disposed region of the other of said transistor bonding pads, of said two adjacent transistor bonding pads.
5. The circuit board of claim 3, wherein of the two transistor bonding areas disposed adjacently, the first bonding pad of one transistor bonding area is disposed on a side of the second bonding pad of the other transistor bonding area facing away from the other second bonding pad of the other transistor bonding area and is adjacent to the body-disposed area of the other transistor bonding area.
6. The circuit board of claim 1, wherein one second bonding pad of any one of the two adjacent transistor bonding pads is disposed between the two second bonding pads of the other transistor bonding pad and is adjacent to the body-disposed region of the other transistor bonding pad.
7. The circuit board of claim 3 or 6, wherein a spacing between two of the second pads of the triode region is greater than a width of the first pad;
and the distance between the two second bonding pads of the triode welding zone is larger than the width of the second bonding pads.
8. The circuit board of claim 1, wherein a spacing between a bonding pad of one of the two adjacent transistor bonding pads and a bonding pad of the other transistor bonding pad adjacent thereto is greater than or equal to 0.2mm.
9. The circuit board of claim 1, wherein a pitch between a first bond pad of the triode region to two second bond pads of the triode region is equal.
10. A packaged device, comprising:
the circuit board of any one of claims 1-9;
the triode comprises a body, a first pin and two second pins, wherein the first pin and the two second pins are arranged on the body, and the triode is arranged in the triode welding area; wherein the method comprises the steps of
The first pins are welded on the first bonding pads, and the second pins are welded on the corresponding second bonding pads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210796869.6A CN117202499A (en) | 2022-07-06 | 2022-07-06 | Circuit board and packaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210796869.6A CN117202499A (en) | 2022-07-06 | 2022-07-06 | Circuit board and packaging device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117202499A true CN117202499A (en) | 2023-12-08 |
Family
ID=89004041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210796869.6A Pending CN117202499A (en) | 2022-07-06 | 2022-07-06 | Circuit board and packaging device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117202499A (en) |
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2022
- 2022-07-06 CN CN202210796869.6A patent/CN117202499A/en active Pending
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