CN217789987U

CN217789987U - Package substrate and electronic component

Info

Publication number: CN217789987U
Application number: CN202221495745.6U
Authority: CN
Inventors: 杨日贵; 余功炽; 柳仁辉
Original assignee: Sky Chip Interconnection Technology Co Ltd
Current assignee: Sky Chip Interconnection Technology Co Ltd
Priority date: 2021-10-21
Filing date: 2022-06-14
Publication date: 2022-11-11
Anticipated expiration: 2032-06-14

Abstract

The utility model discloses a packaging substrate and electronic component, wherein, packaging substrate includes: pins arranged on the package substrate; pad through holes which are arranged on the packaging substrate at intervals with the pins and surround at least one side of the pins; the diameter setting range of the pad through hole is larger than 0.3mm and smaller than 1.5mm or smaller than twice of the diameter of the maximum pin. Through the structure, the utility model discloses can realize that electronic component can siphon away unnecessary soldering tin on the pin when the wave-soldering welding to reduce packaging substrate wave-soldering even tin defect.

Description

Package substrate and electronic component

Technical Field

The present application relates to electronics, and more particularly to a package substrate and an electronic device.

Background

At present, electronic components may be disposed on the package substrate to form different functional circuits. Generally, a conductive hole may be formed in the package substrate, and the electronic component and the package substrate are soldered by inserting a pin of the electronic component into the conductive hole, so that the electronic component and the package substrate can be electrically connected.

In the prior art, a wave soldering process can be generally adopted to perform soldering operation on an electronic element and a package substrate, however, a tin connection defect is easy to occur after the existing wave soldering, so that the package substrate is short-circuited.

SUMMERY OF THE UTILITY MODEL

For solving above-mentioned packaging substrate and electronic component and appear even tin defect behind the wave-soldering welding to lead to packaging substrate to take place the problem of short circuit, the utility model provides a packaging substrate and electronic component.

One technical solution adopted by the present application is to provide a package substrate and an electronic component, the package substrate includes: pins arranged on the package substrate; pad through holes which are arranged on the packaging substrate at intervals with the pins and surround at least one side of the pins; the diameter setting range of the pad through hole is larger than 0.3mm and smaller than 1.5mm or smaller than two times of the maximum diameter of the pin.

Optionally, the pins are arranged in rows or columns; the solder sucking characteristic of the pad through holes is utilized to remove redundant soldering tin of the pins, so that the pad through holes are arranged at intervals corresponding to the pins and are also arranged in rows or columns, and the pad through holes surrounding one side of the pins are at least two rows or two columns to ensure the tin removing effect.

Optionally, the pins are divided into one or more groups, wherein the minimum pitch of the pins in a group does not exceed 1.5mm or 2 times the diameter of the largest pin in the group; when grouping, the spacing between two groups of adjacent pins exceeds 1.5mm or 2 times the diameter of the largest pin in the two groups.

Alternatively, the pad via cross-sectional shape may be circular, rectangular, triangular, or hexagonal.

Optionally, the pad through hole surrounds at least one side of each group of pins, specifically, surrounds the pin on the side away from the moving direction of the package substrate during wave soldering, that is, the last soldered pin of each group on the package substrate during wave soldering.

Optionally, when the maximum diameter of each group of pins is less than or equal to 1.5mm, the diameter of the through holes of the bonding pads which are arranged adjacent to the pins and have the tin removal effect is set to be in a range of 0.3mm to 1.5mm; when the maximum diameter of the group of pins is larger than 1.5mm, the diameter setting range of the pad through holes which are arranged adjacent to the group of pins and have the tin removal effect is 0.3mm to 2 times of the diameter of the maximum pin, wherein the area size and the shape of the pad through holes in the same packaging substrate or the same group of pins can be the same for the convenience of process operation.

Optionally, when the diameter of each group of the pad through holes is smaller than or equal to 1.5mm, the setting range of the pad through hole pitch is 0.3mm to 1.5mm; when the diameter of the pad through holes in the group is larger than 1.5mm, the setting range of the pad through hole distance is 0.3mm to 2 times of the diameter of the largest pad through hole in the group.

In order to solve the technical problem, the application adopts a technical scheme that: there is provided an electronic component comprising a package substrate as described in the above embodiments.

The utility model has the advantages that: be different from prior art's condition, the utility model discloses a packaging substrate is the pad through-hole of row or row range through setting up, utilizes the pad through-hole to inhale the tin characteristic, can inhale away unnecessary soldering tin on the pin when wave-soldering welding to reduce packaging substrate wave-soldering even tin defect by a wide margin, promote packaging substrate's yield.

Drawings

Fig. 1 is a schematic structural diagram of a first embodiment of a package substrate according to the present invention;

fig. 2 is a schematic structural diagram of a second embodiment of a package substrate according to the present invention;

fig. 3 is a schematic structural diagram of a package substrate according to a third embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work all belong to the protection scope of the present invention.

It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are changed accordingly.

In addition, if there is a description relating to "first", "second", etc. in the embodiments of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a package substrate according to a first embodiment of the present invention. The utility model discloses a first embodiment, packaging substrate direction of motion is the X direction during wave-soldering, and packaging substrate 10 includes pin 111-pin 118, pad through-hole 121-pad through-hole 124, and pin 114 also is called the pin interval with the interval d1 of pin 116, and pad through-hole 124 also is called pad through-hole and pin interval with the interval d2 of pin 112, pad through-hole 121 also is called pad through-hole interval with pad through-hole 122 interval d 3. Wherein, the solder is filled in the pins 111-118, and the solder is filled in at least 1 of the pad through holes 121-124.

Referring to fig. 1, in the present embodiment, the leads 111-118 are regularly arranged in two rows on the package substrate 10. In other embodiments, the pins may be arranged in three or more columns, and may also be arranged in rows.

In this embodiment, the cross-sections of the pins 111 to 118 are all circular, the areas are the same, the diameters are all 1.5mm, and the distances d1 between the pins are equal to each other and are half of the radius of the pins. In other embodiments, the cross-section of the leads may have other shapes, and the area size and the pitch of the leads may not be equal.

In this embodiment, the pitch d1 of the adjacent pins is equal and does not exceed 2 times of the diameter of the pins, and the pins are not grouped. In other embodiments, when there is an adjacent pin spacing d1 that exceeds 2 times the maximum pin diameter, then the grouping process is required.

Particularly, in the embodiment, the parallel line direction of the pins is coincident with the X direction, so that when the adjacent pad through holes are arranged for tin absorption, the number and the positions can be determined according to the characteristics of the pins. As shown in fig. 1, two rows of pad through holes 121-124 are disposed adjacent to the

pins

111 and 112, and are parallel to the

pins

111 and 112, and the number of the pad through holes is equal, wherein the cross sections of the pad through holes 121-124 are circular, the diameter of the pad through holes 121-124 is 1.5mm, and the pad through hole distance d3 is equal to the pin distance d 1. In other embodiments, the pad through holes may not have the same shape, the diameters and the intervals of the pad through holes may not be equal, and the pad through holes may be further arranged in three or more rows, or may be arranged in a row. In addition, in other embodiments, when the diameter of the largest pin in the group is smaller than 1.5mm, the diameter of the pad through hole is set in a range of 0.3mm to 1.5mm; when the maximum diameter of the pin is larger than 1.5mm, the diameter of the pad through hole is set to be 0.3mm to 2 times of the diameter of the maximum pin.

In this embodiment, the diameters of the pad through holes 121 to 124 are all 1.5mm, and the pad through hole distance d3 is half of the diameter of the pad through hole 121. In other embodiments, the pad-via pitch may also be set to other values; when the diameter of the pad through hole is smaller than 1.5mm, the setting range of the space between the pad through holes is 0.3mm to 1.5mm; when the diameter of the pad through hole is larger than 1.5mm, the setting range of the pad through hole distance is 0.3mm to 2 times of the maximum pad through hole diameter.

As shown in fig. 1, pad via 121-pad via 124 surround one side of pin 11-pin 118. In wave soldering along the X direction shown in fig. 1, among the pins arranged in two rows, the later soldered pins can absorb the tin tips left when the adjacent and first soldered pins are soldered, the pad through

holes

123 and 124 can absorb the tin tips left when the

corresponding pins

111 and 112 are soldered, and the pad through

holes

121 and 122 can absorb the tin tips left when the previous row of pad through

holes

123 and 124 are not absorbed enough, so that the tin removing effect of the pad through holes 121-124 on the package substrate 10 is effectively ensured.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a package substrate according to a second embodiment of the present invention. In the second embodiment of the present invention, the moving direction of the package substrate is the Y direction during wave soldering, the package substrate 20 includes the pins 211-pins 219 and the pad through holes 22, wherein the solder is filled in each of the pins 211-pins 219, and at least a part of the solder is filled in the pad through holes 22. As shown, the distance between the pin 211 and its adjacent pin 219, pin 216, pin 213, and pin 212 is D1, D2, D3, and D4, respectively, where D1 is the shortest, and the diameter of the pin 213 is larger than the diameters of the other pins.

In the second embodiment, the leads are arranged in three rows on the package substrate, there is a maximum lead 213, and the diameter of the maximum lead 213 is 2 times that of the other leads. In other embodiments, the pins may be arranged in three or more columns, and may also be arranged in rows.

In the second embodiment, the largest pin 213 exists, and as a result of analysis and measurement, the pin pitch in this embodiment does not exceed 2 times the diameter of the largest pin 213, so the pins in this embodiment are not grouped. In other embodiments, when there is a maximum pin, the maximum pin size should also be used as a basis for determining grouping, and when the distance between adjacent pins exceeds 2 times of the maximum pin diameter, grouping should be performed to ensure that the pin distance in each group does not exceed 2 times of the maximum pin diameter of the group.

As shown in fig. 2, in the embodiment, the diameter of the leads 211 on the package substrate 20 is 1mm, the diameter of the leads 213 is 2mm, and the cross-sectional shape of each of the leads is circular; the pad through holes 22 are set to be 1mm in diameter and are all circular. In other embodiments, when the diameter of the largest pin is greater than 1.5mm, the diameter of the pad via 22 is set in the range of 0.3mm to 2 times the diameter of the largest pin; when the diameter of the largest pin is less than or equal to 1.5mm, the diameter setting range of the pad through hole 22 is 0.3mm to 1.5mm; in addition, the pad via holes 22 may be different in shape.

As shown in fig. 2, the package substrate 20 of the present embodiment has two rows of pad through holes 22, the diameter of which is set to be 1mm, and the pitch between adjacent pad through holes is equal to 0.5mm. In other embodiments, the pad through holes may be arranged in three or more columns, and may also be arranged in a row manner; when the diameter of the pad through hole 22 is less than or equal to 1.5mm, the setting range of the pad through hole pitch is 0.3mm to 1.5mm; when the diameter of the pad via hole 22 is larger than 1.5mm, the pad via hole pitch setting range is 0.3mm to 2 times the maximum pad via hole diameter.

In addition, as shown in fig. 2, pad via 22 surrounds one side of pins 211-219. During wave soldering in the Y direction of fig. 2, pad via 22 effectively draws away excess solder from leads 211-219.

In the second embodiment, as shown in fig. 2, the distance between the pin 211 and its adjacent pin is marked, and the method for determining the minimum distance D1 is defined, so as to make up for the deficiencies in the first embodiment. In addition, the pins in the second embodiment have different sizes, and the largest pin 213 exists, so the grouping according to the pin diameter should be performed according to the size of the largest pin 213; the pad via 22 and lead spacing is determined based on the lead diameter, which is also determined based on the size of the largest lead 213. That is, in this embodiment, the variable of the maximum pin is added, and accordingly, the basis of other sizes is changed.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a package substrate according to a third embodiment of the present invention. In the third embodiment of the present invention, the moving direction of the package substrate is the Z direction during wave soldering, the package substrate 30 includes the pins 311-319 and the pad through hole 32, wherein the pins 311-319 are filled with solder, and the pad through hole 32 is filled with solder at least partially.

In this embodiment, the leads 311-319 are arranged in 3 rows on the package substrate, the cross-sections are circular, the areas are the same, and the diameter is 2mm. In other embodiments, the pins may be arranged in two, four or more rows, or may be arranged in columns, and the cross-sections of the pins may be arranged in other shapes or in different areas.

In this embodiment, the diameters of the pins 311 to 319 are all 2mm, that is, the maximum pin diameter is 2mm, the distance between the pin 314 and the pin 317 is 7mm, the distance between the pin 315 and the pin 318 is 7mm, and the distance between the pin 316 and the pin 319 is 7mm, which exceeds 2 times of the maximum pin diameter, so that in this embodiment, the pins are divided into two groups for tin removal, where the pins 311 to 316 are divided into one group and the pins 317 to 319 are divided into one group, that is, in this embodiment, after the grouping, the distance between two adjacent groups of pins is greater than 2 times of the maximum pin diameter, for example: the pitch between the

leads

314 and 317, the pitch between the

leads

315 and 318, and the pitch between the

leads

316 and 319 are the pitches between two adjacent groups of leads. In other embodiments, the pins may also be configured differently, and when the diameter of the largest pin is greater than 1.5mm, the distance between two adjacent groups of pins should be not less than 0.6mm or 2 times the diameter of the largest pin; when the diameter of the largest pin is less than or equal to 1.5mm, the distance between two adjacent groups of pins should be not less than 0.6mm and not more than 3mm.

In this embodiment, the pad through holes 32 are arranged in two rows with a circular cross-sectional shape and a diameter of 2mm. In other embodiments, when the diameter of the pad via 32 is less than or equal to 1.5mm, the pad via 32 pitch setting range is 0.3mm to 1.5mm; when the diameter of the pad through hole 32 is larger than 1.5mm, the distance setting range of the pad through hole 32 is 0.3mm to 2 times of the maximum pad through hole diameter; the cross section of the pad through hole 32 can be set to other shapes, and the areas can be different; the pad vias 32 may also be arranged in three or more columns and may also be arranged in rows.

In the third embodiment, the condition that the distance between adjacent pins is 2 times larger than the maximum pin diameter is added, and the pins are processed in groups, so that the condition that the pins are lacked in the previous case is made up.

In summary, the person skilled in the art can easily understand that the beneficial effects of the present application are: be different from prior art's condition, the utility model discloses a packaging substrate is the pad through-hole of row or row range through setting up, utilizes the pad through-hole to inhale the tin characteristic, can inhale away unnecessary soldering tin on the pin when wave-soldering welding to reduce packaging substrate wave-soldering even tin defect by a wide margin, promote packaging substrate's yield.

The above-mentioned embodiment of the present invention is only, and not the scope of the patent of the present invention is limited, all the equivalent structures or equivalent processes made by the contents of the specification and the drawings are utilized, or directly or indirectly applied to other related technical fields, and all the same principles are included in the patent protection scope of the present invention.

Claims

1. A package substrate, comprising:

pins arranged on the package substrate;

pad through holes which are arranged on the packaging substrate at intervals with the pins and surround at least one side of the pins;

the diameter setting range of the pad through hole is larger than 0.3mm and smaller than 1.5mm or smaller than two times of the maximum diameter of the pin.

2. The package substrate of claim 1, wherein:

the pins are arranged in rows or columns, the pad through holes are arranged corresponding to the pins and are also arranged in rows or columns, and the pad through holes on one side of the pins are at least two rows or two columns.

3. The package substrate of claim 1, wherein:

the pins are divided into a plurality of groups.

4. The package substrate of claim 3, wherein:

the minimum pitch of each group of pins is not more than 1.5mm or 2 times the diameter of the maximum pin of the group.

5. The package substrate according to claim 1 or 2, wherein:

and the pins are filled with soldering tin, and at least part of the pad through holes are filled with the soldering tin.

6. The package substrate of claim 1, wherein:

the pad via cross-sectional shape includes: circular, rectangular, triangular, hexagonal.

7. The package substrate of claim 1, wherein:

when the maximum diameter of the pin is smaller than or equal to 1.5mm, the diameter setting range of the pad through hole is 0.3mm to 1.5mm; when the maximum diameter of the pin is larger than 1.5mm, the diameter setting range of the pad through hole is 0.3mm to 2 times of the maximum pin diameter.

8. The package substrate of claim 1, wherein:

when the diameter of the pad through holes is smaller than or equal to 1.5mm, the setting range of the space between the pad through holes is 0.3mm to 1.5mm; when the diameter of the pad through hole is larger than 1.5mm, the setting range of the distance between the pad through holes is 0.3mm to 2 times of the diameter of the maximum pad through hole.

9. An electronic component, comprising: the package substrate of any of claims 1-8, comprising the leads and the pad vias.