CN117200764A

CN117200764A - Chip and computer device

Info

Publication number: CN117200764A
Application number: CN202210614005.8A
Authority: CN
Inventors: 曹炜; 冯军; 周柏仲
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-05-31
Filing date: 2022-05-31
Publication date: 2023-12-08
Also published as: WO2023231461A1

Abstract

The embodiment of the application provides a chip, which comprises: the device comprises a pulse detection circuit, a filter circuit and an output circuit, wherein the pulse detection circuit is used for acquiring an input signal, determining a first output signal according to the input signal and sending the first output signal to the filter circuit, and the input signal corresponds to an input data signal of a C-port physical layer C-PHY protocol; the filter circuit is used for filtering the first output signal from the pulse detection circuit to obtain a second output signal and sending the second output signal to the output circuit; the output circuit is used for determining a clock signal according to the second output signal. According to the technical scheme, burrs in the first output signal can be reduced or eliminated, so that the occurrence of the beat increasing phenomenon in the determined clock signal can be reduced or even eliminated.

Description

Chip and computer device

Technical Field

The embodiment of the application relates to the technical field of circuits, in particular to a chip and computer equipment.

Background

The C-port physical layer (port physical layer, PHY) protocol is a lower transmission speed than M-PHY, but more readily compatible with D-PHY, as proposed by the mobile industry processor interface (mobile industry processor interface, MIPI) organization.

C-PHYs have many similarities to D-PHYs, most of the characteristics of which are adapted from D-PHYs. Thus, the C-PHY is designed to coexist with the D-PHY on the same integrated circuit (integrated circuit, IC) pin, so that dual mode devices can be developed that support both the C-PHY and the D-PHY.

Although the C-PHY multiplexes most of the D-PHY's standards, the data encoding technique of the C-PHY and the essential differences of the D-PHY are embodied in: 1) The C-PHY uses three signal lines, while the D-PHY uses differential signal line pairs; 2) The C-PHY uses a five-system transmission, while the D-PHY uses a two-system transmission; 3) The C-PHY has no separate clock signal, while the D-PHY has a separate clock signal.

Since there is no separate clock signal, the C-PHY receive system needs to recover the clock signal from the signals transmitted in the three signal lines. Therefore, how to improve the accuracy of the recovered clock signal is a problem that the industry needs to pay attention to.

Disclosure of Invention

The embodiment of the application provides a chip and computer equipment, which can reduce or eliminate burrs in a first output signal, so that the occurrence of a beat increase phenomenon in a determined clock signal can be reduced or even eliminated.

In a first aspect, an embodiment of the present application provides a chip, including: the device comprises a pulse detection circuit, a filter circuit and an output circuit, wherein the pulse detection circuit is used for acquiring an input signal, determining a first output signal according to the input signal and sending the first output signal to the filter circuit, and the input signal corresponds to an input data signal of a C-port physical layer C-PHY protocol; the filter circuit is used for filtering the first output signal from the pulse detection circuit to obtain a second output signal and sending the second output signal to the output circuit; the output circuit is used for determining a clock signal according to the second output signal.

A completed communication link (lane) of the C-PHY is made up of three physical wires, each called A, B, C. The transmitting end always has two lines transmitting high/low different circuits each time a symbol is transmitted, and one line is left to transmit an intermediate level. The input signals acquired by the pulse detection circuit are differential signals, the differential signals comprise differential signals AB, differential signals BC and differential signals CA, wherein the differential signals AB are input data signals A (namely data signals from an A line) and input data signals B (namely data signals from a B line), the differential signals BC are input data signals B and input data signals C (namely data signals from a C line), and the differential signals CA are differential signals CA of the input data signals C and the input data signals A.

The pulse detection circuit may obtain the first output signal by detecting an edge variation of the input signal.

The differential signal AB, the differential signal BC, and the differential signal CA are amplified signals, and thus there is a large jitter in the differential signal AB, the differential signal BC, and the differential signal CA. At the same time, there is also a clock offset (skew) between differential signal AB, differential signal BC, and differential signal CA. The pulse detection circuit output is not a clock signal with the same data frequency, and a plurality of burrs caused by jitter exist, so that the clock is increased, and the clock is increased to cause sampling errors, so that error codes are caused.

The first output signal should ideally be a pulse signal at the same frequency as the data. However, the first output signal output from the pulse detection circuit is a pulse signal containing glitches due to glitches caused by jitter.

According to the technical scheme, the filter circuit capable of filtering high-frequency pulses is additionally arranged between the pulse detection module and the output circuit, so that burrs in output signals of the pulse detection module can be filtered, and the occurrence of the condition that the recovered clock increases the beat at certain time points is reduced or even eliminated. In other words, the number of glitches in the second output signal outputted by the filter circuit is smaller than the number of glitches in the first output signal. Even, in some cases, there may be no glitches in the second output signal. In other words, the second output signal is also a pulse signal, but the second output signal contains a smaller number of glitches than the first output signal.

With reference to the first aspect, in a possible implementation manner of the first aspect, the filtering circuit includes a hysteresis comparator, an integrating circuit, and a comparator, where a first input terminal of the hysteresis comparator is connected to an output terminal of the pulse detection circuit, and a second input terminal of the hysteresis comparator is used to obtain a reference voltage; the first input end of the integrating circuit is connected with the output end of the hysteresis comparator, and the second input end of the integrating circuit is connected with the output circuit and used for acquiring a first control signal from the output circuit; the output end of the integrating circuit is connected with the input end of the comparator, and the output end of the comparator outputs the second output signal; the output circuit is also used for outputting the first control signal.

The technical scheme uses two-stage filtering, wherein the first-stage filtering is realized by a hysteresis comparator, and the second-stage filtering is realized by an integrating circuit and a comparator. A conventional single-limit comparator produces a corresponding jitter (ripple) in the output voltage if the input signal has a small disturbance around the threshold value. The hysteresis comparator has two threshold voltages. The value of the output voltage will be stable as long as the disturbance around the value of the jump voltage does not exceed the difference between the two threshold voltages. Thus, the first stage filtering is implemented with a hysteresis comparator, filtering out some glitches in the first output signal. The second filtering can calculate the total area covered by the discontinuous high pulse train of the previous stage, and output a pulse with the frequency of the data rate, while the burr caused by jitter and not processed by the first filtering can be further averaged by an integrator in the process and can not be output.

With reference to the first aspect, in a possible implementation manner of the first aspect, the filter circuit includes an integrating circuit and a comparator, where a first input terminal of the integrating circuit is connected to an output terminal of the pulse detection circuit, and a second input terminal of the integrating circuit is connected to the output circuit, and is configured to obtain a first control signal from the output circuit; the output end of the integrating circuit is connected with the input end of the comparator, and the output end of the comparator outputs the second output signal; the output circuit is also used for outputting the first control signal.

The above technical solution uses an integrating circuit for filtering. The integrating circuit can calculate the total area covered by the discontinuous high pulse train of the first output signal, output a pulse with the frequency of the data rate, and burrs caused by jitter can be averaged out by the integrator in the process and cannot be output.

With reference to the first aspect, in a possible implementation manner of the first aspect, the integrating circuit includes: the first field effect tube, the second field effect tube, the third field effect tube, the first resistor, the second resistor and the capacitor, wherein the grid electrodes of the first field effect tube and the second field effect tube are connected with the first input end of the integrating circuit, the grid electrode of the third field effect tube is connected with the second input end of the integrating circuit, the first port of the capacitor is connected with the output end of the integrating circuit, the source electrode of the first field effect tube is connected with the first port of the capacitor, and the second port of the capacitor is grounded; the drain electrode of the second field effect tube is connected with the first port of the capacitor, the source electrode of the second field effect tube is connected with the first port of the first resistor, and the second port of the first resistor is grounded; the drain electrode of the third field effect tube is connected with the first port of the capacitor, the source electrode of the third field effect tube is connected with the first port of the second resistor, and the second port of the second resistor is grounded.

According to the technical scheme, the on-resistance and the capacitance of the first field effect transistor are utilized to form the integrating circuit, so that the chip can be conveniently realized.

With reference to the first aspect, in a possible implementation manner of the first aspect, the first resistor is an adjustable resistor, and the adjustable resistor includes a plurality of gear positions.

Configuring different resistors can affect hysteresis windows of different sizes; the specific gear is required to be selected according to the maximum mode dependent jitter (pattern dependent jitter, PDJ) generated by the circuit/channel of the previous stage, so that the method can be suitable for deburring under different conditions. In addition, the hysteresis comparator can be configured with proper gears to achieve the best burr filtering effect with the integrating circuit.

With reference to the first aspect, in a possible implementation manner of the first aspect, the output circuit includes a D flip-flop, a delay circuit, and a control circuit, where the delay circuit is configured to obtain the second output signal, and perform delay processing on the second output signal to obtain a delayed signal; the control circuit is used for generating the first control signal according to the second input signal and the delay signal and sending the first control signal to the integrating circuit, wherein the first control signal is a logic OR signal of the second input signal and the delay signal; the control circuit is further used for determining a second control signal according to the first control signal, wherein the second control signal is a logic NOT signal of the first control signal; the D flip-flop is used for generating the clock circuit according to the second output signal and the second control signal.

With reference to the first aspect, in a possible implementation manner of the first aspect, the filtering circuit includes a hysteresis comparator, wherein a first input terminal of the hysteresis comparator is connected to an output terminal of the pulse detection circuit, a second input terminal of the hysteresis comparator is used for obtaining the reference voltage, and an output terminal of the hysteresis comparator outputs the second output signal.

A conventional single-limit comparator produces a corresponding jitter (ripple) in the output voltage if the input signal has a small disturbance around the threshold value. The hysteresis comparator has two threshold voltages. The value of the output voltage will be stable as long as the disturbance around the value of the jump voltage does not exceed the difference between the two threshold voltages. Thus, filtering with a hysteresis comparator may filter out some glitches in the first output signal.

In a second aspect, an embodiment of the present application provides a chip, where the chip includes a pulse detection circuit, a hysteresis comparator, and an integration circuit, where an input of the pulse detection circuit is used to obtain an input signal, where the input signal corresponds to an input data signal of a C-port physical layer C-PHY protocol; the first input end of the hysteresis comparator is connected with the output end of the pulse detection circuit, and the second input end of the hysteresis comparator is used for obtaining a reference voltage; the output of the hysteresis comparator is connected to the first input of the integrating circuit.

A completed communication link (lane) of the C-PHY is made up of three physical wires, each called A, B, C. The transmitting end always has two lines transmitting high/low different circuits each time a symbol is transmitted, and one line is left to transmit an intermediate level. The input signals acquired by the pulse detection circuit are differential signals including a differential signal AB, a differential signal BC and a differential signal CA. The differential signal AB, the differential signal BC, and the differential signal CA are amplified signals, and thus there is a large jitter in the differential signal AB, the differential signal BC, and the differential signal CA. At the same time, there is also a clock offset (skew) between differential signal AB, differential signal BC, and differential signal CA. The pulse detection circuit output is not a clock signal with the same data frequency, and a plurality of burrs caused by jitter exist, so that the clock is increased, and the clock is increased to cause sampling errors, so that error codes are caused.

The output signal of the pulse detection circuit in the ideal case should be a pulse signal at the same frequency as the data. However, since the glitch is caused by jitter, the output signal output from the pulse detection circuit is a pulse signal containing the glitch.

According to the technical scheme, the hysteresis comparator and the integrating circuit which can filter high-frequency pulses are additionally arranged between the pulse detection module and the output circuit, so that burrs in output signals of the pulse detection module can be filtered, and the occurrence of the condition that the recovered clock increases the shooting at certain time points is reduced or even eliminated.

More specifically, the above-described solution uses two-stage filtering to filter glitches in the signal output by the pulse detection circuit. The first stage of filtering is implemented by a hysteresis comparator and the second stage of filtering is implemented by an integrating circuit. A conventional single-limit comparator produces a corresponding jitter (ripple) in the output voltage if the input signal has a small disturbance around the threshold value. The hysteresis comparator has two threshold voltages. The value of the output voltage will be stable as long as the disturbance around the value of the jump voltage does not exceed the difference between the two threshold voltages. Thus, the first stage filtering is implemented with a hysteresis comparator, filtering out some glitches in the first output signal. The second filtering can calculate the total area covered by the discontinuous high pulse train of the previous stage, and output a pulse with the frequency of the data rate, while the burr caused by jitter and not processed by the first filtering can be further averaged by an integrator in the process and can not be output. In other words, the output signal of the second stage filtering is also a pulse signal, but the output signal contains a smaller amount of glitches than the output signal of the pulse detection circuit.

With reference to the second aspect, in a possible implementation manner of the second aspect, the integrating circuit includes: the first field effect tube, the second field effect tube, the third field effect tube, the first resistor, the second resistor and the capacitor, the grid electrodes of the first field effect tube and the second field effect tube are connected with the first input end of the integrating circuit, the grid electrode of the third field effect tube is connected with the second input end of the integrating circuit, the first port of the capacitor is connected with the output end of the integrating circuit, the source electrode of the first field effect tube is connected with the first port of the capacitor, and the second port of the capacitor is grounded; the drain electrode of the second field effect tube is connected with the first port of the capacitor, the source electrode of the second field effect tube is connected with the first port of the first resistor, and the second port of the first resistor is grounded; the drain electrode of the third field effect tube is connected with the first port of the capacitor, the source electrode of the third field effect tube is connected with the first port of the second resistor, and the second port of the second resistor is grounded.

With reference to the second aspect, in a possible implementation manner of the second aspect, the first resistor is an adjustable resistor, and the adjustable resistor includes a plurality of gear positions.

With reference to the second aspect, in a possible implementation manner of the second aspect, the chip further includes a comparator and an output circuit, where the output circuit includes a D flip-flop, a delay circuit, and a control circuit, a first input terminal of the comparator is connected to an output terminal of the integrating circuit, and a second input terminal of the comparator is used to obtain a reference voltage; the input end of the delay circuit is connected with the output end of the comparator, and the output end of the delay circuit is connected with the first input end of the control circuit; the second input end of the control circuit is used for acquiring a control signal, the first output end of the control circuit is connected with the second input end of the integration circuit, and the second output end of the control circuit is connected with the reset port of the D trigger; the clock port of the D trigger is connected with the output end of the comparator.

In a third aspect, an embodiment of the present application provides a chip, the chip including a pulse detection circuit and an integration circuit, wherein an input terminal of the pulse detection circuit is configured to obtain an input signal, where the input signal corresponds to an input data signal of a C-port physical layer C-PHY protocol; the first input end of the integrating circuit is connected with the output end of the pulse detection circuit.

According to the technical scheme, the integrating circuit capable of filtering high-frequency pulses is additionally arranged between the pulse detection module and the output circuit, so that burrs in output signals of the pulse detection module can be filtered, and the occurrence of the condition that the recovered clock increases the beat at certain time points is reduced or even eliminated. The integrating circuit can calculate the total area covered by the discontinuous high pulse train of the first output signal, output a pulse with the frequency of the data rate, and burrs caused by jitter can be averaged out by the integrator in the process and cannot be output. In other words, the output signal of the integrating circuit is also a pulse signal, but the output signal contains a smaller number of glitches than the output signal of the pulse detecting circuit.

With reference to the third aspect, in a possible implementation manner of the third aspect, the integrating circuit includes: the first field effect tube, the second field effect tube, the third field effect tube, the first resistor, the second resistor and the capacitor, the grid electrodes of the first field effect tube and the second field effect tube are connected with the first input end of the integrating circuit, the grid electrode of the third field effect tube is connected with the second input end of the integrating circuit, the first port of the capacitor is connected with the output end of the integrating circuit, the source electrode of the first field effect tube is connected with the first port of the capacitor, and the second port of the capacitor is grounded; the drain electrode of the second field effect tube is connected with the first port of the capacitor, the source electrode of the second field effect tube is connected with the first port of the first resistor, and the second port of the first resistor is grounded; the drain electrode of the third field effect tube is connected with the first port of the capacitor, the source electrode of the third field effect tube is connected with the first port of the second resistor, and the second port of the second resistor is grounded.

With reference to the third aspect, in a possible implementation manner of the third aspect, the first resistor is an adjustable resistor, and the adjustable resistor includes a plurality of gear positions.

With reference to the third aspect, in a possible implementation manner of the third aspect, the chip further includes a comparator and an output circuit, where the output circuit includes a D flip-flop, a delay circuit, and a control circuit, a first input terminal of the comparator is connected to an output terminal of the integrating circuit, and a second input terminal of the comparator is used to obtain a reference voltage; the input end of the delay circuit is connected with the output end of the comparator, and the output end of the delay circuit is connected with the first input end of the control circuit; the second input end of the control circuit is used for acquiring a control signal, the first output end of the control circuit is connected with the second input end of the integration circuit, and the second output end of the control circuit is connected with the reset port of the D trigger; the clock port of the D trigger is connected with the output end of the comparator.

In a fourth aspect, embodiments of the present application provide a computer device comprising a printed circuit board and a chip of the first aspect, the second aspect, the third aspect or any one of the possible implementations of the first to third aspects, the chip being fixed to the printed circuit board.

Drawings

Fig. 1 is a schematic diagram of a receiving circuit of a receiving end.

Fig. 2 is a schematic diagram of a clock recovery circuit.

Fig. 3 is a timing diagram of a clock recovery circuit recovering a clock.

Fig. 4 is a timing diagram of another clock recovery circuit recovering a clock.

Fig. 5 is a schematic block diagram of a chip according to an embodiment of the present application.

Fig. 6 is a circuit diagram of a clock recovery circuit in the case of adopting scheme 1.

Fig. 7 is a circuit diagram of a clock recovery circuit in the case of adopting scheme 2.

Fig. 8 is a circuit diagram of a clock recovery circuit in the case of adopting scheme 3.

Fig. 9 is a schematic diagram of a hysteresis comparator.

Fig. 10 is a schematic diagram of an integrating circuit.

Fig. 11 is a schematic diagram of an interface circuit according to an embodiment of the present application.

Fig. 12 is a schematic structural diagram of a chip according to an embodiment of the present application.

Fig. 13 is a schematic block diagram of a computer device according to an embodiment of the present application.

Fig. 14 is a schematic block diagram of a pulse detection circuit provided according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

In order to facilitate a better understanding of the technical solutions of the present application, a few techniques related to the technical solutions of the present application will be described first.

A completed communication link (lane) of the C-PHY is made up of three physical wires, each called A, B, C. The transmitting end always has two lines transmitting high/low different circuits each time a symbol is transmitted, and one line is left to transmit an intermediate level. Since the line taking the high/low level is not fixed every time a symbol is transmitted, three lines at a time can represent 3×2=6 states. In the protocol, these 6 states are denoted by +x, -x, +y, +z, -z. Meanwhile, according to the protocol, the code element transmitted each time is necessarily different from the last time, namely the states of three lines are changed each time; i.e. from 6 at a timeOne of the states becomes one of the remaining 5. The C-PHY uses state changes for encoding. Each state change has 5 possibilities, and the C-PHY protocol specifies that the value space of the symbol sequence is defined by 7 consecutive symbols (with state change, i.e., 5 ⁷ =78125 possibilities) to correspond to 16-bit (bit) information space (2 total ¹⁶ =65536 possibilities), although redundancy, coverage can be guaranteed.

At the receiving end, a method of subtracting the signals on three lines from each other is adopted, and a 3bit signal can be obtained each time, and the state of the three lines corresponds to the signal; the corresponding circuit can decode according to the change condition of the 3bit signal and the coding principle defined in the C-PHY protocol to recover the original 2-system information.

Fig. 1 is a schematic diagram of a receiving circuit of a receiving end.

As shown in fig. 1, lines a and B of the three lines A, B, C are connected to a continuous time linear equalizer (continuous time linear equalization, CTLE) 101, lines B and C are connected to CTLE 102, and lines a and C are connected to CTLE 103. CTLE 101 outputs differential signal AB between a line and B line, CTLE 102 outputs differential signal BC between B line and C line, and CTLE103 outputs differential signal CA between C line and a line.

Table 1 is a receiving end encoding table.

TABLE 1

As shown in table 1, when the line state (wire state) is +x, the line voltage received by the a line is high (3/4 volt (V)), the voltage received by the B line is low (1/4V), and the voltage received by the C line is intermediate (1/2V); the differential signal AB is 1/2V, the differential signal BC is-1/4, and the differential signal CA is-1/4. If the value of the differential signal is greater than 0, the corresponding digital output is 1; if the value of the differential signal is less than 0, the corresponding digital output is 0. The digital output at the receiving end is 100 in the case where the on-line state is +x.

To recover the clock signal, a clock recovery circuit is typically connected after CTLE, and the clock recovery circuit recovers the clock signal according to differential signal AB, differential signal BC, and differential signal CA.

Fig. 2 is a schematic diagram of a clock recovery circuit.

The clock recovery circuit 200 shown in fig. 2 includes a pulse detection circuit 201, a D flip-flop (DFF) 202, and a delay line 203.

The pulse detection circuit 201 receives differential signals from CTLE 101 to CTLE 103. The pulse detection circuit 201 outputs a pulse signal with a fixed frequency according to the transitions of the differential signals. The differential signal AB, BC and CA of the C-PHY will hop once per data symbol as required by the C-PHY protocol. Therefore, under ideal conditions, the pulse detection circuit 201 detects the edge variation of the data, and can output a pulse signal with the same frequency as the data rate. Such as a 3.5 gigabit per second (gigabits per second, gbps) data signal, a 3.5GHz narrow pulse may be generated by pulse detection circuit 201. This clock is fed to DFF 202 to sample a constant high level (i.e., tieH as shown in fig. 2), the resulting edges are delayed by a delay line 203 that is configurable to produce a mask (mask) to reset DFF 202 to 0, resulting in a falling edge of the clock, and thus recovering a 3.5G clock at the output of DFF 202, which is used by the C-PHY receive system to sample data for deserializing the a, B, C three-wire code outputs.

Fig. 3 is a timing diagram of a clock recovery circuit recovering a clock.

The AB/BC/CA shown in FIG. 3 is a differential signal AB, a differential signal BC, and a differential signal CA; the edge detection is a signal output from the pulse detection circuit 201; the mask is a mask generated by the delay line 203; the clock signal is the clock of the correct frequency recovered by DFF 202.

Since the differential signal AB, the differential signal BC, and the differential signal CA are signals amplified by CTLE, there is a large jitter in the differential signal AB, the differential signal BC, and the differential signal CA. At the same time, there is also a clock offset (skew) between differential signal AB, differential signal BC, and differential signal CA. The pulse detection circuit 201 outputs a clock signal that is not pure and at the same data frequency and there are many high frequency pulses caused by jitter, and such a clock is unusable. Therefore, a proper mask is selected by the delay line 203 with adjustable subsequent delay to eliminate the high-frequency pulse from the output of the pulse detection circuit 201, and a clock with a correct frequency, that is, the clock signal in fig. 3, is recovered.

An appropriate mask may be found in the timing diagram shown in fig. 3 to recover the clock signal at the correct frequency. However, as products evolve, CTLE before clock recovery circuit is designed to a lower and lower voltage domain (e.g. 1.8V- > 1.2V), and voltage reduction greatly deteriorates linearity of CTLE, resulting in deterioration of jitter of differential signal AB, differential signal BC and differential signal CA. While the actual form of the product may integrate the circuits of the C-PHY and the D-PHY into the same chip for competitive considerations. The CTLE circuits of the C-PHY are often implemented by multiplexing CTLEs of the D-PHY, and the physical design easily causes a mismatch of 3 CTLEs in fig. 1. The intersymbol interference (inter symbol interference, ISI) and insertion loss of the C-PHY channel are also much greater than for the D-PHY. In summary, the high-frequency pulse (also called as burr) which is output by the pulse detection module and is not at the target frequency point can be obviously increased; this can directly lead to glitches in the recovered clock at some point in time, which can lead to clock beat up causing false samples and thus bit errors.

Fig. 4 is a timing diagram of another clock recovery circuit recovering a clock. A clock beat increase due to glitches occurs in the timing diagram shown in fig. 4.

Increasing the mask length is a scheme to filter out unwanted high frequency pulses. But this in turn results in an excessively long mask length, so that the clock for the next beat is reset, resulting in a missing clock beat, which also results in bit errors. If it is desired to filter the high frequency pulses by increasing the mask length while at the same time avoiding the mask length being too long, which results in clock loss, then the mask length of the clock recovery circuit is at least greater than the maximum jitter of the CTLE output, while less than 1 symbol minus the maximum jitter, i.e. satisfies equation 1.1:

max_pdj<Clock _mask <UI-max_ pdj, (equation 1.1)

Wherein the method comprises the steps ofMax_ PDJ is the maximum mode dependent jitter (pattern dependent jitter, PDJ), clock of CTLE output _mask Is the mask length and UI is the length of one symbol.

The constraint of equation 1.1 makes the clock recovery module design very difficult, both to account for jitter in the CTLE output and not to be so large as to reset to the next clock edge that should be recovered. The robustness of the circuit using this scheme is also poor when the process, voltage, and temperature fluctuate.

The application provides a chip, which comprises a clock recovery circuit, wherein a filter circuit capable of filtering burrs is added between pulse detection and DFF, so that burrs in an output signal of a pulse detection module can be filtered without a mode of prolonging a mask, and the occurrence of the condition that the recovered clock is subjected to beat increase at certain time points is reduced.

Fig. 5 is a schematic block diagram of a chip according to an embodiment of the present application. The chip 500 shown in fig. 5 includes a pulse detection circuit 510, a filter circuit 520, and an output circuit 530.

The chip shown in fig. 5 may be a system on chip (SoC), a central processing unit (central processor unit, CPU), an image processor (graphics processing unit, GPU), an application processor (application processor, AP), or the like.

The input signals acquired by the pulse detection circuit 510 are three differential signals, namely a differential signal AB, a differential signal BC and a differential signal CA, output by the CTLE.

The pulse detection circuit 510 is configured to obtain an input signal, determine a first output signal according to the input signal, and send the first output signal to the filter circuit 520.

The pulse detection circuit 510 may use a pulse detection circuit in a clock recovery circuit commonly used at present. For example, pulse detection circuit 510 is typically implemented with simple AND and OR gate combinational logic. Fig. 14 shows schematic diagrams of two pulse detection circuits. The pulse detection circuit as shown in (a) in fig. 14 may be implemented by a delay unit, an exclusive OR gate (XOR), and an OR gate (OR). The pulse detection circuit shown in (b) in fig. 14 may be implemented by a delay unit, a NAND gate (NAND), and an OR gate (OR).

The filtering circuit 520 is configured to filter the first output signal from the pulse detection circuit 510 to reduce glitches in the first output signal. The filtered signal may be referred to as a second output signal. The filter circuit 520 sends the second output signal to the output circuit 530.

The output circuit 530 is configured to determine a clock signal according to the second output signal.

In some embodiments, filtering of glitches may be achieved using a hysteresis comparator. In other words, the filter circuit 520 may be a hysteresis comparator.

In other embodiments, spur filtering may be achieved using an integrating circuit, and then a comparator may be used to output a square wave signal. In other words, the filter circuit 520 may be implemented by an integrating circuit and a comparator.

In other embodiments, spur filtering may be achieved using both a hysteresis comparator and an integrating circuit. In this case, the output signal of the integrating circuit may be processed using a comparator to obtain a square wave. In other words, the filter circuit 520 may include a hysteresis comparator, an integrating circuit, and a comparator.

Table 2 lists possible implementations of the filter circuit.

TABLE 2

Scheme for the production of a semiconductor device	Implementation mode
		Scheme 1	Hysteresis comparator
Scheme 2	Integrating electricityRoad + comparator
		Scheme 3	Hysteresis comparator + integrating circuit + comparator

Schemes 1 to 3 are described below, respectively.

Those skilled in the art will appreciate that the chip may include other components in addition to the pulse detection circuitry, filtering circuitry, and output circuitry. Such as CTLE for acquiring differential signals, logic circuits for processing data, etc. For convenience of description, the pulse detection circuit, the filter circuit, and the output circuit will be generically referred to as a clock recovery circuit hereinafter.

As shown in fig. 6, one input terminal of the hysteresis comparator 521 is connected to the output terminal of the pulse detection circuit 510 for acquiring the output signal of the pulse detection circuit 510, and the other input terminal is used for acquiring the reference voltage Vref.

The output of the hysteresis comparator 521 shown in fig. 6 is connected to a Clock (CLK) pin of the DFF 532. Further, an output terminal of the hysteresis comparator 521 is connected to one terminal of the switch 535, and the other terminal of the switch 535 is connected to an input terminal of the delay circuit 531.

The output of the delay circuit 531 is connected to a control circuit implemented by a logic gate circuit. The control circuit includes an or gate 533 and an nor gate 534. One input of the or gate 533 is connected to the output of the delay circuit 531, and the other input of the or gate 533 is used to acquire an input signal (i.e., ACK shown in fig. 6). An output of the or gate 533 is connected to an input of the nand gate 534, and an output of the nor gate 534 is connected to a reset of the DFF 532.

In some embodiments, the output of delay circuit 531 may also be directly connected to the reset terminal of DFF 532.

The D port of DFF 532 is input with an operating voltage and the Q port output is the recovered clock signal.

When the circuit begins to operate, DFF 532 is reset by an ACK signal, controlling switch 535 to close. In other words, the ACK signal is high at the time the circuit begins to operate, and the ACK signal returns to low after DFF 532 is reset. When the signal output from the hysteresis comparator 531 is low, the DFF 532 does not flip, and Q remains low. When the signal output from the hysteresis comparator 531 is at a high level, the DFF 532 state is inverted, and Q becomes at a high level; after a delay (delay size is determined by the delay circuit 531), the DFF 532 is reset and Q goes low, i.e., the DFF 532 outputs a positive pulse, i.e., a clock pulse is recovered.

Fig. 7 is a circuit diagram of a clock recovery circuit in the case of adopting scheme 2. In the case of adopting scheme 2, the filter circuit shown in fig. 5 includes an integrating circuit 522 and a comparator 523.

As shown in fig. 7, the integrating circuit 522 includes three metal-oxide-semiconductor field effect transistors (MOSFETs) (also simply referred to as MOS transistors) and two resistors. The three MOS transistors can be respectively called as a MOS transistor M1, a MOS transistor M2 and a MOS transistor M3, and the two resistors can be respectively called as a resistor R4 and a resistor R5. In addition, the integrating circuit 522 includes a capacitor, which may be referred to as a capacitor C.

As shown in fig. 7, the gates of the MOS transistors M1 and M2 are connected to the output end of the pulse detection circuit 510, and are configured to receive the first output signal from the output of the pulse detection circuit 510. Thus, the point a shown in fig. 7 can be considered to be equivalent to one input (which may be referred to as a first input) of the integrating circuit 522.

The gate of the MOS transistor M3 is connected to the output end of the or gate 533 in the output circuit 530, and is configured to receive an input signal from the or gate 533. Thus, point b shown in fig. 7 can be considered to be equivalent to the other input (which may be referred to as a second input) of the integrating circuit 522.

As shown in fig. 7, one end of the capacitor C is connected to the source of the MOS transistor M1, and the other end of the capacitor C is grounded. For convenience of description, the end of the capacitor C connected to the MOS transistor M1 may be referred to as a first port of the capacitor C, and the end of the capacitor C grounded may be referred to as a second port of the capacitor C. The first port of the capacitor C is also connected with the drain electrode of the MOS tube M2 and the drain electrode of the MOS tube M3. In addition, the first port of the capacitor C is connected to the positive input of the comparator 523. Thus, point c in fig. 7 can be considered to be equivalent to the output of the integrating circuit 522.

One end of the resistor R5 is connected with the drain electrode of the MOS tube M2. The other end of the resistor R5 is grounded.

One end of the resistor R4 is connected with the drain electrode of the MOS tube M3. The other end of the resistor R4 is grounded.

The resistor R5 shown in fig. 7 is an adjustable resistor, and the adjustable resistor may include a plurality of gear positions, and the plurality of gear positions may be in one-to-one correspondence with a plurality of PDJ. Thus, the integration circuit 522 may be applied to different PDJ scenarios. In other words, the range of the shift position and the burr of the resistor R5 corresponds. Thus, if resistor R5 is an adjustable resistor, different ranges of burrs can be filtered by adjusting the gear of resistor R5.

Of course, in some embodiments, the resistor R5 may also be set to be a fixed resistor. In this case, the resistance of the resistor R5 may be equal to a resistance that can filter a wide range of burrs. Although the same effect as the adjustable resistor can be achieved in this case, a large area is required, which is not beneficial to the integrated design of the chip.

The output of comparator 523 is connected to the CLK pin of DFF 532 as shown in fig. 7. Further, an output terminal of the comparator 523 is connected to one terminal of the switch 535, and the other terminal of the switch 535 is connected to an input terminal of the delay circuit 531.

The output of the delay circuit 531 is connected to a control circuit implemented by a logic gate circuit. The control circuit includes an or gate 533 and an nor gate 534. One input of the or gate 533 is connected to the output of the delay circuit 531, and the other input of the or gate 533 is used to acquire an input signal (i.e., ACK shown in fig. 6). An output of the or gate 533 is connected to an input of the nand gate 534, and an output of the nor gate 534 is connected to a reset of the DFF 532. The output of or gate 533 is also coupled to a second input of integrating circuit 522.

When the circuit shown in fig. 7 starts to operate, DFF 532 is reset by an ACK signal and configuration switch 535 is closed. In other words, the ACK signal is high at the time the circuit begins to operate, and the ACK signal returns to low after DFF 532 is reset. When the MOS tube M1 just starts to charge the capacitor C, the voltage on the capacitor C is lower, namely the voltage at the point C is lower, the corresponding comparator 523 outputs, namely the voltage at the point d is lower, at this time, the DFF 532 cannot overturn, and the Q keeps a low level. When the voltage on the capacitor C exceeds the threshold level (i.e., the input level hi_th of the negative input terminal of the comparator 523), the comparator 523 outputs a high level, i.e., the d point potential is pulled high, the DFF 532 state is inverted, and Q becomes a high level; after a delay (delay size is determined by the delay circuit 531), the DFF 532 is reset and Q goes low, i.e., the DFF 532 outputs a positive pulse, i.e., a clock pulse is recovered. At the same time, the high signal output from the or gate 533 releases the stored charge of the capacitor C.

As shown in fig. 7, when the point a is at the high level, the MOS transistor M2 is turned off and the MOS transistor M1 is turned on. In this case, the on-resistance of the MOS transistor M1 and the capacitor C constitute an integrator, and the charging operation is performed. The integrator composed of the MOS tube M1 and the capacitor C can calculate the total area covered by the discontinuous high pulse train of the upper stage, output a pulse with the frequency of the data rate, and burr caused by jitter can be further averaged by the integrator in the process and cannot be output.

Fig. 8 is a circuit diagram of a clock recovery circuit in the case of adopting scheme 3. In the case of adopting scheme 2, the filter circuit shown in fig. 5 includes a hysteresis comparator 521, an integrating circuit 522, and a comparator 523.

The hysteresis comparator 521 used in the clock recovery circuit shown in fig. 8 is the hysteresis comparator 521 used in the clock recovery circuit shown in fig. 6. The integrating circuit 522 and the comparator 523 employed by the clock recovery circuit shown in fig. 8 are the integrating circuit 522 and the comparator 523 employed by the clock recovery circuit shown in fig. 7.

As shown in fig. 8, one input terminal of the hysteresis comparator 521 is connected to the output terminal of the pulse detection circuit 510 for acquiring the output signal of the pulse detection circuit 510, and the other input terminal is used for acquiring the reference voltage Vref.

An output of the hysteresis comparator 521 is connected to a first input of the integrating circuit 522. In other words, the gates of the MOS transistor M1 and the MOS transistor M2 of the integrating circuit 522 are connected to the output terminal of the hysteresis comparator 521 to obtain the output signal outputted by the hysteresis comparator 521. The connection of the integrating circuit 522, the comparator 523 and the output circuit 530 in fig. 8 is similar to that in fig. 7, and will not be repeated here for brevity.

When the circuit shown in fig. 8 starts to operate, DFF 532 is reset by an ACK signal and configuration switch 535 is closed. In other words, the ACK signal is high at the time the circuit begins to operate, and the ACK signal returns to low after DFF 532 is reset. When the MOS tube M1 just starts to charge the capacitor C, the voltage on the capacitor C is lower, namely the voltage at the point C is lower, the corresponding comparator 523 outputs, namely the voltage at the point d is lower, at this time, the DFF 532 cannot overturn, and the Q keeps a low level. When the voltage on the capacitor C exceeds the threshold level (i.e., the input level hi_th of the negative input terminal of the comparator 523), the comparator 523 outputs a high level, i.e., the d point potential is pulled high, the DFF 532 state is inverted, and Q becomes a high level; after a delay (delay size is determined by the delay circuit 531), the DFF 532 is reset and Q goes low, i.e., the DFF 532 outputs a positive pulse, i.e., a clock pulse is recovered. At the same time, the high signal output from the or gate 533 releases the stored charge of the capacitor C.

In the circuit shown in fig. 8, when the output of the hysteresis comparator 521 makes the point a be at the high level, the MOS transistor M2 is turned off and the MOS transistor M1 is turned on. In this case, the on-resistance of the MOS transistor M1 and the capacitor C constitute an integrator, and the charging operation is performed. The integrator composed of the MOS tube M1 and the capacitor C calculates the total area covered by the discontinuous high pulse train of the upper stage, outputs a pulse with the frequency of the data rate, and the burr which is caused by jitter and is not processed by the front-stage hysteresis comparator 521 can be further averaged by the integrator in the process and cannot be output.

It will be appreciated by those skilled in the art that the hysteresis comparator 521 shown in fig. 6 and 8 is merely an example of a hysteresis comparator. The hysteresis comparator applied to the clock recovery circuit 500 may be a hysteresis comparator of other structures. Fig. 9 is a schematic diagram of a hysteresis comparator.

Fig. 9 (a), fig. 9 (b) and fig. 9 (c) are schematic diagrams of three different hysteresis comparators. In some embodiments, (a) in fig. 9, or (b) in fig. 9 or (c) in fig. 9 may be used instead of the hysteresis comparator 521 shown in fig. 6 and 8. When (a) in fig. 9, (b) in fig. 9 or (c) in fig. 9 are used instead of the hysteresis comparator 521 shown in fig. 6 and 8, vin in (b) in fig. 9 or (c) in fig. 9 is an input terminal of the hysteresis comparator for connecting the pulse detection circuit 510, vout is an output terminal of the hysteresis comparator for the DFF 532 or the integration circuit 522.

Those skilled in the art will appreciate that other hysteresis comparators may be used in place of the hysteresis comparator 521 shown in fig. 6 and 8 in addition to the three hysteresis comparators shown in fig. 9.

Similarly, the integrating circuit 522 shown in fig. 7 and 8 is only an example of one type of integrating circuit. The integrating circuit applied to the clock recovery circuit 500 may be an integrating circuit of other structures. Fig. 10 is a schematic diagram of an integrating circuit.

Fig. 10 (a), fig. 10 (b) and fig. 10 (c) are schematic diagrams of three different integrating circuits. In some embodiments, (a) in fig. 10, (b) in fig. 10 or (c) in fig. 10 may be used instead of the integrating circuit 522 shown in fig. 7 and 8. When (a) in fig. 10, (b) in fig. 10 or (c) in fig. 10 are used instead of the integrating circuit 522 shown in fig. 7 and 8, vin in (b) in fig. 10 or (c) in fig. 10 is an input terminal of the integrating circuit for connecting the pulse detecting circuit 510 or the hysteresis comparator 521, and vout is an output terminal of the integrating circuit for the comparator 523.

Fig. 11 is a schematic diagram of an interface circuit according to an embodiment of the present application. The interface circuit 1100 as shown in fig. 11 includes CTLE circuit 1101 and clock recovery circuit 1102. The clock recovery circuit 1102 may be any one of the clock recovery circuits as in fig. 6-8.

Fig. 12 is a schematic structural diagram of a chip according to an embodiment of the present application. The chip 1200 as shown in fig. 12 includes an interface circuit 1201 and a logic circuit 1202. Logic circuit 1202 is coupled to interface circuit 1201 for receiving signals output by interface circuit 1201.

The chip shown in fig. 12 may be a system on chip (SoC), a central processing unit (central processor unit, CPU), an image processor (graphics processing unit, GPU), an application processor (application processor, AP), or the like.

Fig. 13 is a schematic block diagram of a computer device according to an embodiment of the present application. As shown in fig. 13, a computer device 1300 includes a chip 1301 and a printed circuit board (printed circuit board, PCB) 1302. The chip 1301 is disposed on the PCB 1302.

The computer device 1300 shown in FIG. 13 may also include other necessary elements, such as memory, sensors, display units, input units, audio circuitry, and the like

In some embodiments, computer device 1300 may also include a camera module. The camera module is connected to the chip 1301, and transmits data based on the C-PHY to the chip 1301.

The computer device shown in fig. 13 may be a mobile phone, a notebook computer, a tablet computer, an automobile, a drone, or the like.

In the embodiment shown in fig. 5 and 12, the interface circuit is a circuit internal to the chip. In other embodiments, the interface circuit may be a discrete device. For example, a mobile phone includes a motherboard including a chip therein. The main board is connected with the camera module through a flexible circuit board (flexible printed circuit, FPC) and the interface circuit.

Similarly, the camera module in the computer device shown in fig. 13 may be a separate device. In other words, it may be constituted by a computer system comprising two independent computer devices, which may be referred to as computer device 1 and computer device 2, respectively. Each of the computer devices 1 and 2 may include a chip, a memory, a device of an interface circuit.

In some embodiments, the computer device 1 may be a computer device capable of processing video and/or image functions.

For example, the computer device 1 may be a computer device such as a notebook computer, a desktop computer, or the like. The computer device 2 may be a computer device with camera and/or photographic functionality. For example, the computer device 2 may be a computer device such as a digital still camera, a digital video camera, a video camera, or the like. The computer device 1 includes an interface circuit as shown in fig. 11. The computer device 1 is connected to the computer device 2 via the interface circuit. The computer device 2 transmits the C-PHY based data to the computer device 1. So that the computer device 1 can process the video/image data acquired by the computer device 2.

In other embodiments, the computer device 1 may be a computer device capable of processing video and/or image functions. For example, the computer device 1 may be a computer device such as a notebook computer, a desktop computer, or the like. The computer device 2 is a computer device having a display function. For example, the computer device 2 may be a display, a television, a virtual reality device (VR), an augmented reality (augmented reality, AR) device, or the like. In this case, an interface circuit as shown in fig. 11 is included in the computer device 2. The computer device 2 is connected to the computer device 1 via the interface circuit. The computer device 1 transmits the C-PHY based data to the computer device 2. So that the computer device 2 can display video/image data provided by the computer device 1.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A chip, the chip comprising: pulse detection circuit, filter circuit and output circuit, wherein

The pulse detection circuit is used for acquiring an input signal, determining a first output signal according to the input signal, and sending the first output signal to the filter circuit, wherein the input signal corresponds to an input data signal of a C-port physical layer C-PHY protocol;

the filtering circuit is used for filtering the first output signal from the pulse detection circuit to obtain a second output signal, and sending the second output signal to the output circuit;

The output circuit is used for determining a clock signal according to the second output signal.

2. The chip of claim 1, wherein the filter circuit comprises a hysteresis comparator, an integrating circuit, and a comparator, wherein

The first input end of the hysteresis comparator is connected with the output end of the pulse detection circuit, and the second input end of the hysteresis comparator is used for obtaining a reference voltage;

the first input end of the integrating circuit is connected with the output end of the hysteresis comparator, and the second input end of the integrating circuit is connected with the output circuit and used for acquiring a first control signal from the output circuit;

the output end of the integrating circuit is connected with the input end of the comparator, and the output end of the comparator outputs the second output signal;

the output circuit is also used for outputting the first control signal.

3. The chip of claim 1, wherein the filter circuit comprises an integrating circuit and a comparator, wherein

The first input end of the integrating circuit is connected with the output end of the pulse detection circuit, and the second input end of the integrating circuit is connected with the output circuit and used for acquiring a first control signal from the output circuit;

the output circuit is also used for outputting the first control signal.

4. A chip as claimed in claim 2 or 3, wherein the integrating circuit comprises: a first field effect transistor, a second field effect transistor, a third field effect transistor, a first resistor, a second resistor and a capacitor, wherein

The grid electrodes of the first field effect tube and the second field effect tube are connected with the first input end of the integrating circuit, the grid electrode of the third field effect tube is connected with the second input end of the integrating circuit, the first port of the capacitor is connected with the output end of the integrating circuit,

the source electrode of the first field effect transistor is connected with the first port of the capacitor, and the second port of the capacitor is grounded;

the drain electrode of the second field effect transistor is connected with the first port of the capacitor, the source electrode of the second field effect transistor is connected with the first port of the first resistor, and the second port of the first resistor is grounded;

the drain electrode of the third field effect transistor is connected with the first port of the capacitor, the source electrode of the third field effect transistor is connected with the first port of the second resistor, and the second port of the second resistor is grounded.

5. The chip of claim 4, wherein the first resistor is an adjustable resistor comprising a plurality of gear stages.

6. The chip according to any one of claims 2 to 5, wherein the output circuit comprises a D flip-flop, a delay circuit and a control circuit,

the delay circuit is used for acquiring the second output signal, and performing delay processing on the second output signal to obtain a delay signal;

the control circuit is used for generating the first control signal according to a second input signal and the delay signal and sending the first control signal to the integrating circuit, wherein the first control signal is a logic OR signal of the second input signal and the delay signal;

the control circuit is further used for determining a second control signal according to the first control signal, wherein the second control signal is a logic NOT signal of the first control signal;

the D flip-flop is used for generating the clock circuit according to the second output signal and the second control signal.

7. The chip of claim 1, wherein the filter circuit comprises a hysteresis comparator, wherein

The first input end of the hysteresis comparator is connected with the output end of the pulse detection circuit, the second input end of the hysteresis comparator is used for obtaining the reference voltage, and the output end of the hysteresis comparator outputs the second output signal.

8. The chip according to any one of claims 1 to 7, wherein the pulse detection circuit is in particular configured to detect an edge variation of the input signal, resulting in the first output signal.

9. The chip of any one of claims 1 to 8, wherein the input signals comprise a differential signal AB, a differential signal BC and a differential signal CA, wherein the differential signal AB is a differential signal of an input data signal a and an input data signal B, the differential signal BC is a differential signal of the input data signal B and an input data signal C, and the differential signal CA is a differential signal of the input data signal C and the input data signal a.

10. The chip of any one of claims 1 to 9, wherein the first output signal is a pulse signal containing glitches and the second output signal is a pulse signal containing less glitches than the first output signal.

11. A chip is characterized in that the chip comprises a pulse detection circuit, a hysteresis comparator and an integration circuit, wherein,

the input end of the pulse detection circuit is used for acquiring an input signal, and the input signal corresponds to an input data signal of a C-port physical layer C-PHY protocol;

the output end of the hysteresis comparator is connected with the first input end of the integrating circuit.

12. The chip of claim 11, wherein the integrating circuit comprises: a first field effect transistor, a second field effect transistor, a third field effect transistor, a first resistor, a second resistor and a capacitor,

13. The chip of claim 12, wherein the first resistor is an adjustable resistor comprising a plurality of gear stages.

14. The chip of any one of claims 11 to 13, further comprising a comparator and an output circuit, the output circuit comprising a D flip-flop, a delay circuit and a control circuit,

the first input end of the comparator is connected with the output end of the integrating circuit, and the second input end of the comparator is used for obtaining a reference voltage;

the input end of the delay circuit is connected with the output end of the comparator, and the output end of the delay circuit is connected with the first input end of the control circuit;

the second input end of the control circuit is used for acquiring a control signal, the first output end of the control circuit is connected with the second input end of the integration circuit, and the second output end of the control circuit is connected with the reset port of the D trigger;

The clock port of the D trigger is connected with the output end of the comparator.

15. A chip, characterized in that the chip comprises a logic circuit and an interface circuit, the logic circuit is coupled with the interface circuit, the interface circuit comprises a pulse detection circuit and an integration circuit, wherein,

the first input end of the integrating circuit is connected with the output end of the pulse detection circuit.

16. The chip of claim 15, wherein the integrating circuit comprises: a first field effect transistor, a second field effect transistor, a third field effect transistor, a first resistor, a second resistor and a capacitor,

17. The chip of claim 16, wherein the first resistor is an adjustable resistor comprising a plurality of gear stages.

18. The chip of any one of claims 15 to 17, further comprising a comparator and an output circuit, the output circuit comprising a D flip-flop, a delay circuit and a control circuit,

19. A computer device comprising a printed circuit board and a chip as claimed in any one of claims 1 to 18, the chip being secured to the printed circuit board.