CN116762287A

CN116762287A - Receiver, chip and electronic equipment

Info

Publication number: CN116762287A
Application number: CN202080108242.6A
Authority: CN
Inventors: 许峥嵘
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2023-09-15
Also published as: WO2022141539A1

Abstract

The application discloses a receiver, a chip and electronic equipment, wherein N receiving ends in the receiver can be respectively and correspondingly connected with N signal wires one by one to receive N sub-signals respectively transmitted by the N signal wires. One end of each of the N pull-down resistors is connected with the N receiving ends in one-to-one correspondence, the other end of each of the N pull-down resistors is connected with one end of the negative resistance circuit, and the other end of the negative resistance circuit is grounded. The post-stage circuit is connected with the N receiving ends and can perform differential processing on any two sub-signals in the N sub-signals. The receiver can suppress common mode noise, and is beneficial to improving the anti-interference capability of the receiver.

Description

Receiver, chip and electronic equipment

Technical Field

The present application relates to the field of electronic science and technology, and in particular, to a receiver, a chip, and an electronic device.

Background

With the improvement of the performance of electronic devices, the anti-interference capability of signal transmission in the electronic devices faces an increasingly serious challenge. For example, at generation 5 (5 ^th generation, 5G) smart phones often incorporate camera modules and a large number of antennas. Wherein the camera module can generate data signals according to the acquired image dataThe data signal may carry image data. The camera module is provided with a transmitter which is connected with a receiver in a system on chip (SoC) through a high-speed signal line, so that the camera module can transmit a data signal to the SoC through the high-speed signal line.

Specifically, the data signal may change the level state of the high-speed signal line, and the receiver in the SoC may recognize the change in the level state of the high-speed signal line, thereby receiving the data signal. However, if the antenna in the smart phone transmits signals simultaneously during the period when the high-speed signal line transmits data signals, the antenna may interfere with the data signals transmitted on the high-speed signal line. The antenna generates common mode noise in the high-speed signal line, and the common mode noise can interfere with the level state of the high-speed signal line, so that the SoC cannot receive a correct data signal, and the error rate of the data signal is increased.

In some prior art solutions, an electromagnetic shield may be disposed around the high-speed signal line to enhance the anti-interference capability of signal transmission. However, the electromagnetic shielding cover has high cost, complicated manufacturing procedures of the electronic equipment, and is unfavorable for improving the integration level of the electronic equipment. In view of this, the anti-interference capability of signal transmission in the electronic device is still further to be enhanced.

Disclosure of Invention

The application provides a receiver, a chip and electronic equipment, which are beneficial to improving the anti-interference capability of the receiver in the electronic equipment while reducing the manufacturing cost of the electronic equipment without increasing the manufacturing process of the electronic equipment.

In a first aspect, the present application provides a receiver, which mainly includes N receiving terminals, N pull-down resistors, a negative resistance circuit, and a post-stage circuit, where N is an integer greater than 1. The N receiving terminals can be connected with the N signal lines in a one-to-one correspondence mode respectively, and receive N sub-signals transmitted by the N signal lines respectively. One end of each of the N pull-down resistors is connected with the N receiving ends in a one-to-one correspondence manner, the other end of each of the N pull-down resistors is connected with one end of the negative resistance circuit, and the other end of the negative resistance circuit is grounded; wherein the equivalent resistance of the negative resistance circuit is negative. The post-stage circuit is connected with the N receiving ends and is used for carrying out differential processing on any two sub-signals in the N sub-signals.

In the present application, the value of N is related to the specific implementation of the receiver. For example, if the receiver is a high-speed serial transceiver (SerDes) or a D-class physical layer (D-PHY) receiver, the value of N is 2. If the receiver is a C-class physical layer (C-PHY) receiver, the value of N is 3.

When N is equal to 2, the two sub-signals received by the subsequent stage circuit can be subjected to differential processing. When N is greater than 2, there are a number of possible combinations of two between the N sub-signals. The post-stage circuit may perform differential processing on the two-by-two combinations of the parts, or may perform differential processing on each two-by-two combination, which is not limited in this application.

The application counteracts the common mode impedance brought by the pull-down resistor by adding the negative resistance circuit in the receiver, is beneficial to reducing the common mode impedance of the receiver as a whole, and greatly inhibits common mode noise at the receiving end of the receiver. In theory, when the common mode impedance of the receiver is 0, the common mode noise can be suppressed to 0. In the application, copper foil is not required to be pasted or an electromagnetic shielding structure is not required to be arranged, and the manufacturing process of the electronic equipment is not increased, thereby being beneficial to reducing the manufacturing cost and reducing the space occupation of the electronic equipment. Meanwhile, when the common mode impedance of the receiver approaches 0, common mode noise is favorably suppressed to be close to 0, and the anti-interference capability of data signal transmission is favorably improved.

For example, in the embodiment of the present application, the equivalent resistance of the negative resistance circuit may be any value between-Rt/2N and-3 Rt/2N, where Rt is the resistance of the pull-down resistor. With this implementation, the present application can reduce the common mode impedance by at least half compared to the case without a negative resistance circuit. When the equivalent resistance of the negative resistance circuit is-Rt/N, the common mode impedance of the receiver can be reduced to 0, and thus the common mode noise can be suppressed to 0.

The negative resistance circuit may include an inverter and an N-type metal oxide semiconductor transistor NMOS, an input terminal of the inverter being connected to a drain of the NMOS, an output terminal of the inverter being connected to a gate of the NMOS, a drain of the NMOS being connected to the other ends of the N pull-down resistors, and a source of the NMOS being grounded. Assuming that the input voltage of the inverter is Vn (positive value), the output voltage of the inverter is-Vn, the gate-source voltage controlling the source output current is negative, i.e., -Vn, and the source output current is also negative. That is, the resistance from the drain to the source of the NMOS is negative, and thus the equivalent resistance of the negative resistance circuit is negative.

In order to prevent the bias voltage from being reduced, the embodiments of the present application may at least adopt the following two schemes:

scheme one: common mode capacitor

In one possible implementation, one end of the common mode capacitor is connected to the other end of the negative resistance circuit, and the other end of the common mode capacitor is grounded. Since the bias voltage is a dc voltage and the common mode capacitor has a characteristic of dc cut-off (blocking), the common mode capacitor can prevent the bias voltage of the sub-signal from being lowered.

In another possible implementation, one end of the common mode capacitor is connected to the other ends of the N pull-down resistors, and the other end of the common mode capacitor is connected to one end of the negative resistance circuit. That is, the common mode capacitance is located between the N pull-down resistors and the negative resistance circuit. This is because, for some negative resistance circuits, the dc path therein needs to be conducted to ground to operate. The application directly grounds the other end of the negative resistance circuit, can prevent the common mode capacitor from blocking the direct current path of the negative resistance circuit, so that the negative resistance circuit can keep normal work while preventing the bias voltage of the sub-signal from being reduced.

Scheme II: front capacitor and rear capacitor

The receiver also includes N pre-capacitors and N post-capacitors. One end of the N prepositive capacitors is connected with the N receiving ends in one-to-one correspondence, and the other end of the N prepositive capacitors is connected with one end of the N pull-down resistors in one-to-one correspondence. One end of the N post-capacitors is connected with the other ends of the N pre-capacitors in a one-to-one correspondence mode, and the other ends of the N post-capacitors are connected with the post-circuit.

Specifically, the receiver is connected to the transmitter via N signal lines, and the transmitter outputs N sub-signals. The transmitter comprises a pull-up power supply, and the output current of the pull-up power supply in the transmitter can be prevented from being overlarge by arranging the front capacitor. The receiver also comprises a pull-up power supply, and the output current of the pull-up power supply in the receiver can be prevented from being overlarge by arranging the rear capacitor.

The subsequent stage circuit may apply bias voltages to the received N sub-signals, respectively; any two sub-signals in the N sub-signals after the bias voltage is applied are subjected to differential processing.

Scheme III: rear capacitor

Similar to scheme two, the difference is that the N pre-capacitors can also be located outside the receiver. The specific implementation is not described in detail.

In a second aspect, the present application provides a chip comprising substantially the receiver provided in any one of the above first aspects of the application.

In a third aspect, the present application provides an electronic device, which mainly includes the electronic device provided in the second aspect of the present application.

These and other aspects of the application will be more readily apparent from the following description of the embodiments.

Drawings

FIG. 1 is a schematic diagram of a smart phone structure;

FIGS. 2a and 2b are schematic diagrams of a sub-signal;

FIG. 3 is a schematic diagram of a connection between a transmitter and a receiver;

fig. 4 is a schematic structural diagram of a receiver according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a negative resistance circuit according to an embodiment of the present application;

FIG. 6a is a schematic diagram of the equivalent structure of the pull-down resistor of the negative resistance-less circuit for the sub-signal;

FIG. 6b is a schematic diagram of the equivalent structure of the pull-down resistor of the non-negative resistance circuit for common mode noise;

FIG. 7a is a schematic diagram of an equivalent structure of a pull-down resistor for common mode noise according to an embodiment of the present application;

FIG. 7b is a schematic diagram of an equivalent structure of a pull-down resistor for a sub-signal according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a receiver according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a SerDes or D-PHY structure according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a C-PHY according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a receiver according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a SerDes or D-PHY structure according to an embodiment of the present application;

fig. 13 is a schematic structural diagram of a C-PHY according to an embodiment of the present application;

fig. 14 is a schematic structural diagram of a receiver according to an embodiment of the present application;

fig. 15 is a schematic structural diagram of a receiver according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings. In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings. The specific method of operation in the method embodiment may also be applied to the device embodiment or the system embodiment. In the description of the present application, "at least one" means one or more, wherein a plurality means two or more. In view of this, the term "plurality" may also be understood as "at least two" in embodiments of the present application. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/", unless otherwise specified, generally indicates that the associated object is an "or" relationship. In addition, it should be understood that in the description of the present application, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not for indicating or implying any relative importance or order.

It should be noted that in embodiments of the present application, "connected" may be understood as electrically connected, and two electrical components may be connected directly or indirectly between the two electrical components. For example, a may be directly connected to B, or indirectly connected to B through one or more other electrical components, for example, a may be directly connected to B, or directly connected to C, and C may be directly connected to B, where a and B are connected through C.

In most electronic devices (e.g., smart phones, tablet computers, notebook computers, etc.), information transmission is the basis for implementing the functions of the electronic devices. With the improvement of the performance of electronic devices, the anti-interference capability of signal transmission in the electronic devices faces an increasingly serious challenge.

For example, in the 5G smart phone shown in fig. 1, the smart phone 10 mainly includes an SoC11, a camera module 12, and n antennas (antenna 1 to antenna n), where n is an integer greater than or equal to 1. The SoC11 is connected to the camera module 12 through a signal line 14.

In a specific scenario, the camera module 12 includes a camera, and the camera module 12 may generate a data signal according to image data collected by the camera, where the data signal may carry the image data. The camera module 12 in turn sends the image data to the SoC11 via the signal line 14, so that the SoC11 can further process the image data.

Illustratively, the data signals transmitted by camera module 12 include a sub-signal p and a sub-signal n. As shown in fig. 3, the camera module 12 includes a transmitter 121, and the transmitter 121 is connected to the signal line 14p and the signal line 14 n. The signal line 14p is used for transmitting the sub-signal p, and the signal line 14n is used for transmitting the sub-signal n.

The voltage fluctuation ranges of the sub-signal p and the sub-signal n are the same, and the phases are 180 degrees apart. Specifically, if the sub-signal p is at a high level, the sub-signal n is at a low level. If the sub-signal n is high, the sub-signal p is low.

For example, as shown in fig. 2a, the level states of the sub-signal n and the sub-signal p corresponding to one bit data are schematically shown. In fig. 2a, the sub-signal n is high, the sub-signal p is low, the level difference between the sub-signal p and the sub-signal n is-1.5V, and one bit of data "0" can be transmitted. It is understood that when the sub-signal n is low and the sub-signal p is high, a level difference between the sub-signal n and the sub-signal p is 1.5V, one bit of data "1" may be transmitted.

The SoC11 may receive the data signals, i.e. the sub-signal p and the sub-signal n. The SoC11 may further perform differential processing on the received sub-signal p and the sub-signal n, to obtain a level difference obtained by subtracting the sub-signal n from the sub-signal p, thereby obtaining image data carried by the data signal. For example, if the level difference of the sub-signal p minus the sub-signal n is-1.5V, the data is "0" in one bit, and if the level difference of the sub-signal p minus the sub-signal n is 1.5V, the data is "1" in one bit.

Generally, as shown in fig. 3, the camera module 12 is located outside the mobile phone motherboard, and the camera module 12 is connected to the mobile phone motherboard through a flexible circuit board (flexible printed circuit, FPC) and a Board To Board (BTB) connector. The FPC carries the signal line 14p and the signal line 14n, and is connected to the mobile phone motherboard by the BTB connector, so that the signal line 14p and the signal line 14n can be connected to the SoC11 located on the mobile phone motherboard. It will be appreciated that the portions of the signal lines 14p and 14n on the motherboard of the handset may be implemented by printed circuit board (print circle board, PCB) traces on the motherboard of the handset.

As shown in fig. 3, the SoC11 includes a receiver 111, and the receiver 111 is connected to the signal line 14p and the signal line 14n, respectively, and can receive the sub-signal p and the sub-signal n, respectively. The SoC11 may further acquire image data according to the sub-signal p and the sub-signal n received by the receiver 111, and detailed implementation is not repeated.

On the other hand, as the performance of the camera module 12, such as the number of photo pixels and the number of frames per second of dynamic video, is continuously improved, the transmission rate between the camera module 12 and the SoC11 needs to be synchronously improved. That is, the signal lines 14p and 14n are high-speed signal lines, and the sub-signals p and n are high-speed signals. As shown in fig. 2b, since the sub-signal p and the sub-signal n are high-speed signals, the sub-signal p and the sub-signal n are short in time for transmitting one bit of data. Therefore, the receiver 111 needs to complete the differential processing for the sub-signal p and the sub-signal n in a short time. The receiver 111 is more and more sensitive to external environmental noise due to the loss influence of the PCB wiring and the like, and the error rate of the data signal is improved.

On the other hand, as the 5G age comes, the smart phone 10 adds a plurality of antennas (such as the antennas 1 to n shown in fig. 1) of 5G frequency bands, so that electromagnetic interference (electromagnetic interference, EMI) of the whole smart phone is more dense. When the antennas 1 to n transmit power signals, serious interference can be generated on the exposed parts of the signal lines 14p and 14n, so that common mode noise is introduced into the sub-signals p and n, and further, the improvement of the shooting specification and the product competitiveness of the smart phone 10 are restricted.

Therefore, how to solve the EMI problem of the data signals (including the sub-signal p and the sub-signal n) with low cost and high performance, so that the transmission rate of the data signals is further improved, is an important difficulty affecting the imaging specification and the product competitiveness of the smart phone 10.

Taking fig. 3 as an example, EMI of the data signal is mainly from the signal lines 14p and 14n located at the exposed portion of the FPC. In order to reduce EMI of the data signals, in one current implementation, a metallized grounded electromagnetic shielding structure may be added to the camera module 12, FPC, and BTB. Such as metallized shielding the housing of camera module 12, adding an EMI shielding film to the FPC, or attaching a grounded copper foil to the FPC and BTB connector to shield external EMI.

However, the cost of using this implementation is high and the process is complex. Moreover, the shielding effect of this implementation depends on whether the shielding structure is well grounded. If the number of grounding points is insufficient or the positions of the grounding points are not ideal, the shielding effect may be greatly reduced. In addition, the copper foil is attached to the surface of the FPC to possibly increase the high frequency loss of the signal lines 14p and 14n, which is disadvantageous in further improving the transmission rate of the data signal.

In view of the above, the embodiment of the application provides a receiver, which is provided with a negative resistance circuit to improve the anti-interference capability of data signal transmission. In addition, the embodiment of the application does not need to arrange an electromagnetic shielding structure on the FPC, has lower cost and does not increase the manufacturing process of electronic equipment.

Next, the receiver provided by the embodiment of the present application will be further exemplarily described by taking the transmitter 121 and the receiver 111 in fig. 4 as an example. It should be noted that other structures between the transmitter 121 and the receiver 111, such as FPC, BTB connector, mobile phone motherboard, etc., are omitted to simplify the drawing. In actual construction, however, other constructions may be included between the transmitter 121 and the receiver 111.

As illustrated in fig. 4, the receiver 111 includes N receiving terminals (receiving terminal p1 to receiving terminal pN), N pull-down resistors (pull-down resistor Rt1 to pull-down resistor RtN), a negative resistance circuit Rn, and a post-stage circuit, where N is an integer greater than 1. The N receiving terminals are connected to N signal lines (signal lines 14-1 to 14-N), respectively.

The transmitter 121 may transmit the data signal to the receiver 111 through N signal lines. Specifically, the signal lines 14-1 to 14-N may be referred to as a set of signal lines, and one or more sets of signal lines may be connected between the transmitter 121 and the receiver 111. Each set of signal lines may transmit one data signal, and thus N sub-signals within one data signal may also be referred to as a set of sub-signals. When the transmitter 121 and the receiver 111 are connected by a plurality of sets of signal lines, the transmitter 121 may transmit a plurality of data signals to the receiver 111 in parallel. For ease of understanding, embodiments of the present application will be described below with reference to a set of sub-signals transmitted by a set of signal lines.

The data signal includes N sub-signals (sub-signal 1 to sub-signal N) which are respectively in one-to-one correspondence with the N signal lines. The signal line 1 is used for transmitting the sub-signal 1, the signal line 2 is used for transmitting the sub-signals 2 and … …, and the signal line N is used for transmitting the sub-signal N.

In the embodiment of the present application, the value of N is related to the specific implementation of the receiver 111. For example, if the receiver 111 is a high-speed serial transceiver (SerDes) or a D-class physical layer (D-PHY) receiver, the value of N is 2. If the receiver 111 is a C-class physical layer (C-PHY) receiver, N takes a value of 3. Embodiments of the present application are not specifically recited herein.

Of the N sub-signals, any two sub-signals differ in phase. And at any one time, the average voltage of the N sub-signals is a stable value, which may also be referred to as a bias voltage. For example, in fig. 2a, the average voltage between sub-signal p and sub-signal n at any one time is 0.75V, which 0.75V may also be referred to as the bias voltage.

The latter stage circuit may perform differential processing on any two sub-signals of the N sub-signals. For example, the post-stage circuit may include a differential operation circuit, one input terminal of which may receive one of the two sub-signals, and the other input terminal of which may receive the other of the two sub-signals, and the differential operation circuit may differential-process the two sub-signals to output a voltage difference of the two sub-signals.

Specifically, when N is equal to 2, for example, when the receiver 111 is a SerDes or D-PHY receiver, the receiver 111 and the signal receiver 111 are connected to the signal line 14-1 and the signal line 14-2, and the sub-signal 1 and the sub-signal 2 can be received as differential signals. The latter stage circuit may perform differential processing on the sub-signal 1 and the sub-signal 2, thereby obtaining a voltage difference of the sub-signal 1 minus the sub-signal 2.

When N is greater than 2, there are a number of possible combinations of two between the N sub-signals. The post-stage circuit may perform differential processing on the two-by-two combinations of the two-by-two combinations, or may perform differential processing on each two-by-two combination, which is not limited in the embodiment of the present application.

Illustratively, as in the case where receiver 111 is a C-PHY receiver, sub-signal 1, sub-signal 2, and sub-signal 3 may be received by receiver 111 and signal receiver 111 coupled to signal line 14-1, signal line 14-2, and signal line 14-3, respectively. The phases of the sub-signal 1, the sub-signal 2 and the sub-signal 3 are different from each other, and at any moment, the average voltages of the sub-signal 1, the sub-signal 2 and the sub-signal 3 are bias voltages.

The post-stage circuit may perform differential processing on the sub-signals 1 and 2, the sub-signals 1 and 3, and the sub-signals 2 and 3, respectively, to obtain a voltage difference of subtracting the sub-signal 2 from the sub-signal 1, a voltage difference of subtracting the sub-signal 3 from the sub-signal 1, and a voltage difference of subtracting the sub-signal 3 from the sub-signal 2.

As shown in fig. 4, N pull-down resistors in the receiver 111 are respectively connected to N receiving terminals in one-to-one correspondence. Specifically, one end of the pull-down resistor Rt1 is connected to the receiving terminal p1, one end of the pull-down resistor Rt2 is connected to the receiving terminal p2, … …, and one end of the pull-down resistor RtN is connected to the receiving terminal pN.

The other ends of the N pull-down resistors are connected with one end of a negative resistance circuit Rn, and the other end of the negative resistance circuit Rn is grounded. The negative resistance circuit Rn is a circuit in which the equivalent resistance is negative, that is, the current in the negative resistance circuit Rn decreases with an increase in voltage.

As shown in fig. 5, the negative resistance circuit Rn may include an inverter a and an N-type metal oxide semiconductor transistor (N metal oxide semiconductor, NMOS), wherein an input terminal of the inverter a is connected to a drain of the NMOS, an output terminal of the inverter a is connected to a gate of the NMOS, a drain of the NMOS is connected to the other ends of the N pull-down resistors, and a source of the NMOS is grounded.

As shown in fig. 5, the voltage at one end of the negative resistance circuit Rn is Vn and the voltage at the other end is 0. The input voltage of the inverter A is Vn (positive value), the output voltage is-Vn, the gate-source voltage of the source output current is controlled to be negative, namely-Vn, and the source output current is also controlled to be negative. That is, the resistance from the drain to the source of the NMOS is negative, and thus the equivalent resistance of the negative resistance circuit Rn shown in fig. 5 is negative.

It should be noted that fig. 5 is only an example of the negative resistance circuit Rn, and that other possible implementations of the negative resistance circuit Rn are possible in different application scenarios, which are not listed here.

Next, the anti-interference principle of the embodiment of the present application will be described by taking a scenario in which the receiver 111 is a SerDes as an example.

Suppose that the negative resistance circuit Rn is not provided in the receiver 111:

as shown in fig. 6a, it is assumed that the sub-signal 1 is at a high level and the sub-signal 2 is at a low level, so that the potential of the receiving terminal p1 is higher than that of the receiving terminal p 2. The current is input from the receiving terminal p1, and is output from the receiving terminal p2 through the pull-down resistor Rt1 and the pull-down resistor Rt 2. In this case, the pull-down resistor Rt1 and the pull-down resistor Rt2 may be equivalent to a series relationship.

In the embodiment of the present application, the impedance of the receiver 111 with respect to the sub-signal 1 and the sub-signal 2 may be referred to as differential impedance. As shown in fig. 6a, for the sub-signal 1 and the sub-signal 2, the pull-down resistor Rt1 and the pull-down resistor Rt2 may be equivalently in a series relationship, and thus, the differential impedance zdiff=2rt of the receiver 111, where Rt is the resistance value of the pull-down resistor Rt1 and the pull-down resistor Rt 2.

EMI may generate common mode noise in the signal line 14-1 and the signal line 14-2. As shown in fig. 6b, for common mode noise, current may be input from the receiving terminal p1 and the receiving terminal p2 and output from ground. In this case, the pull-down resistor Rt1 and the pull-down resistor Rt2 may be equivalent to a parallel relationship.

In an embodiment of the present application, the impedance of the receiver 111 to the common mode noise may be referred to as a common mode impedance. As shown in fig. 6b, for common mode noise, the pull-down resistance Rt1 and the pull-down resistance Rt2 may be equivalent to a parallel relationship, and thus, the common mode resistance Zcm =rt/2 of the receiver 111.

It will be appreciated that the greater the common mode impedance, the greater the common mode noise received by the receiver 111. To suppress the common mode noise received by the receiver 111, the common mode impedance of the pull-down resistor Rt1 and the pull-down resistor Rt2 should be reduced as much as possible.

In view of this, the embodiment of the present application sets a negative resistance circuit Rn in the receiver 111:

as shown in fig. 7a, for common mode noise, the pull-down resistance Rt1 and pull-down resistance Rt2 may be equivalently in parallel relationship, with the parallel resistance being Rt/2. One end of the negative resistance circuit Rn is connected to the pull-down resistor Rt1 and the pull-down resistor Rt2, respectively, and the common mode impedance of the receiver 111 can be understood as the equivalent resistance of the negative resistance circuit Rn and the sum of the parallel resistances of the pull-down resistor Rt1 and the pull-down resistor Rt 2.

Since the equivalent resistance of the negative resistance circuit Rn is negative, the negative resistance circuit Rn can partially or completely cancel the common mode impedance generated by the pull-down resistor Rt1 and the pull-down resistor Rt2, so as to reduce the common mode impedance of the receiver 111 as a whole, and the common mode noise received by the receiver 111 can be released to the ground, thereby being beneficial to suppressing the common mode noise.

It can be understood that when the equivalent resistance of the negative resistance circuit Rn is-Rt/2, the common mode impedance of the receiver 111 is Zcm =0. At this time, it can be realized that the common mode noise is suppressed to a level of zero, greatly improving the influence of EMI on the receiver 111.

As shown in fig. 7b, for sub-signal 1 and sub-signal 2, pull-down resistor Rt1 and pull-down resistor Rt2 may still be equivalently in series, and negative resistance circuit Rn does not change the differential impedance of receiver 111.

In summary, the embodiment of the present application counteracts the common mode impedance caused by the pull-down resistor by adding the negative resistance circuit Rn to the receiver 111, which is beneficial to reducing the common mode impedance of the receiver 111 as a whole, so as to greatly suppress the common mode noise at the receiving end of the receiver 111. In theory, when the common mode impedance of the receiver 111 is 0, the common mode noise can be suppressed to 0.

In the embodiment of the application, copper foil is not required to be attached to the FPC, so that the loss of a hardware link is not increased, and the further improvement of the data signal transmission speed is facilitated. In addition, the electromagnetic shielding structure is not required to be arranged in the areas of the camera module 12, the FPC, the BTB connector and the like, and the manufacturing procedure of electronic equipment is not required to be increased, so that the manufacturing cost is reduced, and the space occupation of the smart phone 10 is reduced. Meanwhile, when the common mode impedance of the receiver 111 approaches 0, it is advantageous to suppress the common mode noise to approximately 0, and to improve the anti-interference capability of the data signal transmission.

In particular, the equivalent resistance of the negative resistance circuit Rn may be set to any value between-3 Rt/2N and-Rt/2N, that is, the equivalent resistance of the negative resistance circuit Rn may be equal to-Rt/2N, or equal to-3 Rt/2N, or greater than-3 Rt/2N and less than-Rt/2N, where Rt is the resistance of each pull-down resistor.

For example, as shown in FIG. 8, the value of N is 2 in D-PHY and SerDes, that is, the equivalent resistance of the negative resistance circuit Rn can be set to any value between-3 Rt/4 and-Rt/4. As shown in fig. 6b, in the case where the negative resistance circuit Rn is not provided, the common mode impedance of the receiver 111 is a parallel resistance of two pull-down resistors, that is, rt/2. Therefore, setting the equivalent resistance of the negative resistance circuit Rn to an arbitrary value between-3 Rt/4 and-Rt/4 can reduce the common mode impedance of the receiver 111 to an arbitrary value between-Rt/4 and Rt/4. Compared with the common-mode impedance Rt/2 when the negative resistance circuit Rn is not arranged, the negative resistance circuit Rn provided by the embodiment of the application can offset at least half of the common-mode impedance and completely offset the value of the common-mode impedance (namely-Rt/2).

As another example, as shown in fig. 9, N takes a value of 3 in the C-PHY, that is, the equivalent resistance of the negative resistance circuit Rn may be set to any value between 3-Rt/6 to-Rt/6. Similar to the case of n=2 shown in fig. 6b, in the case where the negative resistance circuit Rn is not provided, the common mode impedance of the receiver 111 is the parallel resistance of three pull-down resistors, that is, rt/3. Therefore, the equivalent resistance of the negative resistance circuit Rn is set to any value between 3-Rt/6 and-Rt/6, and the common-mode impedance of the receiver 111 can be reduced to any value between-Rt/6 and Rt/6. Compared with the common mode impedance Rt/3 when the negative resistance circuit Rn is not arranged, the negative resistance circuit Rn provided by the embodiment of the application can offset at least half of the common mode impedance and completely offset the value of the common mode impedance (namely-Rt/3).

As described above, at any one time, the average voltage of the N sub-signals is a stable bias voltage. It will be appreciated that the bias voltage is a dc voltage and each sub-signal may be considered to fluctuate within a voltage range centered around the bias voltage. Thus, each sub-signal can be divided into a bias voltage and an ac voltage, which can represent the voltage difference between the voltage of the sub-signal at any time and the bias voltage. For example, the bias voltage of the sub-signal 1 is 0.75, the ac voltage is V1 (t) -0.75, where V1 (t) represents the voltage of the sub-signal 1 at the time point t.

In the embodiment of the present application, the negative resistance circuit Rn is included in the receiver 111, so that the common mode impedance of the receiver 111 can be reduced. Since the bias voltage is a dc voltage, which corresponds to a common mode signal, the bias voltage may be reduced while reducing the common mode impedance of the receiver 111. The negative resistance circuit Rn may cause the bias voltage of the sub-signal to drop to 0 when the common mode impedance of the receiver 111 approaches 0.

When the bias voltage of the sub-signal decreases, the subsequent circuit may not recognize each sub-signal it receives. In view of this, the embodiment of the present application can at least keep the bias voltage in the sub-signal from being reduced by any one of the following schemes.

Scheme one: common mode capacitor

In one possible implementation, as shown in fig. 8, one end of the common mode capacitor Ccm is connected to the other end of the negative resistance circuit Rn, and the other end of the common mode capacitor Ccm is grounded. The common mode capacitor Ccm can realize direct current open circuit and alternating current short circuit. For the bias voltage, it is a stable direct current voltage, and thus the common mode capacitance Ccm can prevent the bias voltage from being lowered. The common mode noise is an alternating voltage, so that the common mode capacitor Ccm has small influence on the common mode noise, and the common mode noise can still be released through the ground.

For example, the connection between the common mode capacitance Ccm and the negative resistance circuit Rn in D-PHY and SerDes may be as shown in fig. 9. The connection between the common mode capacitance Ccm and the negative resistance circuit Rn in the C-PHY may be as shown in fig. 10.

In another possible implementation, as shown in fig. 11, one end of the common mode capacitor Ccm is connected to the other ends of the N pull-down resistors, and the other ends of the common mode capacitor Ccm are connected to one ends of the negative resistance circuit Rn.

Specifically, the negative resistance circuit Rn is often an active circuit, and in some configurations of the negative resistance circuit Rn, the dc path in the negative resistance circuit Rn needs to be turned on to operate. If the common-mode capacitor Ccm is spaced between the negative resistance circuit Rn and the ground, the dc path in the negative resistance circuit Rn is disconnected, so that the negative resistance circuit Rn cannot work normally.

In the receiver 111 shown in fig. 11, the negative resistance circuit Rn is directly grounded, and the dc path of the negative resistance circuit Rn can be turned on while the bias voltage of each sub-signal is kept not to be lowered by the common mode capacitor Ccm, so that the negative resistance circuit Rn can operate normally. For example, the connection between the common mode capacitance Ccm and the negative resistance circuit Rn in D-PHY and SerDes may be as shown in fig. 12. The connection between the common mode capacitance Ccm and the negative resistance circuit Rn in the C-PHY may be as shown in fig. 13.

Scheme II: front capacitor and rear capacitor

As shown in fig. 14, the receiver 111 further includes N pre-capacitors C11 to C1N, and N post-capacitors C21 to C2N.

One end of the N prepositive capacitors is connected with the N receiving ends in one-to-one correspondence, and the other end of the N prepositive capacitors is connected with one end of the N pull-down resistors in one-to-one correspondence. One end of the N post-capacitors is connected with the other ends of the N pre-capacitors in a one-to-one correspondence mode, and the other ends of the N post-capacitors are connected with the post-circuit.

Specifically, a pull-up power source is provided in the transmitter 121, and the pull-up power source is connected to the signal lines 14-1 and 14-N, respectively, and the transmitter 121 can control the connection and disconnection between the pull-up power source and each signal line, respectively, so as to control the voltage of each sub-signal.

It will be appreciated that if the pull-down resistors Rt1 to RtN in the receiver 111 and the negative resistance circuit Rn can implement a dc short circuit, the output current of the pull-up power supply in the transmitter 121 will be too large, which is detrimental to the safety of the transmitter 121 and the receiver 111. Accordingly, the pre-capacitors C11 to C1N can be provided, preventing a large current from occurring in the signal lines 14-1 to 14-2.

Since the pre-capacitors C11 to C1N have a characteristic of direct current breaking (blocking), the pre-capacitors C11 to C1N can drop the bias voltage of the sub-signals 1 to N to 0.

In this case, a pull-up power supply may be included in the post-stage circuit, and the post-stage circuit may apply a bias voltage to the received sub-signal through the pull-up power supply. For example, the bias voltage in the sub-signal is 0.75V, and the bias voltage drops to 0V after being blocked by N pre-capacitors. Then, the post-stage circuit may apply a bias voltage of 0.75V to each sub-signal, and it may be understood that the post-stage circuit increases the voltage of each sub-signal by 0.75V simultaneously.

It will be appreciated that if the pull-down resistors Rt1 to RtN in the receiver 111 and the negative resistance circuit Rn can implement dc short-circuiting, the output current of the pull-up power supply in the subsequent circuit will be too large, which is also detrimental to the safety of the transmitter 121 and the receiver 111. Accordingly, the post-capacitors C21 to C2N can be provided, preventing the output current of the pull-up power supply in the post-stage circuit from being excessively large.

Scheme III:

as illustrated in fig. 15. The N signal lines (signal lines 14-1 to 14-N) include N pre-capacitors (pre-capacitors C11 to C1N) respectively connected in one-to-one correspondence with the N receiving ends of the receiver 111.

In this case, the receiver 111 may include N post-capacitors, one ends of which are respectively connected to N receiving terminals in one-to-one correspondence, and the other ends of which are connected to a post-stage circuit.

It will be appreciated that scheme three is similar to scheme two, except that the pre-capacitors C11 to C1N in scheme three may also be located external to the receiver 111. For example, the front capacitors C11 to C1N may be disposed on the mobile phone motherboard shown in fig. 3. The specific principle of the third scheme is not repeated.

Based on the same technical concept, the embodiment of the application also provides a chip, which can be a universal serial bus (universal serial bus, USB) chip, a high-speed serial computer expansion bus (peripheral component interconnect express, PCI-E) chip, a processor chip, an SoC chip, an electronic control unit (electronic control unit, ECU), a graphics processor (graphics processing unit, GPU), an application specific integrated circuit (application specific integrated circuits, ASIC) and the like. The chip may receive a data signal through the receiver 111 provided in the embodiment of the present application and process the data signal.

Based on the same technical concept, the embodiment of the application also provides electronic equipment, which can comprise the chip. By way of example, the electronic device may be a smart phone, tablet, wireless base station, switch, router, internet high-end server, etc.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

The receiver is characterized by comprising N receiving ends, N pull-down resistors, a negative resistance circuit and a post-stage circuit, wherein N is an integer greater than 1;

the N receiving terminals are used for being connected with the N signal lines in a one-to-one correspondence mode respectively and receiving N sub-signals transmitted by the N signal lines respectively;

one end of the N pull-down resistors is connected with the N receiving ends in a one-to-one correspondence manner, the other end of the N pull-down resistors is connected with one end of the negative resistance circuit, and the other end of the negative resistance circuit is grounded; wherein the equivalent resistance of the negative resistance circuit is negative;

the back-stage circuit is connected with the N receiving ends and is used for carrying out differential processing on any two sub-signals in the N sub-signals.
The receiver of claim 1, wherein the receiver further comprises a common mode capacitance;

one end of the common mode capacitor is connected with the other end of the negative resistance circuit, and the other end of the common mode capacitor is grounded.
The receiver of claim 1, wherein the receiver further comprises a common mode capacitance;

one end of the common mode capacitor is connected with the other ends of the N pull-down resistors, and the other end of the common mode capacitor is connected with one end of the negative resistance circuit.
A receiver according to any one of claims 1 to 3, further comprising N pre-capacitors and N post-capacitors;

one end of the N prepositive capacitors is respectively connected with the N receiving ends in a one-to-one correspondence manner, and the other end of the N prepositive capacitors is respectively connected with one end of the N pull-down resistors in a one-to-one correspondence manner;

one end of the N post-capacitors is connected with the other ends of the N pre-capacitors in a one-to-one correspondence mode, and the other ends of the N post-capacitors are connected with the post-circuit.
A receiver according to any one of claims 1 to 3, wherein the N signal lines comprise N pre-capacitors, the N pre-capacitors being respectively connected in one-to-one correspondence with N receiving ends of the receiver;

the receiver further comprises N post-capacitors, one ends of the N post-capacitors are respectively connected with the N receiving ends in a one-to-one correspondence mode, and the other ends of the N post-capacitors are connected with the post-circuit.
The receiver according to claim 4 or 5, wherein the post-stage circuit is specifically configured to:

respectively applying bias voltages to the N sub-signals;

and carrying out differential processing on any two sub-signals in the N sub-signals after the bias voltage is applied.
The receiver according to any one of claims 1 to 6, wherein the equivalent resistance of the negative resistance circuit is any value between-3 Rt/2N and-Rt/2N, where Rt is the resistance of the pull-down resistor.
The receiver according to any one of claims 1 to 7, wherein the negative resistance circuit comprises an inverter and an N-type metal oxide semiconductor transistor NMOS, an input terminal of the inverter is connected to a drain of the NMOS, an output terminal of the inverter is connected to a gate of the NMOS, a drain of the NMOS is connected to the other end of the N pull-down resistors, and a source of the NMOS is grounded.
The receiver according to any of claims 1 to 8, wherein the receiver is a class C physical layer C-PHY receiver, or a class D physical layer D-PHY receiver, or a high speed serial transceiver SerDes.
A chip comprising a receiver as claimed in any one of claims 1 to 9.
An electronic device comprising the chip of claim 10.