CN109286396B

CN109286396B - Physical layer circuit for multi-wire interface

Info

Publication number: CN109286396B
Application number: CN201810799479.8A
Authority: CN
Inventors: 章晋祥; 张原熏; 吕岳全; 王怀德
Original assignee: M31 Technology Corp
Current assignee: M31 Technology Corp
Priority date: 2017-07-19
Filing date: 2018-07-19
Publication date: 2022-04-08
Anticipated expiration: 2038-07-19
Also published as: CN114629493A; CN109286396A; TW201918805A; TWI670577B

Abstract

A physical layer circuit for a multi-wire interface comprising four-signal or six-signal physical media add-on sub-layers, comprising: a four signal physical media additional sublayer coupled to the four signal pads, comprising: a four-signal terminal circuit coupled to the four signal pads; a first differential amplifier coupled to a first signal pad and a second signal pad; a second differential amplifier coupled to the first signal pad and a third signal pad; a third differential amplifier coupled to the two switches, selectively coupled to the second signal pad and the third signal pad or the third signal pad and a fourth signal pad; a first signal processing block coupled to the first differential amplifier; a second signal processing block coupled to the first, second and third differential amplifiers; and a third signal processing block coupled to the third differential amplifier; thus, a pad arrangement mode, a termination circuit, a de-sequencing architecture and a clock and data recovery circuit are provided.

Description

Physical layer circuit for multi-wire interface

Technical Field

The present invention relates to a multi-wire data interface, and more particularly, to a phy layer circuit and phy additional sublayer for different phy layer modes of a multi-wire data interface.

Background

Mobile devices such as smart phones include various components for different purposes, such as application processors (application processors), displays, CMOS image sensors, and the like. These elements need to be interconnected by a physical interface, e.g. the application processor may provide frame data to the display via an interface to present visual content. Alternatively, the CMOS image sensor may provide the sensed image data to the application processor through an interface to output a photograph or video.

The MIPI specification established by the Mobile Industry Processor Interface (MIPI) alliance is widely used for the communication of signals and data between the elements of the Mobile device. MIPI D-PHY is one of the MIPI specifications. In the MIPI D-PHY interface, communication is achieved through one clock lane and one to four data lanes. Each data lane contains a differential signal pair. The clock channels are used for transmitting differential clock signals, and each data channel is used for transmitting differential data signals.

To meet the high-speed transmission requirements of specific data (e.g., image data), the MIPI alliance has newly developed and defined the MIPI C-PHY specification. In the MIPI C-PHY interface, communication is performed through three signal lines. The signal lines respectively transmit three-valued signals, which can be converted into binary logic signals. One feature of the MIPI C-PHY is that a clock is embedded in the data signal, and the receiving end performs clock and data recovery when receiving the data signal.

While the MIPI C-PHY interface can efficiently enable high speed signal communication and can provide high throughput, this interface is not essential to all elements and requirements in the mobile device. It would be quite acceptable for the manufacturer if the vendor could provide functional blocks and/or integrated circuits that are applicable to both specifications. Therefore, there is a need to provide integrated circuits or semiconductor devices that support the MIPI D-PHY and MIPI C-PHY specifications.

Disclosure of Invention

It is an object of the present invention to provide a physical layer circuit and multiple signal physical media additional sub-layer for different physical layer modes of a multi-wire (multi-wire) interface. The physical layer circuit and physical media addition sublayer proposed by the present invention has been designed to take into account the difference in signal characteristics between different physical layer modes, such as MIPI D-PHY and MIPI C-PHY. A two-in-one physical layer (combo PHY) device is thereby realized that can seamlessly connect with either a MIPI D-PHY based device or a MIPI C-PHY based device.

An embodiment of the present invention provides a physical layer circuit, including: four signal pads and a four signal physical media additional sublayer. The four signal entity medium additional sublayers are coupled to the four signal pads and comprise: a four-signal terminal circuit coupled to the four signal pads; a first differential amplifier coupled to a first signal pad and a second signal pad for receiving signals on the first signal pad and the second signal pad and outputting a first differential signal; a second differential amplifier, coupled to the first signal pad and a third signal pad, for receiving signals on the first signal pad and the third signal pad, and outputting a second differential signal accordingly; a third differential amplifier, coupled to the two switches, selectively coupled to the second signal pad and the third signal pad or the third signal pad and a fourth signal pad, for receiving signals on the second signal pad and the third signal pad or signals on the third signal pad and the fourth signal pad, and accordingly outputting a third differential signal; a first signal processing block, coupled to the first differential amplifier, for processing the first differential signal when the four-signal PMA operates in a first physical layer mode; a second signal processing block, coupled to the first, second and third differential amplifiers, for processing the first, second and third differential signals when the four-signal PMA operates in a second physical layer mode; and a third signal processing block, coupled to the third differential amplifier, for processing the third differential signal when the four-signal PMA operates in the first physical layer mode.

An embodiment of the present invention provides a physical layer circuit, including: six signal pads and a six signal physical media additional sublayer. The six signal physical medium additional sublayers are coupled to the six signal pads and comprise: a six-signal terminal circuit coupled to the six signal pads; a first differential amplifier coupled to a first signal pad and a second signal pad for receiving signals on the first signal pad and the second signal pad and outputting a first differential signal; a second differential amplifier, coupled to the first signal pad and a third signal pad, for receiving signals on the first signal pad and the third signal pad, and outputting a second differential signal accordingly; a third differential amplifier, coupled to the two switches, selectively coupled to the second signal pad and the third signal pad or the third signal pad and a fourth signal pad, for receiving signals on the second signal pad and the third signal pad or signals on the third signal pad and the fourth signal pad, and accordingly outputting a third differential signal; a fourth differential amplifier, coupled to the fourth signal pad and a fifth signal pad, for receiving the signals on the fourth signal pad and the fifth signal pad, and outputting a fourth differential signal accordingly; a fifth differential amplifier, coupled to the fourth signal pad and a sixth signal pad, for receiving the signals on the fourth signal pad and the sixth signal pad, and outputting a fifth differential signal accordingly; a sixth differential amplifier, coupled to the fifth signal pad and the sixth signal pad, for receiving signals on the fifth signal pad and the sixth signal pad, and outputting a sixth differential signal accordingly; a first signal processing block, coupled to the first differential amplifier, for processing the first differential signal when the six-signal PMA operates in a first physical layer mode; a second signal processing block, coupled to the first, second and third differential amplifiers, for processing the first, second and third differential signals when the six-signal PMA operates in a second physical layer mode; a third signal processing block, coupled to the third differential amplifier, for processing the third differential signal when the six-signal PMA operates in the first physical layer mode; a fourth signal processing block, coupled to the fourth, fifth and sixth differential amplifiers, for processing the fourth, fifth and sixth differential signals when the sixth signal PMA operates in the second physical layer mode; and a fifth signal processing block, coupled to the sixth differential amplifier, for processing the sixth differential signal when the sixth signal PMA operates in the first physical layer mode.

An embodiment of the present invention provides a clock and data recovery circuit for a multi-wire interface, the clock and data recovery circuit comprising: a plurality of exclusive-OR (XOR) gates, a plurality of latches, an OR gate, and a duty cycle correction circuit. Each of the plurality of XOR gates is coupled to a conductor in the multi-wire interface and has a normal input and a delay input comprising a delay element, wherein each XOR gate receives the same signal on the conductor from the normal input and the delay input and performs an XOR operation on the received signal and a delayed version of the signal to output an XOR output signal. Each of the plurality of latches is coupled to one of the plurality of XOR gates for latching a predetermined signal according to one of the plurality of XOR output signals to output a latch output signal, wherein the plurality of latches is resettable by a reset control signal. The OR gate is coupled to the latches and is used for performing OR operation on the latch output signals to output a clock signal. The duty cycle correction circuit is coupled to the or gate and used for generating a reset control signal to correct the clock signal according to the clock signal, so that the clock signal has a duty cycle of 50%.

An embodiment of the present invention provides a clock and data recovery circuit for a multi-wire interface, the clock and data recovery circuit comprising: a plurality of XOR gates, a plurality of latches, an OR gate and a delay adjustment unit. Each of the plurality of XOR gates is coupled to a wire of the multi-wire interface and has a common input and a delay input including a delay element, wherein each XOR gate receives the same signal on the wire from the common input and the delay input and performs an XOR operation on the received signal and a delayed version of the signal to output an XOR output signal. Each of the plurality of latches is coupled to one of the plurality of exclusive-or gates, and is configured to latch a predetermined signal according to one of a plurality of exclusive-or output signals to output a latch output signal, wherein the plurality of latches is resettable by a reset control signal. The OR gate is coupled to the latches and is used for performing OR operation on the latch output signals to output a clock signal. The delay adjusting unit is coupled to the OR gate and used for generating the reset control signal according to a plurality of output signals of a plurality of sampling units.

Drawings

Fig. 1 shows a PHY circuit comprising a four-signal PMA supporting a dual lane PHY mode and a three lane PHY mode, in accordance with an embodiment of the present invention.

Fig. 2 illustrates how embodiments of the invention reduce the number of deserializers in a PMA.

Fig. 3 shows an embodiment of a PHY circuit comprising a six signal PMA supporting a dual lane PHY mode and a three lane PHY mode.

FIG. 4 shows how the clock signal is utilized to process the data signals at different stages according to an embodiment of the present invention.

Fig. 5 shows a signal pad layout for a PHY circuit including a four-signal PMA according to an embodiment of the present invention.

Fig. 6 shows a signal pad layout for a PHY circuit including a six-signal PMA according to an embodiment of the present invention.

Fig. 7 and 8 show the layout of signal pads including esd protection and pad shielding.

Fig. 9A-9C are prior art termination circuits suitable for use in a two-lane PHY mode and a three-lane PHY mode.

Fig. 10A-10D show a termination circuit for a four-signal PMA according to an embodiment of the invention.

Fig. 11A-11D show a termination circuit for a six-signal PMA according to an embodiment of the present invention.

Fig. 12 is a CDR circuit for use in a receiver of a three-wire communication link in one embodiment of the invention.

Fig. 13 is a signal timing diagram for a CDR circuit having a duty cycle correction circuit.

FIG. 14 is a detailed circuit diagram of one embodiment of a duty cycle correction circuit.

Fig. 15 and 16 are signal timing diagrams for explaining the operation of the duty cycle correction circuit of fig. 14.

Fig. 17 is a detailed circuit diagram of another embodiment of the duty cycle correction circuit.

Fig. 18 is a signal timing diagram for explaining the operation of the duty correction circuit of fig. 17.

Fig. 19 is a CDR circuit for use in a receiver of a three-wire communication link in accordance with another embodiment of the present invention.

Fig. 20 is a signal timing diagram explaining the operation of the delay correction circuit of fig. 19.

Reference numerals

800. 900, 110, 210, 411, 412 physical media additional sub-layers

600 terminal circuit

811-813, 911-916 differential amplifier

821. 822, 1110, 1112, 921, 923, 925S/H circuits

823. 1111, 922, 924, 1010, 1200 CDR circuit

831. 832, 833, 1120, 931-

840. 1130, 941, 942, 1030 buffer

845. 1035, 943 and 944 symbol decoder

850. 1040, 951, 952 data processing unit

100. 200, 300, 400 physical layer circuit

320. 322, 420, 422 ESD protection circuit

330. 430 physical coding sublayer

500. 600, 700 terminal circuit

1210-

1221-1223, 2021-2023, 2091-2092 XOR gate

1231-1233, 2031-2033 latches

1240. 2040 OR gate

1250. 1500, 1800 duty cycle correction circuit

1260. 2060 alignment delay unit

1281-1282-2081-2082 sampling unit

1271-1272 and 2071-2072 frequency eliminator

1511-

1520 TDC

1530. 1820 digital control logic

1540. 1830 NAND gate

1550. 1840 programmable delay line

1810 comparator

2000 delay adjusting unit

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention to the reader. However, those skilled in the art will understand how to implement the invention without one or more of the specific details, or with other methods or elements or materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. Thus, the appearances of the phrase "in one embodiment" appearing in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics described above may be combined in any suitable manner in one or more embodiments.

The present invention generally provides a four-signal (four-signal) physical media attachment sublayer (PMA) and/or a six-signal (six-signal) PMA in a physical layer circuit (PHY) of a receiver for communicative interfacing with a PHY specification conforming to the MIPI C-PHY specification or other type that uses three signal lines to form lanes (hereinafter referred to as a three-wire lane (PHY)) and with a PHY specification conforming to the MIPI C-PHY specification or other type that uses two signal lines to form lanes (hereinafter referred to as a two-wire lane (PHY)) of the receiver. In an embodiment of the present invention, the four-signal PMA and the six-signal PMA may be implemented in the form of an Intellectual Property (IP) core, an IP block or a functional block to improve design productivity and to facilitate management of highly complex integrated circuit development.

Both the four-signal PMA and the six-signal PMA of the present invention may be configured to operate in one of a MIPI D-PHY mode (or other type of two-wire PHY mode) and a MIPI C-PHY mode (or other type of three-wire PHY mode). For each of them, a four-signal PMA may provide two "two-wire" channels or one "three-wire" channel for one communication link, while a six-signal PMA may provide three "two-wire" channels or two "three-wire" channels for one communication link.

Due to the signal characteristics of these different PHY modes, different signal processing procedures/hardware resources are required to process signals that conform to different PHY specifications. The present invention provides pad arrangements, termination circuits, desequence structures and clock and data recovery circuits for four-signal and six-signal PMA as described below.

Inventive ensemble

Please refer to fig. 1, which is a diagram illustrating a portion of a PHY circuit according to an embodiment of the present invention. As shown, the PHY circuit includes a four-signal PMA 800 and four signal pads D0P _ T0A, D0N _ T0B, D1P _ T0C, and D1N, and a four-signal termination circuit 600. The signal pads D0P _ T0A, D0N _ T0B, D1P _ T0C and D1N are respectively coupled to the differential amplifier 811-813 in the four-signal PMA 800. The four-signal termination circuit 600 is also coupled to the signal pads D0P _ T0A, D0N _ T0B, D1P _ T0C, and D1N, respectively. Thus, the differential amplifiers 811-813 are coupled to the terminal circuits 600, respectively.

Typically, the four signal PMA 800 in this embodiment supports a two-wire-lane PHY mode (e.g., MIPI D-PHY) and a three-wire-lane PHY mode (e.g., MIPI C-PHY). When the four-signal PMA 800 is configured as a MIPI D-PHY mode and operates in a communication link for a MIPI D-PHY mode, it can support 2 two-wire channels, with signal pads D0P _ T0A and D0N _ T0B connected to the first two-wire channel and signal pads D1P _ T0C and D1N connected to the second two-wire channel. Alternatively, when the four-signal PMA 800 is set to MIPI C-PHY mode and is operating on a communication link for MIPI C-PHY in MIPI C-PHY mode, the signal pads D0P _ T0A, D0N _ T0B and D1P _ T0C are connected to a three-wire channel.

In the case of MIPI D-PHY mode/signal wiring, signal pads D0P _ T0A and D0N _ T0B are coupled to differential amplifier 811, and differential amplifier 811 outputs differential signal D0 based on the difference between the signals on signal pads D0P _ T0A and D0N _ T0B. The signal pads D1P _ T0C and D1N are coupled to the differential amplifier 813 through switches, and the differential amplifier 813 outputs a differential signal D1 based on the difference between the signals on the signal pads D1P _ T0C and D1N. In addition, a first signal processing block is coupled to the differential amplifier 811. Also, the first signal processing block is used to process the differential signal D0 when the four-signal PMA 800 operates in MIPI D-PHY mode. A third signal processing block is coupled to the differential amplifier 811. Also, the third signal processing block is used to process the differential signal D1 when the four-signal PMA 800 operates in MIPI D-PHY mode.

In one embodiment, the first signal processing block comprises a sample and hold (S/H) circuit 821. The S/H circuit 821 generates sequence data signals D0[ 1:0] and a clock signal D0_ CK. The third signal processing block includes at least an S/H circuit 823, and the S/H circuit 823 generates sequence data signals D1[1:0] and a clock signal D1_ CK.

In one embodiment, the first signal processing block may also include a 2-to-8 deserializer 831 coupled to the S/H circuit 821. The S/H circuit 821 outputs a data signal D0[ 1:0] and a clock signal D0_ CK to the 2-8 deserializer 831. The 2-to-8 deserializer 831 deserializes them to produce a plurality of parallel data signals D0[ 7: 0] and a clock signal D0_ BCK. The third signal processing block may also include a 2-to-8 deserializer 833 coupled to the S/H circuit 823. The S/H circuit 823 converts the data signal D1[1:0] and the clock signal D1_ CK to the 2-to-8 deserializer 833. The 2-to-8 deserializer 833 performs deserializing operations on them to produce a plurality of parallel data signals D1[ 7: 0] and a clock signal D1_ BCK.

In the case of MIPI C-PHY mode/signal connections, signal pads D0P _ T0A, D0N _ T0B, and D1P _ T0C are coupled to differential amplifiers 811-813. The differential amplifier 811 outputs a differential signal T0AB based on the difference between the signals on the signal pads D0P _ T0A and D0N _ T0B. The differential amplifier 812 outputs a differential signal T0CA based on the difference between the signals on the signal pads D1P _ T0C and D0P _ T0A. The differential amplifier 813 outputs a differential signal T0BC based on the difference between the signals on the signal pads D0P _ T0B and D1P _ T0C. The differential amplifiers 811-813 are coupled to a second signal processing block. The second signal processing block is used to process the differential signals T0AB, T0BC, and T0CA when the four-signal PMA 800 operates in MIPI C-PHY mode.

In one embodiment, the second signal processing block includes a C-PHY Clock and Data Recovery (CDR) circuit 822, and the C-PHY CDR circuit 822 generates a set of sequential data signals T0AB [1: 0), T0BC [1:0] and T0CA [1:0] and the corresponding clock signal T0_ CK.

In one embodiment, the second signal processing block includes at least a 2-to-8 deserializer 832 coupled to the C-PHY CDR circuit 822. C-PHY CDR circuit 822 outputs signal T0AB [1: 0), T0BC [1:0] and T0CA [1:0] and T0_ CK to the 2-8 deserializer 832. The 2-8 deserializer 832 generates a clock signal T0CK to clock the signal T0AB [1: 0), T0BC [1:0] and T0CA [1:0] to produce a set of parallel data signals T0AB [ 7: 0), T0BC [ 7: 0), T0CA [ 7: 0] and the corresponding clock signal T0_ BCK.

The 2-to-8 deserializer 832 is further coupled to an 8-to-7 first-in, first-out buffer (FIFO) 840, and the 8-to-7 FIFO 840 converts the 8-bit data signal T0AB [ 7: 0), T0BC [ 7: 0] and T0CA [ 7: 0] to 7 bits long. The 8-to-7 FIFO 840 is coupled to a 7 symbol decoding unit (7-symbol decoding unit) 845. The 7 symbol decoding unit 845 is used for decoding the data signal read from the 8-to-7 FIFO 840, thereby generating data symbols. The 7 symbol decoding unit 845 is coupled to the data processing unit 850. The data processing unit 850 is used for processing the data symbols output by the 7 symbol decoding unit 845. The data processing unit 850 may include a 7-symbol to 16-bit demapper (demapper) for demapping each 7 symbols received from the 7-symbol decoding unit 845 into a 16-bit data word.

Further, the 8 to 7FIFO 840, the 7 symbol decoding unit 845, and the data processing unit 850 collectively function as a C-PHY decoding processor 860 in the four-signal PMA 800. Further, the order of the 8 to 7 FIFOs and the 7 symbol decoding units in the four-signal PMA 800 is interchangeable. According to various embodiments of the present invention, the symbol decoding unit may be disposed before the FIFO (refer to applicant's U.S. patent application No. 15/956,709, which discloses the architecture of the symbol decoding unit before the FIFO).

Since the four-signal PMA 800 may not operate in the MIPI D-PHY mode and the MIPI C-PHY mode simultaneously, the number of 2 to 8 deserializers configured in the four-signal PMA 800 may be reduced. Please refer to fig. 2 for further understanding. When operating in MIPI D-PHY mode, S/

H circuits

1110 and 1112 may share the same 2-to-8 deserializer 1120, and the 2-to-8 deserializer 1120 performs a data conversion on a data signal D0[ 1:0] and D1[1:0] were deserialized. On the other hand, when operating in MIPI C-PHY mode, the C-PHY CDR circuit 1111 only needs one 2-to-8 deserializer 1120, and the 2-to-8 deserializer 1120 performs a deserialization of the data signal T0AB [1: 0), T0BC [1:0] and T0CA [1:0] deserializing. This implementation significantly improves the circuit area utilization efficiency compared to the three separate deserializers 831-833 required for the four-signal PMA 800 of fig. 1.

Figure 3 is another embodiment of the present invention that supports both MIPI D-PHY communication links and MIPI C-PHY communication links. As shown, the PHY circuit in fig. 3 includes a six-signal PMA 900, signals D0P _ T0A, D0N _ T0B, D1P _ T0C, D1N _ T1A, D2P _ T1B, and D2N _ T1C, and a six-signal termination circuit 700. The signal pads D0P _ T0A, D0N _ T0B, D1P _ T0C, D1N _ T1A, D2P _ T1B and D2N _ T1C are respectively coupled to the differential amplifier 911-916 of the 6-signal PMA 900. The six signal termination circuits 700 are also coupled to the signal pads D0P _ T0A, D0N _ T0B, D1P _ T0C, D1N _ T1A, D2P _ T1B, and D2N _ T1C, respectively. Thus, the differential amplifiers 911-916 are coupled to the six-signal termination circuit 700, respectively.

When six signal PMA 900 is set to MIPI D-PHY mode and is operating in MIPI D-PHY based communication links in MIPI D-PHY mode, signal pads D0P _ T0A and D0N _ T0B are connected to a first two-wire lane in MIPI D-PHY communication links, signal pads D1P _ T0C and D1N _ T1A are connected to a second two-wire lane in MIPI D-PHY communication links, and pads D2P _ T1C and D2N _ T1C are connected to a third two-wire lane in MIPI D-PHY communication links. Alternatively, when six signal PMA 900 is set to MIPI C-PHY mode and is operating in MIPI C-PHY based communication link in MIPI C-PHY mode, signal pads D0P _ T0A, D0N _ T0B and D1P _ T0C are connected to the first three-wire channel in MIPI C-PHY communication link and signal pads D1N _ T1A, D2P _ T1B and D2N _ T1C are connected to the second three-wire channel in MIPI C-PHY communication link.

In the case of MIPI D-PHY mode/communication links, signal pads D0P _ T0A and D0N _ T0B are coupled to differential amplifier 911, and differential amplifier 911 outputs differential signal D0 based on the difference between the signals on signal pads D0P _ T0A and D0N _ T0B. The signal pads D1P _ T0C and D1N _ T1A are coupled to the differential amplifier 913 through switches, and the differential amplifier 913 outputs a differential signal D1 based on the difference between the signals on the signal pads D1P _ T0C and D1N _ T1A. The signal pads D2P _ T1B and D2N _ T1C are coupled to the differential amplifier 916 through switches, and the differential amplifier 916 outputs a differential signal D2 based on the difference between the signals on the signal pads D2P _ T1B and D2N _ T1C. Further, the first signal processing block is coupled to the differential amplifier 911 and is used to process the differential signal D0 when the six-signal PMA 900 operates in the MIPI D-PHY mode. The third signal processing block is coupled to the differential amplifier 913 and is used to process the differential signal D1 when the six-signal PMA 900 operates in the MIPI D-PHY mode. The fifth signal processing block is coupled to the differential amplifier 916 and is used to process the differential signal D2 when the six-signal PMA 900 operates in the MIPI D-PHY mode.

In one embodiment, the first signal processing block includes at least an S/H circuit 921. The S/H circuit 921 generates the sequence data signal D0[ 1:0] and a clock signal D0_ CK. The third signal processing block includes at least an S/H circuit 923, and the S/H circuit 923 generates a sequence data signal D1[1:0] and a clock signal D1_ CK. The fifth signal processing block includes at least an S/H circuit 925, the S/H circuit 925 generating a sequence data signal D2[ 1:0] and a clock signal D2_ CK.

In one embodiment, the first signal processing block may further include a 2-to-8 deserializer 931 coupled to the S/H circuit 921. The S/H circuit 921 outputs a data signal D0[ 1:0] and a clock signal D0_ CK to the 2-to-8 deserializer 931. The 2-to-8 deserializer 931 performs a deserializing operation on the signals to generate a plurality of parallel data signals D0[ 7: 0] and a clock signal D0_ BCK. The third signal processing block may further include a 2-to-8 deserializer 933 coupled to the S/H circuit 923. The S/H circuit 923 outputs a data signal D1[1:0] and clock signal D1_ CK to 2-8 deserializer 933. The 2-to-8 deserializer 933 deserializes the signals to produce a plurality of parallel data signals D1[ 7: 0] and a clock signal D1_ BCK. The fifth signal processing block may also include a 2-to-8 deserializer 935 coupled to the S/H circuit 925. The S/H circuit 925 outputs a data signal D2[ 1:0] and a clock signal D2_ CK to the 2-to-8 deserializer 935. The 2-to-8 deserializer 935 deserializes the signals to produce a plurality of parallel data signals D2[ 7: 0] and a clock signal D2_ BCK.

In the case of MIPI C-PHY mode/communication links, signal pads D0P _ T0A and D0N _ T0B are coupled to differential amplifier 911, and differential amplifier 911 outputs differential signal T0AB based on the difference between the signals on signal pads D0P _ T0A and D0N _ T0B. The signal pads D0P _ T0A and D1P _ T0C are coupled to the differential amplifier 912, and the differential amplifier 912 outputs a differential signal T0CA based on the difference between the signals on the signal pads D0P _ T0A and D1P _ T0C. The signal pads D1P _ T0C and D0N _ T0B are coupled to the differential amplifier 913 through switches, and the differential amplifier 913 outputs a differential signal T0BC based on the difference between the signals on the signal pads D1P _ T0C and D0N _ T0B. The signal pads D1N _ T1A and D2P _ T1B are coupled to the differential amplifier 914, and the differential amplifier 914 outputs a differential signal T1AB based on the difference between the signals on the signal pads D1N _ T1A and D2P _ T1B. The signal pads D1N _ T1A and D2N _ T1C are coupled to the differential amplifier 915, and the differential amplifier 915 outputs a differential signal T1CA based on the difference between the signals on the signal pads D1N _ T1A and D2N _ T1C. The signal pads D2P _ T1B and D2N _ T1C are coupled to the differential amplifier 916 through switches, and the differential amplifier 916 outputs the differential signal T1BC based on the difference between the signals on the signal pads D2P _ T1B and D2N _ T1C.

The differential amplifiers 911-913 are also coupled to a second signal processing block. When the six-signal PMA 900 is set to the MIPI C-PHY mode, the second signal processing block is used to process the differential signals T0AB, T0BC and T0 CA. The

differential amplifiers

914 and 916 are further coupled to a fourth signal processing block. When the six signal PMA 900 is set to MIPI C-PHY mode, the fourth signal processing block is used to process the differential signals T1AB, T1BC and T1 CA.

In one embodiment, the second signal processing block includes at least a C-PHY CDR circuit 922, and the C-PHY CDR circuit 922 generates a set of sequence data signals T0AB [1: 0), T0BC [1:0] and T0CA [1:0] and the corresponding clock signal T0_ CK. The fourth signal processing block includes at least the C-PHY CDR circuit 924 and, based on the signals T1AB, T1BC, and T1CA, generates a set of sequence data signals T1AB [1: 0), T1BC [1:0] and T1CA [1:0] and the corresponding clock signal T1_ CK.

In one embodiment, the second signal processing block may also include a 2-to-8 deserializer 932 coupled to the C-PHY CDR circuit 922. The C-PHY CDR circuit 922 outputs a signal T0AB [1: 0), T0BC [1: 0), T0CA [1:0] and T0_ CK to a2 to 8 deserializer 932. The 2-to-8 deserializer 932 generates a clock signal T0CK to the signal T0AB [1: 0), T0BC [1:0] and T0CA [1:0] to produce a set of parallel data signals T0AB [ 7: 0), T0BC [ 7: 0), T0CA [ 7: 0] and the corresponding clock signal T0_ BCK. The fourth signal processing block may also include a 2-to-8 deserializer 934, which is coupled to the C-PHY CDR circuit 924. The C-PHY CDR circuit 924 outputs a signal T1AB [1: 0), T1BC [1: 0), T1CA [1:0] and T1_ CK to 2-8 deserializer 934. The 2-to-8 deserializer 934 deserializes the signal T1AB [1: 0), T1BC [1:0] and T1CA [1:0] to produce a set of parallel data signals T1AB [ 7: 0), T1BC [ 7: 0), T1CA [ 7: 0] and the corresponding clock signal T1_ BCK.

In one embodiment, the 2-to-8 deserializer 932 is further coupled to an 8-to-7 FIFO 941, and the 8-to-7 FIFO 941 converts the 8-bit data signal T0AB [ 7: 0), T0BC [ 7: 0), T0CA [ 7: 0] to 7 bits long. The 8-7 FIFO 941 is coupled to the 7 symbol decode unit 943. The 7 symbol decoding unit 943 is used for decoding the data signals read from the 8-to-7 FIFO 941, thereby generating data symbols. The 7 symbol decoding unit 943 is coupled to the data processing unit 951. The data processing unit 951 is used for processing data symbols output by the 7 symbol decoding unit 943. The data processing unit 951 may include a 7 symbol to 16 bit demapper for demapping each 7 symbols received from the 7 symbol decoding unit 943 into a 16 bit data word. Further, the 8 to 7FIFO 941, the 7 symbol decoding unit 943, and the data processing unit 951 function together as a C-PHY decoding processor 960 in the six-signal PMA 900. In addition, the order of the FIFO and the symbol decoding unit in the six-signal PMA of the present invention is interchangeable. According to various embodiments of the present invention, the symbol decoding unit may also be disposed before the FIFO (refer to the applicant's U.S. patent application No. 15/956,709, which discloses the structure of the symbol decoding unit before the FIFO).

The 2-to-8 deserializer 934 is further coupled to an 8-to-7 FIFO 942. The 8-to-7 FIFO 942 stores 8-bit data signals T1AB [ 7: 0), T1BC [ 7: 0] and T1CA [ 7: 0] to 7 bits long. The 8-to-7 FIFO 942 is coupled to a 7 symbol decode unit 944. The 7 symbol decoder 944 is configured to decode the data signal read from the 8-to-7 FIFO 942, thereby generating data symbols. The 7 symbol decoding unit 944 is coupled to the data processing unit 952. The data processing unit 952 is configured to process the data symbols outputted by the 7 symbol decoding unit 944. The data processing unit 952 may include a 7 symbol to 16 bit demapper for demapping each 7 symbols received from the 7 symbol decoding unit 944 into a 16 bit data word group. Further, the 8 to 7FIFO 942, the 7 symbol decoding unit 944, and the data processing unit 952 collectively function as another C-PHY decoding processor 970 in the six-signal PMA 900.

As described above, for circuit area utilization efficiency, the 2-to-8 de-sequencers 931-933 may be combined as well as the 2-to-8 de-sequencers 934 and 935 as in the embodiment shown in FIG. 2.

FIG. 4 shows how the clock signal is used to process the data signals at different stages. As shown, the 2-to-8 deserializer 1020 generates a clock signal TCK on the data signal AB [1: 0), BC [1:0] and CA [1:0] performing a desequence operation, wherein the frequency of the clock signal TCK is half of the symbol rate (symbol rate) of the communication line. The 8-to-7 FIFO 1030 outputs an 8-bit data signal AB [ 7: 0), BC [ 7: 0] and CA [ 7: 0] into a 7-bit data word, wherein the frequency of the clock signal BCK is 1/8 of the symbol rate. The 7 symbol decoding unit 1035 is used for decoding the data signals read from the 8-to-7 FIFO 1030 to generate symbols according to the clock signal SCK. The data processing unit 1040 is coupled to the 7-symbol decoding unit 1035, and is used to process the symbols output from the 7-symbol decoding unit 1035. The data processing unit 1040 may comprise a 7 symbol to 16 bit demapper arranged to demap each 7 symbol received from the 7 symbol decoding unit 1035 into a 16 bit data word according to a clock signal SCK, wherein the frequency of the clock signal SCK is 1/7 of the symbol rate.

It is noted that the data width of any particular number of bits mentioned in the embodiments of fig. 1 and 3 is intended to be illustrative rather than limiting. Those skilled in the art will understand how to select different numbers of data width bits to arrange the various elements therein according to different applications and design requirements, such as the deserializer, the FIFO, and the symbol decoding unit in the four-signal and six-signal PMA.

Pad arrangement mode

Signals transmitted from the PHY circuits in fig. 1 and 3 may be subject to interference, such as cross-talk (cross-talk) between signal transmission lines. Therefore, in various designs, shielding (shielding) techniques are often applied to mitigate interference. To solve these problems, the present invention provides an innovative pad arrangement (pad arrangement) to more reasonably and effectively use and distribute the pads, thereby shielding the interference.

Fig. 5 shows a pad arrangement according to an embodiment of the invention, which may be used for a PHY circuit comprising a four-signal PMA. As shown, the PHY circuit 100 includes a four-signal PMA 110, and signal pads D0P _ T0A, D0N _ T0B, CKP _ T0C, and CKN _ XXX for connection with other integrated circuits/devices, which are coupled to the four-signal PMA 110 by any possible type of conductor. The shielding pad (shielding pad) SH is coupled to ground or a power voltage and is used for shielding the signal pads D0P _ T0A and D0N _ T0B from interfering with the signal pads CKP _ T0C and CKN _ XXX.

The four signal PMA 110 may be configured as a two wire lane PHY mode (e.g., MIPI D-PHY) or a three wire lane PHY mode (e.g., MIPI C-PHY). In the two-wire PHY mode, the signal pads D0P _ T0A and D0N _ T0B may form a data channel, and the signal pads CKP _ T0C and CKN _ XXX may be used as clock channels. The PMA 110 sends/receives a pair of data signals through the pads D0P _ T0A and D0N _ T0B and a pair of clock signals through the pads CKP _ T0C and CKN _ XXX. In the three-channel mode, three signal pads form one channel. For example, the signal pads D0P _ T0A, D0N _ T0B and CKP _ T0C form a channel, and the signal pads CKN _ XXX may not be used.

Please note that, in various embodiments of the present invention, the pad layout shown in fig. 5 can be further applied to a PHY circuit including N signal pads and M shield pads, where N and M are positive integers. In such an embodiment, the N signal pads include at least four signal pads, and the M shielding pads include at least one shielding pad. The at least four signal pads and the at least one shielding pad may be arranged in a pad arrangement similar to that shown in fig. 5.

Fig. 6 shows a pad arrangement for a PHY circuit including a six-signal PMA according to an embodiment of the present invention. As shown, the PHY circuit 200 includes a six-signal PMA210 and signal pads D0P _ T0A, D0N _ T0B, CKP _ T0C, CKN _ T1A, D1P _ T1B, and D1N _ T1C for connection to another integrated circuit/device. The shielding pads SH0, SH1, and SH2 are coupled to ground or a power voltage and serve to protect some signal pads from interference by other signal pads.

The six signal PMA210 may be set to a two-wire lane PHY mode or a three-wire lane PHY mode. In the two-wire channel PHY mode, signal pads D0P _ T0A and D0N _ T0B and D1P _ T1B and D1N _ T1C form data channels, while signal pads CKP _ T0C and CKN _ XXX form clock channels. The six signal PMA210 transmits/receives a data signal pair through the signal pads D0P _ T0A and D0N _ T0B and D1P _ T1B and D1N _ T1C, and transmits/receives a clock signal pair through the signal pads CKP _ T0C and CKN _ T1A. In the three-lane PHY mode, three pads form one lane. For example, the signal pads D0P _ T0A, D0N _ T0B and CKP _ T0C form a three-wire channel, and the signal pads CKN _ T1A, D1P _ T0B and D1N _ T1C form another three-wire channel.

It is noted that in various embodiments of the present invention, the pad layout shown in fig. 6 can be further applied to a PHY circuit including N signal pads and M shield pads, where N and M are positive integers. In such an embodiment, the N signal pads include at least six signal pads, and the M shielding pads include at least three shielding pads. The at least six signal pads and the at least three shielding pads may be arranged in a pad arrangement similar to that shown in fig. 6.

Referring to fig. 7 and 8, pad arrangements for Electrostatic Discharge (ESD) protection and pad shielding are shown. Fig. 7 shows a pad arrangement according to an embodiment of the invention, which may be used for a PHY circuit comprising a six-signal PMA. As shown, the PHY circuit 300 includes a six-signal PMA210, a Physical encoding sublayer (PCS) 330,

ESD protection circuits

320 and 322, and signal pads D0P _ T0A, D0N _ T0B, CKP _ T0C, CKN _ T1A, D1P _ T1B, and D1N _ T1C for connection to another integrated circuit/device. The shielding pads SH0 and SH4 are used to couple the

ESD protection circuits

320 and 322 to ground to provide electromagnetic shielding. In addition, the shielding pads SH1, SH2, and SH3 are coupled to ground or power voltage and are used for shielding some signal pads from interference of other signal pads.

Fig. 8 is a pad arrangement according to an embodiment of the invention, which may be used for a PHY circuit comprising a combination of a six-signal PMA and a four-signal PMA. As shown, the PHY circuit 400 includes a six-signal PMA 411, a four-signal PMA 412, a PCS 430,

ESD protection circuits

420 and 422. The six-signal PMA 411 is connected to another integrated circuit/device through signal pads D0P _ T0A, D0N _ T0B, CKP _ T0C, CKN _ T1A, D1P _ T1B, and D1N _ T1C. The four signal PMA 412 is connected to another integrated circuit/device through the signal pads D0P _ T0A, D0N _ T0B, CKP _ T0C and CKN _ XXX. The shielding pads SH0 and SH6 are used to couple the

ESD protection circuits

420 and 422 to ground to provide electromagnetic shielding. In addition, the shielding pads SH1, SH2, SH3, SH4, and SH5 are coupled to ground or power voltage and are used to shield some signal pads from interference from other signal pads.

Terminal circuit

As described above, both the four-signal PMA and the six-signal PMA of the present invention may be arranged to operate in a two-wire lane PHY mode or a three-wire lane PHY mode. Therefore, it is desirable to provide a termination circuit (termination circuit) suitable for signal characteristics of different PHY modes.

Fig. 9A shows a prior art termination circuit suitable for use in a two-lane PHY mode and a three-lane PHY mode. By controlling the switches in termination circuit 500 of fig. 9A. As shown in fig. 9A, termination circuit 500 may be switched to a first configuration to accommodate the two-wire path shown in fig. 9B. Alternatively, switching to the second configuration to accommodate the three-wire channel shown in fig. 9C. In the MIPI standard, an equivalent decoupling capacitance (decoupling capacitor) in a three-wire channel is required to be larger than that in a two-wire channel. Thus, the capacitance value of each decoupling capacitive element C1, C2, and C3 will be 1X (where "X" represents a unit capacitance value). However, such an implementation would result in capacitive redundancy (i.e., capacitive element C2) in a three-wire channel configuration as shown in fig. 9C. To overcome the capacitive redundancy of the termination circuit 500 in a three-wire channel configuration, the present invention provides an innovative architecture for improving the termination circuit.

Fig. 10A shows a four-signal termination circuit 600 of an embodiment of the invention, which may be used for a PHY circuit comprising a four-signal PMA. The termination circuit 600 includes adjustable resistive elements R1-R4, switches S61-S62, and decoupling capacitive elements C1-C3 (each capacitive element C1-C2 has a capacitance of 0.5X, while capacitive element C3 has a capacitance of 1X). In this embodiment, each of the adjustable resistive elements R1-R4 may be coupled to a signal pad of a PHY circuit including a four-signal PMA (e.g., four-signal PMA 800). Please note that, according to various embodiments of the present invention, the adjustable resistive elements R1-R4 can be replaced by other types of resistive elements (electrical impedance).

Please refer to fig. 1 and fig. 10A simultaneously. When the four-signal PMA 800 is configured to operate in the two-wire PHY mode, each two signal pads will form one channel, and one pair of differential signals may be transmitted/received through the signal pads D0P _ T0A and D0N _ T0B, respectively, while another pair of clock signals may be transmitted/received through the signal pads D1P _ T0C and D1N, respectively. At this time, switch S62 is conductive and switch S61 is non-conductive (as shown in FIG. 10B). Therefore, the equivalent decoupling capacitance value obtained at the signal pads D0P _ T0A and D0N _ T0B is (0.5+0.5) X, and the decoupling capacitance value of 1X is obtained at the pads D1P _ T0C and D1N. Further, when the four-signal PMA 800 sets operation in the three-lane PHY mode, switch S61 is conductive and switch S62 is non-conductive (shown in fig. 10C). Therefore, equivalent decoupling capacitance values of (0.5+0.5+1) X are obtained at the signal pads D0P _ T0A, D0N _ T0B and D1P _ T0C. Furthermore, as shown in fig. 10D, in another embodiment, the decoupling capacitive elements C1 and C2 may be combined into one larger decoupling capacitive element CN with a capacitance value of (0.5+ 0.5).

Fig. 11A shows a six-signal termination circuit 700 of an embodiment of the invention, which may be used for a PHY circuit comprising a six-signal PMA. The six-signal termination circuit 700 includes adjustable resistive elements R1-R6, switches S61-S63, and decoupling capacitive elements C1-C6 (each capacitive element has a capacitance value of 0.5X). In this embodiment, each of the adjustable resistive elements R1-R6 may be coupled to a signal pad of a PHY circuit including a six-signal PMA (e.g., six-signal PMA 900). Please note that, according to various embodiments of the present invention, the adjustable resistive elements R1-R6 can be replaced by other types of resistive elements.

Please refer to fig. 3 and fig. 11A simultaneously. When six signal PMA 900 is set to operate in two-lane PHY mode, a pair of data signals may be transmitted/received on signal pads D0P _ T0A and D0N _ T0B, a pair of data signals may be transmitted/received on signal pads D1P _ T0C and D1N _ T1A, and a pair of clock signals may be transmitted/received on signal pads D2P _ T1B and D2N _ T1C. Additionally, when the six-signal PMA 900 is set to operate in the three-lane PHY mode, the six-signal PMA 900 may provide two three-lanes. For example, one set of three-wire signals is sent on signal pads D0P _ T0A, D0N _ T0B, and signal pad D1P _ T0A, respectively, and another set of three-wire signals is sent on signal pads D1N _ T1A, D2P _ T1B, and D2P _ T1C.

When the six signal PMA 900 is set to operate in the two-wire lane PHY mode, the switch S62 is turned on and the switches S61 and S63 are not turned on (as shown in fig. 11B). Therefore, decoupling capacitors with capacitance values equivalent to (0.5+0.5) X are formed at the signal pads D0P _ T0A and D0N _ T0B, the signal pads D1P _ T0C and D1N _ T1A, and the signal pads D2P _ T1B and D2N _ T1C, respectively. Further, when the six signal PMA 900 is set to operate in the three-wire channel PHY mode, the switches S61 and 63 are conductive and the switch S62 is non-conductive (as shown in fig. 11C). Therefore, decoupling capacitors with capacitance values equivalent to (0.5+0.5+0.5) X are formed at the signal pads D0P _ T0A, D0N _ T0B and D1P _ T0C and the signal pads D1N _ T1A, D2P _ T1B and D2N _ T1C, respectively. Furthermore, as shown in fig. 11D, in one possible embodiment, decoupling capacitive elements C1 and C2 may be implemented with a larger decoupling capacitive element CN1 having a (0.5+0.5) X capacitance value. In addition, in one possible embodiment, decoupling capacitive elements C5 and C6 may also be implemented with a larger decoupling capacitive element CN2 having a (0.5+0.5) X capacitance value.

In contrast to termination circuit 500, there is no capacitive redundancy in the four signal termination circuit 600 and the six signal termination circuit 700 when switched to the three-wire channel configuration. Also, another advantage of the

termination circuits

600 and 700 of the present invention is the number of switches. Since fewer switches are required for the

termination circuits

600 and 700 as compared to the termination circuit 500, signal loss can be reduced.

Clock and data recovery

In the MIPI C-PHY specification, a clock signal is embedded in a data signal. Therefore, the PHY circuitry in the receiver needs to recover the clock signal from the received data signal.

Fig. 12 shows CDR circuitry in a receiver suitable for use in a MIPI C-PHY (or other three-wire PHY standard) communication link, according to one embodiment of the present invention. As shown, CDR circuit 1200 has three input terminals for receiving signals AB, BC, and CA generated by the differential amplifiers. The differential amplifier can be the differential amplifier 811-813 shown in the embodiment of FIG. 1, or the differential amplifier 911-916 shown in the embodiment of FIG. 3, which receives the differential signals on three signal pads/wires, i.e., the signal pads D0P _ T0A, D0N _ T0B, D1P _ T0C, and converts them into the differential signals AB, BC, CA (i.e., T0AB [1:0], T0BC [1:0] and T0CA [1:0] in FIG. 1 or FIG. 3).

The three signals AB, BC and CA are input to delay

units

1210, 1211 and 1212, thereby generating delayed versions AB _ D, BC _ D and CA _ D of the signals AB, BC and CA. Thereafter, exclusive OR (XOR)

gates

1221, 1222, and 1223 perform XOR operations on the signals AB and AB _ D, BC and BC _ D, and CA _ D, respectively. Accordingly,

XOR gates

1221, 1222, and 1223 generate XOR output signals AB _ X, BC _ X and CA _ X. Due to the XOR-operation, signal transitions in the signals AB, BC and CA will result in pulses (pulses) in the XOR-output signals AB _ X, BC _ X and CA _ X. The XOR output signals AB _ X, BC _ X and CA _ X are then provided to

latches

1231,1232, and 1233, which clock latches 1231,1232 and 1233 to latch a high logic level signal. In addition, the

latches

1231,1232, and 1233 may be reset by the reset control signal RSTB. Accordingly, rising EDGEs of the latch output signals AB _ EDGE, BC _ EDGE, and CA _ EDGE are triggered by the XOR output signals AB _ X, BC _ X, and CA _ X, respectively, and falling EDGEs of the latch output signals AB _ EDGE, BC _ EDGE, and CA _ EDGE are triggered by the reset control signal RSTB, respectively.

Then, the latch output signals AB _ EDGE, BC _ EDGE, and CA _ EDGE are sent to an OR gate (OR gate)1240, which performs an OR operation on the latch output signals AB _ EDGE, BC _ EDGE, and CA _ EDGE, thereby generating a clock signal RCK. The clock signal RCK may be processed by

frequency dividers

1271 and 1272 having different divisors (i.e., 2 and 7) to generate clock signals for different purposes. The clock signal TCK generated by the frequency divider 1271 is supplied to the

sampling units

1281 and 1282 for sampling the signals AB _ S, BC _ S and CA _ S to perform a deserializing operation (wherein the signals AB _ S, BC _ S and CA _ S may be output by delaying the delayed signals AB _ D, BC _ D and CA _ D by an aligned delay unit 1260). In addition, the clock signal SCK generated by the frequency divider 1272 is provided to circuits such as the data processing units 850 (fig. 1), 951-.

On the other hand, the generated clock signal RCK is further sent to a duty cycle correction circuit 1250, thereby generating a reset control signal RSTB. The duty cycle calibration circuit 1250 is used to calibrate the clock signal RCK to achieve a duty cycle of 50% (or about 50%) for the clock signal RCK. The duty cycle correction circuit 1250 corrects the clock signal RCK by generating the reset control signal RSTB to realize a 50% duty cycle.

As described above, the clock signal RCK is generated by performing an OR operation on the latch output signals AB _ EDGE, BC _ EDGE, and CA _ EDGE. Thus, adjusting the duty cycle of the latch output signals AB _ EDGE, BC _ EDGE, and CA _ EDGE (by resetting these signals) can substantially change the duty cycle of the clock signal RCK.

The timing diagram of the duty cycle correction circuit 1250 processing the clock signal RCK is shown in fig. 13. The pulses of signals AB _ X, BC _ X and CA _ X are indicated in dashed lines to reflect this when the pulses of signals AB _ X, BC _ X and CA _ X follow the signal transitions of signals AB, BC, and CA. The pulses of signals AB _ X, BC _ X and CA _ X will trigger

latches

1231,1232, and 1233 to toggle the latch output signals AB _ EDGE, BC _ EDGE, and CA _ EDGE to a high logic level. Also, when the reset control signal RSTB is pulled up (asserted), the

latches

1231,1232, and 1233 are reset, which causes the latch output signals AB _ EDGE, BC _ EDGE, and CA _ EDGE to transition to a low logic level. It should be appreciated that the timing of the pulses of the reset control signal RSTB can determine the duty cycle of the latch output signals AB _ EDGE, BC _ EDGE, and CA _ EDGE, thereby determining the duty cycle of the clock signal RCK.

According to various embodiments of the present invention, the duty cycle correction circuit may have different details. Referring to fig. 14, a detailed circuit diagram of an embodiment of the duty cycle correction circuit 1250 is shown. As shown, the duty cycle correction circuit 1500 has a time-to-digital converter (TDC) 1520. The TDC 1520 is used to measure time differences of adjacent EDGEs of the signals AB _ EDGE, BC _ EDGE, and CA _ EDGE, and accordingly converts the measured time differences into digital bit (TDC) results. The

selectors

1511 and 1512 are used to select two signals from the signals AB _ EDGE, BC _ EDGE, and CA _ EDGE to be measured by the TDC 1520. The TDC results will be averaged by the digital control circuit logic 1530 and the digital control logic 1530 outputs a delay control signal to control the delay line 1550 based on half of the averaged TDC results. The delay line 1550 is used for delaying the clock signal RCK, and a NAND gate 1540 is used for performing a NAND operation on the clock signal RCK and the delayed version of the clock signal RCK, thereby generating the reset control signal RSTB. When the time difference between the signals AB _ EDGE, BC _ EDGE and CA _ EDGE is long, the duty cycle of the clock signal RCK will be longer, and vice versa. Thus, the TDC result will reflect this condition, allowing the digital control logic 1530 to find the appropriate delay amount for the delay line, and thereby adjust the timing of the reset control signal RSTB such that the clock signal RCK has a duty cycle of about 50%. Note that NAND gate 1540 can be replaced by another type of logic gate or combination of logic gates, as long as they can provide the same result.

Please refer to fig. 15 and fig. 16 to better understand how the duty cycle correction circuit 1500 actually processes the repetitive input pattern "+ x → -y → + z → -x → + y → -z → + x" representing the symbol 3333333 and the repetitive input pattern "+ x → -z → + y → -x → + z → -y → -x → + x" representing the symbol 1111111.

Fig. 17 shows a detailed circuit diagram of another embodiment of the duty cycle correction circuit 1250 of the present invention. Duty cycle correction circuit 1800 includes a low pass RC filter that includes resistive element R and capacitive element C for filtering clock signal RCK. The low-pass RC filter generates a filtered signal Vduty. The comparator 1810 compares the signal Vduty with a predetermined signal VDD/2 to generate a comparison result UP. Digital control logic 1820 controls delay line 1840 based on the comparison UP. Through the low-pass RC filter, the duty cycle of the clock signal RCK is reflected and represented as the voltage level of the signal Vduty. Please refer to fig. 18. As shown, if the comparator 1810 detects that the voltage level of the signal Vduty is lower than the predetermined signal VDD/2, it means that the duty cycle of the clock signal RCK is lower than 50%. Therefore, the output signal UP of the comparator 1810 maintains the high logic level "1". Based on the UP output signal, the digital control logic 1820 generates a delay control signal to adjust the delay time of the delay line 1840. Once the comparator 1810 detects that the voltage level of the signal Vdut is equal to the predetermined signal VDD/2, it indicates that the duty cycle of the clock signal RCK is 50%. Therefore, the output signal UP of the comparator 1810 changes to the low logic level "0". Accordingly, digital control logic 1820 controls delay line 1840 to generate an appropriate delay (i.e., increase or decrease the delay until comparison UP shows no difference) according to comparison UP to generate reset control signal RSTB to calibrate clock signal RCK, thereby achieving 50% duty cycle.

Fig. 19 is a schematic diagram of CDR circuitry in a receiver for a MIPI C-PHY (or other three-wire-channel PHY standard) communication link in another embodiment of the present invention. The CDR circuit in fig. 19 has features and elements in common with the CDR circuit shown in fig. 12. However, the main difference between them is that the embodiment of fig. 19 generates the reset control signal using the delay adjustment unit 2000 instead of the duty correction circuit 1200. The delay adjusting unit 2000 generates the reset control signal RSTB according to the adjustable delay time and the clock signal RCK.

As described above, the clock signal RCK transitions to a high logic level at the rising edge of signals AB _ X, BC _ X and CA _ X and begins a new cycle. However, as shown by the circle in fig. 20, if the period of the signal BC _ edge is too long, the rising edges of the signals AB _ X and CA _ X will be masked. This is caused by an erroneous timing of the reset control signal RSTB. The error timing of the reset control signal RSTB resets the signal BC _ edge too slowly, thus masking the rising edges of the signals AB _ X and CA _ X. To prevent the rising edges of the signals AB _ X, BC _ X and CA _ X from being masked, the delay adjustment unit 2000 adjusts the reset control signal RSTB according to the sampling results AB _ O [0], BC _ O [0], and CA _ O [0] and the sampling results AB _ O [1], BC _ O [1], and CA _ O [1 ]. Specifically, delay adjustment unit 2000 detects the XOR output signal XOR [0] of XOR gate 2091 and XOR output signal XOR [1] of XOR gate 2092. XOR gate 2091 performs an XOR operation on the sampled results AB _ O [0], BC _ O [0], and CA _ O [0 ]. The sampling results AB _ O [0], BC _ O [0], and CA _ O [0] are generated by the sampling unit 2081 sampling the signals AB _ S, BC _ S and CA _ S according to the clock signal TCK. XOR gate 2092 performs an XOR operation on the sampled results AB _ O [1], BC _ O [1], and CA _ O [1 ]. The sampling results AB _ O [1], BC _ O [1], and CA _ O [1] are generated by the sampling unit 2082 sampling the signals AB _ S, BC _ S and CA _ S according to the inverted version of the clock signal TCK.

The delay adjustment circuit 2000 will start with an initial delay that ensures that the entire CDR circuit of fig. 19 is functioning properly. Then, the delay timing of the reset control signal RSTB is slowly increased by the circuit of the delay adjustment circuit 2000. Once an erroneous timing is made, it will be reflected as a signal transition in the XOR output signal XOR [0] and/or XOR output signal XOR [1 ]. Once the delay adjustment unit 2000 detects a signal transition of the XOR output signal XOR [0] and/or the XOR output signal XOR [1], it sets the adjustable delay time to half the error timing. As a result, the reset control signal RSTB resets 2031-2033 earlier than the error timing, which causes the falling EDGEs of the signals AB _ EDGE, BC _ EDGE, and CA _ EDGE to occur earlier without masking the next signal EDGE. Therefore, the clock signal RCK can reach nearly 50% of the duty cycle. For example, as shown in the circle portion of FIG. 20, if the reset control signal RSTB resets the latch 2031-2033 earlier than before, the falling edge of the latch output signal BC _ edge will occur earlier. In this way, the XOR output signals AB _ X and CA _ X will not be masked by the latch output signal BC _ edge, and the clock signal RCK can also properly follow the rising edges of the signals AB _ X and CA _ X.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.

Claims

1. A phy-layer circuit, the phy-layer circuit comprising:

four signal pads;

a four signal physical media attachment sublayer PMA, coupled to the four signal pads, comprising:

a four-signal terminal circuit coupled to the four signal pads;

a first differential amplifier coupled to a first signal pad and a second signal pad for receiving signals on the first signal pad and the second signal pad and outputting a first differential signal;

a second differential amplifier, coupled to the first signal pad and a third signal pad, for receiving signals on the first signal pad and the third signal pad, and outputting a second differential signal accordingly;

a third differential amplifier, coupled to the two switches, selectively coupled to the second signal pad and the third signal pad or the third signal pad and a fourth signal pad, for receiving signals on the second signal pad and the third signal pad or signals on the third signal pad and the fourth signal pad, and accordingly outputting a third differential signal;

a first signal processing block, coupled to the first differential amplifier, for processing the first differential signal when the four-signal PMA operates in a first physical layer mode;

a second signal processing block, coupled to the first, second and third differential amplifiers, for processing the first, second and third differential signals when the four-signal PMA operates in a second physical layer mode; and

a third signal processing block, coupled to the third differential amplifier, for processing the third differential signal when the four-signal PMA operates in the first physical layer mode.

2. The physical layer circuit of claim 1,

the first signal processing block includes:

a first sample-and-hold circuit, coupled to the first differential amplifier, for outputting a first serial data signal and a first serial clock signal according to the first differential signal in the first phy layer mode;

the third signal processing block includes:

a second sample and hold circuit, coupled to the third differential amplifier, for outputting a second serial data signal and a second serial clock signal according to the third differential signal in the first phy layer mode;

the second signal processing block includes:

a clock and data recovery CDR circuit coupled to the first, second and third differential amplifiers for outputting a set of third serial data signals and a third serial clock signal according to the first, second and third differential signals in the second PHY mode.

3. The phy layer circuit of claim 2 wherein the first signal processing block further comprises:

a first deserializer, coupled to the first sample and hold circuit, for deserializing the first serial data signal according to the first serial clock signal in the first physical layer mode to output a first deserialized data signal and a first deserialized clock signal;

the third signal processing block further comprises:

a third deserializer, coupled to the second sample and hold circuit, for deserializing the second serial data signal according to the second serial clock signal in the first physical layer mode to output a second deserialized data signal and a second deserialized clock signal; and

the second signal processing block further comprises:

a second deserializer, coupled to the CDR circuit, for deserializing the set of third serial data signals according to the third serial clock signal in the second physical layer mode to output a set of third deserialized data signals and a third deserialized clock signal; and

a decoding processor, coupled to the second de-sequencer, for decoding the set of third de-serialized data signals in the second physical layer mode.

4. The phy layer circuit of claim 2 wherein the second signal processing block further comprises:

a deserializer, coupled to the CDR circuit, for:

de-serializing the first serial data signal and the second serial data signal according to the serial clock signal in the first physical layer mode, thereby outputting a first de-serialized data signal, a second de-serialized data signal, and a de-serialized clock signal; and

deserializing the set of third serial data signals in the second physical layer mode according to the third serial clock signal to output a set of third deserialized data signals and a third deserialized clock signal; and

a decoding processor, coupled to the de-sequencer, for decoding the set of third de-serialized data signals in the second phy mode.

5. The phy layer circuit of claim 1 further comprising:

the N signal connecting pads comprise at least four signal connecting pads; and

the M shielding connection pads comprise at least one shielding connection pad coupled to the four-signal PMA;

wherein the at least one shielding pad is located between the second and third signal pads of the four signal pads, and M and N are positive integers.

6. The PHY layer circuit according to claim 5, wherein when the first PHY layer mode is selected, every two of the N signal pads are set to the same channel and when the second PHY layer mode is selected, every three of the N signal pads are set to the same channel.

7. The phy-layer circuit of claim 1 wherein the four-signal termination circuit comprises:

four adjustable resistive elements, each coupled to one of the four signal pads;

a conductive line coupled between a terminal of a first adjustable resistive element and a terminal of a second adjustable resistive element;

a first switch selectively coupled between a terminal of the second adjustable resistive element and a terminal of a third adjustable resistive element; and

a second switch selectively coupled between a terminal of the third adjustable resistive element and a terminal of a fourth adjustable resistive element;

wherein the first switch is controlled by a switch control signal and the second switch is controlled by an inverted version of the switch control signal.

8. A phy-layer circuit, the phy-layer circuit comprising:

six signal pads; and

a six-signal physical medium attachment sublayer PMA, coupled to the six signal pads, comprising:

a six-signal terminal circuit coupled to the six signal pads;

a fourth differential amplifier, coupled to the fourth signal pad and a fifth signal pad, for receiving the signals on the fourth signal pad and the fifth signal pad, and outputting a fourth differential signal accordingly;

a fifth differential amplifier, coupled to the fourth signal pad and a sixth signal pad, for receiving the signals on the fourth signal pad and the sixth signal pad, and outputting a fifth differential signal accordingly;

a sixth differential amplifier, coupled to the fifth signal pad and the sixth signal pad, for receiving the signals on the fifth signal pad and the sixth signal pad, and outputting a sixth differential signal accordingly;

a first signal processing block, coupled to the first differential amplifier, for processing the first differential signal when the six-signal PMA operates in a first physical layer mode;

a second signal processing block, coupled to the first, second and third differential amplifiers, for processing the first, second and third differential signals when the six-signal PMA operates in a second physical layer mode;

a third signal processing block, coupled to the third differential amplifier, for processing the third differential signal when the six-signal PMA operates in the first physical layer mode;

a fourth signal processing block, coupled to the fourth, fifth and sixth differential amplifiers, for processing the fourth, fifth and sixth differential signals when the sixth signal PMA operates in the second physical layer mode; and

a fifth signal processing block, coupled to the sixth differential amplifier, for processing the sixth differential signal when the sixth signal PMA operates in the first physical layer mode.

9. The physical layer circuit of claim 8,

the first signal processing block includes:

the third signal processing block includes:

the fifth signal processing block includes:

a third sample and hold circuit, coupled to the sixth differential amplifier, for outputting a third serial data signal and a third serial clock signal according to the sixth differential signal in the first phy layer mode;

the second signal processing block includes:

a first CDR circuit, coupled to the first, second and third differential amplifiers, for outputting a set of fourth serial data signals and a fourth serial clock signal according to the first, second and third differential signals in the second PHY mode; and

the fourth signal processing block includes:

a second CDR circuit, coupled to the fourth, fifth and sixth differential amplifiers, for outputting a set of fifth serial data signals and a fifth serial clock signal according to the fourth, fifth and sixth differential signals in the second phy layer mode.

10. The physical layer circuit of claim 9,

the first signal processing block further comprises:

the third signal processing block further comprises:

the fifth signal processing block further comprises:

a fifth deserializer, coupled to the third sample and hold circuit, for deserializing the third serial data signal according to the third serial clock signal in the first physical layer mode to output a third deserialized data signal and a third deserialized clock signal;

the second signal processing block further comprises:

a second deserializer, coupled to the first CDR circuit, for deserializing the set of fourth serial data signals according to the fourth serial clock signal in the second physical layer mode to output a set of fourth deserialized data signals and a fourth deserialized clock signal; and

a first decoding processor, coupled to the second de-sequencer, for decoding the set of fourth de-serialized data signals in the second phy mode;

the fourth signal processing block further comprises:

a fourth deserializer, coupled to the second CDR circuit, for deserializing the set of fifth serial data signals according to the fifth serial clock signal in the second physical layer mode to output a set of fifth deserialized data signals and a fifth deserialized clock signal; and

a second decoding processor, coupled to the fourth de-sequencer, for decoding the set of fifth de-serialized data signals in the second phy mode.

11. The phy layer circuit of claim 8 further comprising:

the N signal connecting pads comprise at least six signal connecting pads; and

the M shielding connection pads comprise at least one first shielding connection pad, one second shielding connection pad and one third shielding connection pad which are coupled to the six-signal PMA;

wherein the first shielding pad is located between the second and the third signal pads of the six signal pads; the second shielding connecting pad is positioned between a third signal connecting pad and a fourth signal connecting pad in the six signal connecting pads; the third shielding pad is located between the fourth and fifth signal pads of the six signal pads, wherein M and N are positive integers.

12. The PHY layer circuit according to claim 11, wherein when the first PHY layer mode is selected, every two of the N signal pads are arranged in a same channel and when the second PHY layer mode is selected, every three of the N signal pads are arranged in a same channel.

13. The phy layer circuit of claim 8 wherein the six signal termination circuit comprises:

six adjustable resistive elements, each coupled to one of the six signal pads;

a first conductive line coupled between a terminal of a first adjustable resistive element and a terminal of a second adjustable resistive element;

a second conductive line coupled between a terminal of a fifth adjustable resistive element and a terminal of a sixth adjustable resistive element;

a first switch selectively coupled between a terminal of the second adjustable resistive element and a terminal of a third adjustable resistive element;

a second switch selectively coupled between a terminal of the third adjustable resistive element and a terminal of a fourth adjustable resistive element; and

a third switch selectively coupled between a terminal of the fourth adjustable resistive element and a terminal of a fifth adjustable resistive element;

the first switch and the third switch are controlled by a switch control signal, and the second switch is controlled by an inverted version of the switch control signal.

14. A clock and data recovery circuit for a multi-wire interface, the circuit comprising:

a plurality of XOR gates, each coupled to a conductive line of the multi-line interface and each having a normal input and a delay input comprising a delay element, wherein each XOR gate receives the same signal on the conductive line from the normal input and the delay input and performs an XOR operation on the received signal and a delayed version of the signal to output an XOR output signal;

a plurality of latches, each coupled to one of the plurality of XOR gates, for latching a predetermined signal according to one of the plurality of XOR output signals to output a latch output signal, wherein the plurality of latches can be reset by a reset control signal;

an OR gate coupled to the latches for performing an OR operation on the latch output signals to output a clock signal; and

and the duty cycle correction circuit is coupled with the OR gate and used for generating a reset control signal according to the clock signal to correct the clock signal so as to enable the clock signal to have 50% of duty cycle.

15. The clock and data recovery circuit of claim 14, wherein the duty cycle correction circuit comprises:

a programmable delay line for delaying the clock signal according to a delay control signal to generate a delayed clock signal;

a time-to-digital converter for measuring a time difference of the plurality of XOR output signals to generate a measurement result;

a digital control circuit, coupled to the time-to-digital converter, for averaging the measurement result to generate the delay control signal accordingly; and

and the logic circuit is coupled with the programmable delay line and used for carrying out logic operation on the clock pulse signal and the delayed clock pulse signal so as to generate the reset control signal.

16. The clock and data recovery circuit of claim 14, wherein the duty cycle correction circuit comprises:

a low pass filter for filtering the clock signal to generate a filtered signal;

a comparator coupled to the low pass filter for comparing the filtered signal with a predetermined voltage signal to generate a comparison result;

a digital control circuit, coupled to the comparator, for generating the delay control signal according to the comparison result; and

17. A clock and data recovery circuit for a multi-wire interface, the circuit comprising:

a plurality of XOR gates, each coupled to a conductor in the multi-wire interface and each having a normal input and a delay input comprising a delay element, wherein each XOR gate receives the same signal on the conductor from the normal input and the delay input and performs an XOR operation on the received signal and a delayed version of the signal to output an XOR output signal;

and the delay adjusting unit is coupled with the OR gate and used for generating the reset control signal according to a plurality of output signals of a plurality of sampling units.

18. The clock and data recovery circuit of claim 17, further comprising:

the first sampling unit is coupled with the OR gate and used for sampling signals on a plurality of wires in the multi-wire interface according to the clock pulse signal so as to output a group of first output signals; and

a second sampling unit, coupled to the or gate, for sampling signals on the plurality of wires in the multi-wire interface according to the inverted version of the clock signal to output a set of second output signals;

a first XOR gate coupled to the first sampling unit for performing an XOR operation on the set of first output signals to output a first XOR output signal; and

a second XOR gate coupled to the second sampling unit for performing an XOR operation on the set of second output signals to output a second XOR output signal;

the delay adjusting unit is used for generating the reset control signal according to a delay time and the clock pulse signal, and adjusting the delay time according to the first XOR output signal and the second XOR output signal.