WO2023231461A1 - Chip and computer device - Google Patents

Abstract

Embodiments of the present application provide a chip, comprising: a pulse detection circuit, a filter circuit and an output circuit. The pulse detection circuit is used for acquiring an input signal, determining a first output signal according to the input signal, and sending the first output signal to the filter circuit, wherein the input signal corresponds to an input data signal of a C-port physical layer (C-PHY) protocol. The filter circuit is used for filtering the first output signal from the pulse detection circuit to obtain a second output signal, and sending the second output signal to the output circuit. The output circuit is used for determining a clock signal according to the second output signal. According to the described technical solution, glitches in the first output signal can be reduced or eliminated, so that the overshooting of the determined clock signal can be reduced or even eliminated.

Description

Chips and computer equipment

This application claims priority to the Chinese patent application filed with the China Patent Office on May 31, 2022, with the application number 202210614005.8 and the application name "Chip and Computer Equipment", the entire content of which is incorporated into this application by reference.

Technical field

The embodiments of the present application relate to the field of circuit technology, and more specifically, to a chip and a computer device.

Background technique

The C-port physical layer (PHY) protocol is proposed by the mobile industry processor interface (MIPI) organization. It has a lower transmission speed than M-PHY, but is more compatible with D-PHY. agreement.

C-PHY and D-PHY have many things in common, and most of the features of C-PHY are adapted from D-PHY. Therefore, C-PHY is designed to coexist with D-PHY on the same integrated circuit (IC) pin, so that dual-mode devices that support both C-PHY and D-PHY can be developed.

Although C-PHY reuses most of the D-PHY standards, the data encoding technology of C-PHY is essentially different from that of D-PHY. This is reflected in the following: 1) C-PHY uses three signal lines, while D-PHY Differential signal line pairs are used; 2) C-PHY uses quinary transmission, while D-PHY uses binary; 3) C-PHY does not have a separate clock signal, while D-PHY has a separate clock signal.

Since there is no separate clock signal, the C-PHY receiving system needs to recover the clock signal based on the signals transmitted in the three signal lines. Therefore, how to improve the accuracy of the recovered clock signal has become an issue that the industry needs to pay attention to.

Contents of the invention

Embodiments of the present application provide a chip and computer equipment that can reduce or eliminate glitches in the first output signal, thereby reducing or even eliminating the occurrence of the overshooting phenomenon in the determined clock signal.

In a first aspect, embodiments of the present application provide a chip, which includes: a pulse detection circuit, a filter circuit and an output circuit, wherein the pulse detection circuit is used to obtain an input signal and determine a first output signal based on the input signal, and sends the first output signal to the filter circuit, wherein the input signal corresponds to the input data signal of the C-port physical layer C-PHY protocol; the filter circuit is used to process the first output signal from the pulse detection circuit. The output signal is filtered to obtain a second output signal, and the second output signal is sent to the output circuit; the output circuit is used to determine a clock signal according to the second output signal.

A completed communication link (lane) of C-PHY consists of three physical connections, called A, B, and C respectively. Every time the transmitter sends a symbol, there are always two lines sending different high/low circuits, and the remaining one line sends the middle level. The input signal obtained by the pulse detection circuit is a differential signal. The differential signal includes differential signal AB, differential signal BC and differential signal CA. The differential signal AB is the input data signal A (that is, the data from line A signal) and the input data signal B (that is, the data signal from the B line), the differential signal BC is the input data signal B and the input data signal C (that is, the data signal from the C line), the differential signal CA is the input data signal C and the differential signal CA of the input data signal A.

The pulse detection circuit can obtain the first output signal by detecting edge changes of the input signal.

The differential signal AB, the differential signal BC and the differential signal CA are amplified signals, so the differential signal AB, the differential signal BC and the differential signal CA have large jitter. At the same time, there is also a clock skew (skew) between the differential signal AB, the differential signal BC and the differential signal CA. Therefore, the output of the pulse detection circuit is not a clock signal with the same frequency as the data, and there are many burrs caused by jitter, which leads to clock overshooting. The overshooting will cause false sampling, resulting in bit errors.

So ideally the first output signal should be a pulse signal with the same frequency as the data. However, due to glitches caused by jitter, the first output signal output by the pulse detection circuit is a pulse signal containing glitches.

The above technical solution adds a filter circuit capable of filtering high-frequency pulses between the pulse detection module and the output circuit. This can filter out burrs in the output signal of the pulse detection module, thereby reducing or even eliminating the occurrence of the recovered clock at certain points in time. Additional shooting occurs. In other words, the number of glitches in the second output signal output by the filter circuit is smaller than the number of glitches in the first output signal. Even, in some cases, there may be no glitches in the second output signal. In other words, the second output signal is also a pulse signal, but the second output signal contains a smaller number of glitches than the first output signal.

In conjunction with the first aspect, in a possible implementation of the first aspect, the filter circuit includes a hysteresis comparator, an integrating circuit and a comparator, wherein the first input terminal of the hysteresis comparator and the output terminal of the pulse detection circuit connected, the second input terminal of the hysteresis comparator is used to obtain the reference voltage; the first input terminal of the integrating circuit is connected to the output terminal of the hysteresis comparator, and the second input terminal of the integrating circuit is connected to the output circuit. In order to obtain the first control signal from the output circuit; the output terminal of the integrating circuit is connected to the input terminal of the comparator, and the output terminal of the comparator outputs the second output signal; the output circuit is also used to output the third a control signal.

The above technical solution uses two levels of filtering. The first level of filtering is implemented by a hysteresis comparator, and the second level of filtering is implemented by an integrating circuit and a comparator. If the input signal of a traditional single-limit comparator has slight interference near the threshold value, the output voltage will produce corresponding jitter (fluctuation). Hysteretic comparators have two threshold voltages. As long as the disturbance near the trip voltage value does not exceed the difference between the two threshold voltages, the value of the output voltage will be stable. Therefore, the first stage of filtering is implemented using a hysteresis comparator to filter out some glitches in the first output signal. The second stage of filtering can calculate the total area covered by the discontinuous high pulse train of the previous stage, and output a pulse with a frequency of the data rate, and the burrs caused by jitter and not processed by the first stage of filtering, then It can be further averaged out by the integrator in this process and will not be output.

In conjunction with the first aspect, in a possible implementation of the first aspect, the filter circuit includes an integrating circuit and a comparator, wherein the first input end of the integrating circuit is connected to the output end of the pulse detection circuit, and the integrating circuit The second input terminal is connected to the output circuit for obtaining the first control signal from the output circuit; the output terminal of the integrating circuit is connected to the input terminal of the comparator, and the output terminal of the comparator outputs the second Output signal; the output circuit is also used to output the first control signal.

The above technical solution uses an integrating circuit for filtering. The integrating circuit can calculate the total area covered by the discontinuous high pulse train of the first output signal, and output a pulse with a frequency of the data rate. The burrs caused by jitter can be averaged out by the integrator in the process. , will not be output.

Combined with the first aspect, in a possible implementation of the first aspect, the integrating circuit includes: a first field effect transistor, a second field effect transistor, a third field effect transistor, a first resistor, a second resistor and a capacitor, wherein the gates of the first field effect transistor and the second field effect transistor are connected to the first input of the integrating circuit terminal is connected, the gate of the third field effect transistor is connected to the second input terminal of the integrating circuit, the first port of the capacitor is connected to the output terminal of the integrating circuit, and the source of the first field effect transistor is connected to the capacitor. The first port of the capacitor is connected to the ground, the drain of the second field effect transistor is connected to the first port of the capacitor, and the source of the second field effect transistor is connected to the first port of the first resistor. connected, the second port of the first resistor is connected to ground; the drain of the third field effect transistor is connected to the first port of the capacitor, and the source of the third field effect transistor is connected to the first port of the second resistor, The second terminal of the second resistor is grounded.

The above technical solution uses the on-resistance and capacitance of the first field effect transistor to form an integrating circuit, thereby facilitating chip implementation.

In conjunction with the first aspect, in a possible implementation of the first aspect, the first resistor is an adjustable resistor, and the adjustable resistor includes a plurality of gears.

Configuring different resistors will affect the hysteresis windows of different sizes; the specific gear needs to be selected based on the maximum pattern-dependent jitter (PDJ) generated by the circuit/channel of the previous stage, so that it can be suitable for different situations. Eliminate burrs below. In addition, the hysteresis comparator can be configured with appropriate gears to achieve the best glitch filtering effect with the integrating circuit.

In conjunction with the first aspect, in a possible implementation of the first aspect, the output circuit includes a D flip-flop, a delay circuit and a control circuit, the delay circuit is used to obtain the second output signal, and the second output signal Perform delay processing to obtain a delayed signal; the control circuit is used to generate the first control signal according to the second input signal and the delay signal and send the first control signal to the integrating circuit, where the first control signal is the The logical OR signal of the second input signal and the delay signal; the control circuit is also used to determine a second control signal according to the first control signal, the second control signal is a logical negation signal of the first control signal; the D flip-flop, used to generate the clock circuit according to the second output signal and the second control signal.

In conjunction with the first aspect, in a possible implementation of the first aspect, the filter circuit includes a hysteresis comparator, wherein the first input terminal of the hysteresis comparator is connected to the output terminal of the pulse detection circuit, and the hysteresis comparator The second input terminal is used to obtain the reference voltage, and the output terminal of the hysteresis comparator outputs the second output signal.

If the input signal of a traditional single-limit comparator has slight interference near the threshold value, the output voltage will produce corresponding jitter (fluctuation). Hysteretic comparators have two threshold voltages. As long as the disturbance near the trip voltage value does not exceed the difference between the two threshold voltages, the value of the output voltage will be stable. Therefore, filtering using a hysteresis comparator can filter out some glitches in the first output signal.

In a second aspect, embodiments of the present application provide a chip that includes a pulse detection circuit, a hysteresis comparator and an integrating circuit, wherein the input end of the pulse detection circuit is used to obtain an input signal, and the input signal corresponds to the C-port The input data signal of the physical layer C-PHY protocol; the first input terminal of the hysteresis comparator is connected to the output terminal of the pulse detection circuit, and the second input terminal of the hysteresis comparator is used to obtain the reference voltage; the hysteresis comparator's The output terminal is connected to the first input terminal of the integrating circuit.

A completed communication link (lane) of C-PHY consists of three physical connections, called A, B, and C respectively. Every time the transmitter sends a symbol, there are always two lines sending different high/low circuits, and the remaining one line sends the middle level. The input signal obtained by the pulse detection circuit is a differential signal, and the differential signal includes differential signal AB, differential signal BC and differential signal CA. The differential signal AB, the differential signal BC and the differential signal CA are amplified signals, so the differential signal AB, the differential signal BC and the differential signal CA have large jitter. Simultaneous differential signal AB, difference There is also a clock skew (skew) between the partial signal BC and the differential signal CA. Therefore, the output of the pulse detection circuit is not a clock signal with the same frequency as the data, and there are many burrs caused by jitter, which leads to clock overshooting. The overshooting will cause false sampling, resulting in bit errors.

Therefore, ideally, the output signal of the pulse detection circuit should be a pulse signal with the same frequency as the data. However, due to glitches caused by jitter, the output signal output by the pulse detection circuit is a pulse signal containing glitches.

The above technical solution adds a hysteresis comparator and an integrating circuit capable of filtering high-frequency pulses between the pulse detection module and the output circuit. This can filter out burrs in the output signal of the pulse detection module, thereby reducing or even eliminating the frequency of the recovered clock at a certain point. Additional auctions may occur at certain points in time.

More specifically, the above technical solution uses two-stage filtering to filter burrs in the signal output by the pulse detection circuit. The first level of filtering is implemented by a hysteresis comparator, and the second level of filtering is implemented by an integrating circuit. If the input signal of a traditional single-limit comparator has slight interference near the threshold value, the output voltage will produce corresponding jitter (fluctuation). Hysteretic comparators have two threshold voltages. As long as the disturbance near the trip voltage value does not exceed the difference between the two threshold voltages, the value of the output voltage will be stable. Therefore, the first stage of filtering is implemented using a hysteresis comparator to filter out some glitches in the first output signal. The second stage of filtering can calculate the total area covered by the discontinuous high pulse train of the previous stage, and output a pulse with a frequency of the data rate, and the burrs caused by jitter and not processed by the first stage of filtering, then It can be further averaged out by the integrator in this process and will not be output. In other words, the output signal of the second stage filtering is also a pulse signal, but the number of burrs contained in this output signal is smaller than the number of burrs contained in the output signal of the pulse detection circuit.

Combined with the second aspect, in a possible implementation of the second aspect, the integrating circuit includes: a first field effect transistor, a second field effect transistor, a third field effect transistor, a first resistor, a second resistor and a capacitor. , the gates of the first field effect transistor and the second field effect transistor are connected to the first input terminal of the integrating circuit, the gate electrode of the third field effect transistor is connected to the second input terminal of the integrating circuit, and the capacitor The first port is connected to the output end of the integrating circuit, the source of the first field effect transistor is connected to the first port of the capacitor, the second port of the capacitor is grounded; the drain of the second field effect transistor is connected to the first port of the capacitor. The first port of the capacitor is connected, the source of the second field effect transistor is connected to the first port of the first resistor, the second port of the first resistor is connected to ground; the drain of the third field effect transistor is connected to the capacitor. The first port is connected, the source of the third field effect transistor is connected to the first port of the second resistor, and the second port of the second resistor is connected to ground.

The above technical solution uses the on-resistance and capacitance of the first field effect transistor to form an integrating circuit, thereby facilitating chip implementation.

In conjunction with the second aspect, in a possible implementation of the second aspect, the first resistor is an adjustable resistor, and the adjustable resistor includes a plurality of gears.

Configuring different resistors will affect the hysteresis windows of different sizes; the specific gear needs to be selected based on the maximum pattern-dependent jitter (PDJ) generated by the circuit/channel of the previous stage, so that it can be suitable for different situations. Eliminate burrs below. In addition, the hysteresis comparator can be configured with appropriate gears to achieve the best glitch filtering effect with the integrating circuit.

In conjunction with the second aspect, in a possible implementation of the second aspect, the chip further includes a comparator and an output circuit. The output circuit includes a D flip-flop, a delay circuit and a control circuit. The first input terminal of the comparator Connected to the output terminal of the integrating circuit, the second input terminal of the comparator is used to obtain the reference voltage; the input terminal of the delay circuit is connected to the output terminal of the comparator, and the output terminal of the delay circuit is connected to the third input terminal of the control circuit. One input terminal is connected; the second input terminal of the control circuit is used to obtain a control signal; the first output terminal of the control circuit is connected to the second input terminal of the integrating circuit; the second output terminal of the control circuit is connected to the D trigger The reset port of the D flip-flop is connected to the The output of the comparator is connected.

In a third aspect, embodiments of the present application provide a chip that includes a pulse detection circuit and an integrating circuit, wherein the input end of the pulse detection circuit is used to obtain an input signal, and the input signal corresponds to the C-port physical layer C- The input data signal of the PHY protocol; the first input terminal of the integrating circuit is connected to the output terminal of the pulse detection circuit.

A completed communication link (lane) of C-PHY consists of three physical connections, called A, B, and C respectively. Every time the transmitter sends a symbol, there are always two lines sending different high/low circuits, and the remaining one line sends the middle level. The input signal obtained by the pulse detection circuit is a differential signal, and the differential signal includes differential signal AB, differential signal BC and differential signal CA. The differential signal AB, the differential signal BC and the differential signal CA are amplified signals, so the differential signal AB, the differential signal BC and the differential signal CA have large jitter. At the same time, there is also a clock skew (skew) between the differential signal AB, the differential signal BC and the differential signal CA. Therefore, the output of the pulse detection circuit is not a clock signal with the same frequency as the data, and there are many burrs caused by jitter, which leads to clock overshooting. The overshooting will cause false sampling, resulting in bit errors.

Therefore, ideally, the output signal of the pulse detection circuit should be a pulse signal with the same frequency as the data. However, due to glitches caused by jitter, the output signal output by the pulse detection circuit is a pulse signal containing glitches.

The above technical solution adds an integrating circuit capable of filtering high-frequency pulses between the pulse detection module and the output circuit. This can filter out burrs in the output signal of the pulse detection module, thereby reducing or even eliminating the occurrence of the recovered clock at certain points in time. Additional shooting occurs. The integrating circuit can calculate the total area covered by the discontinuous high pulse train of the first output signal, and output a pulse with a frequency of the data rate. The burrs caused by jitter can be averaged out by the integrator in the process. , will not be output. In other words, the output signal of the integrating circuit is also a pulse signal, but the number of burrs contained in the output signal is smaller than the number of burrs contained in the output signal of the pulse detection circuit.

Combined with the third aspect, in a possible implementation of the third aspect, the integrating circuit includes: a first field effect transistor, a second field effect transistor, a third field effect transistor, a first resistor, a second resistor and capacitor, the gates of the first field effect transistor and the second field effect transistor are connected to the first input end of the integrating circuit, the gate electrode of the third field effect transistor is connected to the second input end of the integrating circuit, the The first port of the capacitor is connected to the output end of the integrating circuit, the source of the first field effect transistor is connected to the first port of the capacitor, the second port of the capacitor is grounded; the drain of the second field effect transistor is connected to the ground. The first port of the capacitor is connected, the source of the second field effect transistor is connected to the first port of the first resistor, the second port of the first resistor is connected to ground; the drain of the third field effect transistor is connected to the capacitor. The first port of the third field effect transistor is connected to the first port of the second resistor, and the second port of the second resistor is connected to ground.

In conjunction with the third aspect, in a possible implementation of the third aspect, the first resistor is an adjustable resistor, and the adjustable resistor includes a plurality of gears.

The above technical solution uses the on-resistance and capacitance of the first field effect transistor to form an integrating circuit, thereby facilitating chip implementation.

Configuring different resistors will affect the hysteresis windows of different sizes; the specific gear needs to be selected based on the maximum pattern-dependent jitter (PDJ) generated by the circuit/channel of the previous stage, so that it can be suitable for different situations. Eliminate burrs below. In addition, the hysteresis comparator can be configured with appropriate gears to achieve the best glitch filtering effect with the integrating circuit.

In conjunction with the third aspect, in a possible implementation of the third aspect, the chip further includes a comparator and an output circuit. The output circuit includes a D flip-flop, a delay circuit and a control circuit. The first input terminal of the comparator Connected to the output terminal of the integrating circuit, the second input terminal of the comparator is used to obtain the reference voltage; the input terminal of the delay circuit is connected to the comparator. The output end of the comparator is connected, the output end of the delay circuit is connected to the first input end of the control circuit; the second input end of the control circuit is used to obtain the control signal, and the first output end of the control circuit is connected to the integrating circuit The second input terminal of the control circuit is connected to the reset port of the D flip-flop; the clock port of the D flip-flop is connected to the output terminal of the comparator.

In a fourth aspect, embodiments of the present application provide a computer device, which computer device includes a printed circuit board and any possible implementation of the first aspect, the second aspect, the third aspect, or the first aspect to the third aspect. The chip is fixed on the printed circuit board.

Description of the drawings

Figure 1 is a schematic diagram of the receiving circuit at the receiving end.

Figure 2 is a schematic diagram of a clock recovery circuit.

Figure 3 is a timing diagram for the clock recovery circuit to recover the clock.

Figure 4 is a timing diagram of another clock recovery circuit recovering the clock.

Figure 5 is a schematic structural block diagram of a chip provided according to an embodiment of the present application.

FIG. 6 is a circuit diagram of the clock recovery circuit in the case where Scheme 1 is adopted.

FIG. 7 is a circuit diagram of the clock recovery circuit in the case of adopting Scheme 2.

FIG. 8 is a circuit diagram of the clock recovery circuit in the case where Scheme 3 is adopted.

Figure 9 is a schematic diagram of a hysteresis comparator.

Figure 10 is a schematic diagram of the integrating circuit.

Figure 11 is a schematic diagram of an interface circuit provided according to an embodiment of the present application.

Figure 12 is a schematic structural diagram of a chip provided according to an embodiment of the present application.

Figure 13 is a schematic structural diagram of a computer device provided according to an embodiment of the present application.

Figure 14 is a schematic structural diagram of a pulse detection circuit provided according to an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

In order to facilitate those skilled in the art to better understand the technical solution of the present application, some technologies involved in the technical solution of the present application are first introduced.

A completed communication link (lane) of C-PHY consists of three physical connections, called A, B, and C respectively. Every time the transmitter sends a symbol, there are always two lines sending different high/low circuits, and the remaining one line sends the middle level. Because the line that takes the high/low level each time a symbol is sent is not fixed, three lines at a time can represent 3×2=6 states. In the protocol, these 6 states are represented by +x,-x,+y,-y,+z,-z. At the same time, according to the protocol, the code elements sent each time must be different from the last time, that is, the status of the three lines will change each time; that is, each time it will change from one of the 6 states to the remaining 5 states. A sort of. C-PHY uses state changes for encoding. There are 5 possibilities for each state change. The C-PHY protocol stipulates that 7 consecutive codes are used to correspond (the value space of the code element sequence is defined by state changes, that is, there are 5 ⁷ = 78125 possibilities). Although there is redundancy in the 16-bit information space (a total of 2 ¹⁶ = 65536 possibilities), coverage can be guaranteed.

At the receiving end, the method of subtracting the signals on the three lines is used to obtain a 3-bit signal each time, corresponding to the status of the three lines; the corresponding circuit can, based on the changes in the 3-bit signal, define the C-PHY protocol Decode according to the coding principle and restore the original binary information.

Figure 1 is a schematic diagram of the receiving circuit at the receiving end.

As shown in Figure 1, among the three lines A, B, and C, line A and line B are connected to the continuous time linear equalizer (CTLE) 101, lines B and C are connected to CTLE 102, and line A and Line C is connected to CTLE103. CTLE 101 outputs the differential signal AB between line A and line B, CTLE 102 outputs the differential signal BC between line B and line C, and CTLE 103 outputs the differential signal CA between line C and line A.

Table 1 is the receiving end encoding table.

Table 1

As shown in Table 1, when the wire state is +x, the line voltage received by line A is high (3/4 volt (V)), and the voltage received by line B is low. level (1/4V), the voltage received by line C is the middle level (1/2V); the differential signal AB is 1/2V, the differential signal BC is -1/4, and the differential signal CA is -1/4. If the value of the differential signal is greater than 0, the corresponding digital output is 1; if the value of the differential signal is less than 0, the corresponding digital output is 0. Factor, when the online status is +x, the digital output at the receiving end is 100.

In order to recover the clock signal, a clock recovery circuit is usually connected after the CTLE. The clock recovery circuit recovers the clock signal based on the differential signal AB, the differential signal BC and the differential signal CA.

Figure 2 is a schematic diagram of a clock recovery circuit.

The clock recovery circuit 200 shown in FIG. 2 includes a pulse detection circuit 201, a D flip-flop (D type flip-flop, DFF) 202 and a delay line 203.

Pulse detection circuit 201 receives differential signals from CTLE 101 to CTLE 103. The pulse detection circuit 201 will output a pulse signal with a fixed frequency according to the transition of these differential signals. According to the requirements of the C-PHY protocol, each data symbol of the C-PHY differential signal AB, differential signal BC, and differential signal CA will jump once. Therefore, under ideal conditions, the pulse detection circuit 201 detects the edge change of data and can output a pulse signal with the same frequency as the data rate. For example, a 3.5 gigabits per second (Gbps) data signal can generate a 3.5GHz narrow pulse through the pulse detection circuit 201 . This clock will be sent to DFF 202 to sample a constant high level (i.e., TieH shown in Figure 2), and the generated edge will pass through the delay line 203 with configurable delay to generate a mask to reset DFF 202 to 0. The falling edge of the clock is obtained, thereby recovering a 3.5G clock at the output of DFF 202. The C-PHY receiving system uses this clock to sample data and deserialize and output the A, B, and C three-line codes.

Figure 3 is a timing diagram for the clock recovery circuit to recover the clock.

As shown in Figure 3, AB/BC/CA is the differential signal AB, the differential signal BC and the differential signal CA; the edge detection is the signal output by the pulse detection circuit 201; the mask is the mask generated by the delay line 203; the clock signal is DFF 202 recovers the correct frequency clock.

Since the differential signal AB, the differential signal BC and the differential signal CA are signals amplified by CTLE, there is a large jitter in the differential signal AB, the differential signal BC and the differential signal CA. At the same time, there is also a clock skew (skew) between the differential signal AB, the differential signal BC and the differential signal CA. Therefore, the output of the pulse detection circuit 201 is not a pure clock signal with the same frequency as the data, but there are many high-frequency pulses caused by jitter, and such a clock cannot be used. Therefore, it is necessary to use the subsequent delay-adjustable delay line 203 to select an appropriate mask to eliminate the high-frequency pulses caused by the output of the pulse detection circuit 201 and recover a clock with a correct frequency, that is, the clock signal in Figure 3.

A suitable mask can be found in the timing diagram shown in Figure 3 to recover the clock signal with the correct frequency. However, with the evolution of products, the CTLE before the clock recovery circuit will be designed to lower and lower voltage domains (such as 1.8V->1.2V). The reduction in voltage will greatly deteriorate the linearity of the CTLE, resulting in differential signals AB, The jitter of the differential signal BC and the differential signal CA deteriorates. At the same time, for competitiveness considerations, the actual form of the product may integrate C-PHY and D-PHY circuits into the same chip. The CTLE circuit of C-PHY is often implemented by reusing the CTLE of D-PHY. The physical design can easily cause the mismatch of the three CTLEs in Figure 1. The inter-symbol interference (ISI) and insertion loss of the C-PHY channel are also much greater than those of the D-PHY. To sum up, the high-frequency pulses (also called glitches) output by the pulse detection module that are not at the target frequency will increase significantly; this will directly cause the recovered clock to have glitches at certain points in time, and these glitches will cause the clock to increase. The beat causes false sampling, resulting in bit errors.

Figure 4 is a timing diagram of another clock recovery circuit recovering the clock. As shown in the timing diagram shown in Figure 4, there is an increase in clock beats caused by glitches.

Increasing the mask length is a solution to filter out unwanted high-frequency pulses. However, this will cause the mask length to be too long, causing the clock of the next beat to be reset, causing the clock to lose a beat, which will also lead to bit errors. If you want to filter high-frequency pulses by increasing the mask length but at the same time avoid clock missing due to too long mask length, then the mask length of the clock recovery circuit must be at least greater than the maximum jitter of the CTLE output, and at the same time less than 1 symbol minus The maximum jitter satisfies formula 1.1:

max_pdj<Clock _mask <UI-max_pdj, (Formula 1.1)

Among them, max_pdj is the maximum pattern dependent jitter (PDJ) output by CTLE, Clock _mask is the mask length, and UI is the length of one symbol.

The constraints of Equation 1.1 make it very difficult to design a clock recovery module. It is necessary to take into account the jitter of the CTLE output, but at the same time it cannot be too large to reset to the next clock edge that should be recovered. When the process, voltage, and temperature fluctuate, the robustness of the circuit using this solution will also be relatively poor.

This application provides a chip. The clock recovery circuit included in the chip adds a filter circuit capable of filtering burrs between pulse detection and DFF, so that burrs in the output signal of the pulse detection module can be filtered out without extending the mask. This reduces the occurrence of additional shots in the recovered clock at certain points in time.

Figure 5 is a schematic structural block diagram of a chip provided according to an embodiment of the present application. The chip 500 shown in FIG. 5 includes a pulse detection circuit 510, a filter circuit 520 and an output circuit 530.

The chip shown in Figure 5 can be a system on chip (SoC), a central processor (central processor unit, CPU), or a graphics processor (graphics processing unit, GPU), or It is an application processor (application processor, AP), etc.

The input signals acquired by the pulse detection circuit 510 are three differential signals output by CTLE, namely differential signal AB, differential signal BC and differential signal CA.

The pulse detection circuit 510 is used to obtain the input signal, determine the first output signal according to the input signal, and The first output signal is sent to filter circuit 520 .

The pulse detection circuit 510 may use a pulse detection circuit in a currently commonly used clock recovery circuit. For example, the pulse detection circuit 510 can generally be implemented using simple AND gate and OR gate combination logic. Figure 14 shows schematic diagrams of two pulse detection circuits. The pulse detection circuit shown in (a) of FIG. 14 can be implemented by a delay unit, an exclusive OR gate (XOR), and an OR gate (OR). The pulse detection circuit shown in (b) of FIG. 14 can be implemented by a delay unit, a NAND gate (NAND), and an OR gate (OR).

The filter circuit 520 is used to filter the first output signal from the pulse detection circuit 510 to reduce glitches in the first output signal. The signal obtained after filtering can be called the second output signal. Filter circuit 520 sends the second output signal to output circuit 530.

The output circuit 530 is used to determine the clock signal according to the second output signal.

In some embodiments, a hysteresis comparator may be used to implement glitch filtering. In other words, filter circuit 520 may be a hysteretic comparator.

In other embodiments, an integrating circuit may be used to implement glitch filtering, and then a comparator may be used to output a square wave signal. In other words, the filter circuit 520 can be implemented by an integrating circuit and a comparator.

In other embodiments, a hysteresis comparator and an integrating circuit may be used simultaneously to implement glitch filtering. In this case, the output signal of the integrating circuit can be processed using a comparator to obtain a square wave. In other words, the filter circuit 520 may include a hysteresis comparator, an integrating circuit, and a comparator.

Table 2 lists possible filter circuit implementations.

Table 2

The following introduces options 1 to 3 respectively.

Those skilled in the art can understand that in addition to pulse detection circuits, filter circuits and output circuits, the chip may also include other components. For example, CTLE used to obtain differential signals, logic circuits used to process data, etc. For ease of description, the pulse detection circuit, filter circuit and output circuit are collectively referred to as clock recovery circuits below.

FIG. 6 is a circuit diagram of the clock recovery circuit in the case where Scheme 1 is adopted.

As shown in FIG. 6 , one input terminal of the hysteresis comparator 521 is connected to the output terminal of the pulse detection circuit 510 for obtaining the output signal of the pulse detection circuit 510 , and the other input terminal is used for obtaining the reference voltage Vref.

The output end of the hysteresis comparator 521 shown in Figure 6 is connected to the clock (clock, CLK) pin of the DFF 532. In addition, the output terminal of the hysteresis comparator 521 is connected to one terminal of the switch 535 , and the other terminal of the switch 535 is connected to the input terminal of the delay circuit 531 .

The output terminal of the delay circuit 531 is connected to a control circuit implemented by a logic gate circuit. The control circuit includes an OR gate 533 and a NOT gate 534 . One input terminal of the OR gate 533 is connected to the output terminal of the delay circuit 531, and the other input terminal of the OR gate 533 is used to obtain the input signal (ie, ACK shown in FIG. 6). The output terminal of the OR gate 533 is connected to the input terminal of the NOT gate 534, and the output terminal of the NOT gate 534 is connected to the reset terminal of the DFF 532.

In some embodiments, the output terminal of the delay circuit 531 may also be directly connected to the reset terminal of the DFF 532 .

The D port of DFF 532 inputs the operating voltage, and the Q port output is the recovered clock signal.

When the circuit starts to work, the DFF 532 is first reset through the ACK signal and the control switch 535 is closed. In other words, the ACK signal is a high level when the circuit starts working. After the DFF 532 is reset, the ACK signal returns to a low level. When the signal output by hysteresis comparator 531 is low level, DFF 532 will not flip and Q remains low level. When the signal output by the hysteresis comparator 531 is high level, the state of DFF 532 is reversed, and Q becomes high level; after a period of delay (the delay size is determined by the delay circuit 531), the DFF 532 is reset, and Q becomes high level. into a low level, that is, DFF 532 outputs a positive pulse, that is, a clock pulse is recovered.

FIG. 7 is a circuit diagram of the clock recovery circuit in the case of adopting Scheme 2. In the case of using Scheme 2, the filter circuit shown in FIG. 5 includes an integrating circuit 522 and a comparator 523.

As shown in FIG. 7 , the integrating circuit 522 includes three metal-oxide-semiconductor field-effect transistors (MOSFETs) (also referred to as MOS transistors for short) and two resistors. The three MOS tubes can be called MOS tube M1, MOS tube M2 and MOS tube M3 respectively, and the two resistors can be called resistor R4 and resistor R5 respectively. In addition, the integrating circuit 522 also includes a capacitor, which may be called a capacitor C.

As shown in FIG. 7 , the gates of the MOS transistor M1 and the MOS transistor M2 are connected to the output terminal of the pulse detection circuit 510 for receiving the first output signal from the pulse detection circuit 510 . Therefore, it can be considered that point a shown in FIG. 7 is equivalent to an input terminal of the integrating circuit 522 (which can be called a first input terminal).

The gate of the MOS transistor M3 is connected to the output terminal of the OR gate 533 in the output circuit 530 for receiving the input signal from the OR gate 533. Therefore, it can be considered that point b shown in FIG. 7 is equivalent to another input terminal of the integrating circuit 522 (which can be called the second input terminal).

As shown in Figure 7, one end of the capacitor C is connected to the source of the MOS tube M1, and the other end of the capacitor C is connected to the ground. For the convenience of description, the end of the capacitor C connected to the MOS transistor M1 can be called the first port of the capacitor C, and the end of the capacitor C connected to the ground can be called the second port of the capacitor C. The first port of the capacitor C is also connected to the drain of the MOS transistor M2 and the drain of the MOS transistor M3. In addition, the first port of the capacitor C is also connected to the positive input terminal of the comparator 523 . Therefore, it can be considered that point c in FIG. 7 is equivalent to the output terminal of the integrating circuit 522.

One end of resistor R5 is connected to the drain of MOS tube M2. The other end of resistor R5 is connected to ground.

One end of the resistor R4 is connected to the drain of the MOS transistor M3. The other end of resistor R4 is connected to ground.

The resistor R5 shown in Figure 7 is an adjustable resistor, and the adjustable resistor may include multiple gears, and the multiple gears may correspond to multiple PDJs one by one. In this way, the integration circuit 522 can be applied to different PDJ scenarios. In other words, the range of resistor R5 corresponds to the range of burrs. Therefore, if the resistor R5 is an adjustable resistor, then the burrs in different ranges can be filtered by adjusting the gear of the resistor R5.

Of course, in some embodiments, the resistor R5 can also be set as a fixed resistor. In this case, the resistance value of resistor R5 can be a resistance value that can filter out glitches in a larger range. Although the same effect as the adjustable resistor can be achieved in this case, it requires a larger area, which is not conducive to the integrated design of the chip.

The output of the comparator 523 shown in Figure 7 is connected to the CLK pin of the DFF 532. In addition, the output terminal of the comparator 523 is connected to one terminal of the switch 535, and the other terminal of the switch 535 is connected to the input terminal of the delay circuit 531.

The output terminal of the delay circuit 531 is connected to a control circuit implemented by a logic gate circuit. The control circuit includes an OR gate 533 and a NOT gate 534 . One input terminal of the OR gate 533 is connected to the output terminal of the delay circuit 531, and the other input terminal of the OR gate 533 is used to obtain the input signal (ie, ACK shown in FIG. 6). The output terminal of the OR gate 533 and the input terminal of the NAND gate 534 connected, the output terminal of the NOT gate 534 is connected to the reset terminal of the DFF 532 . The output terminal of the OR gate 533 is also connected to the second input terminal of the integrating circuit 522 .

When the circuit shown in Figure 7 starts to work, the DFF 532 is first reset through the ACK signal, and the configuration switch 535 is closed. In other words, the ACK signal is a high level when the circuit starts working. After the DFF 532 is reset, the ACK signal returns to a low level. When MOS tube M1 first starts charging capacitor C, the voltage on capacitor C is low, that is, the voltage at point c is low, and the corresponding comparator 523 outputs, that is, the voltage at point d is low. At this time, DFF 532 will not flip, and Q remains low level. When the voltage on the capacitor C exceeds the threshold level (i.e., the input level Hi_TH at the negative input terminal of the comparator 523), the comparator 523 outputs a high level, that is, the potential of point d is pulled high, the state of DFF 532 is reversed, and Q becomes High level; after a period of delay (the delay size is determined by the delay circuit 531), the DFF 532 is reset, and Q becomes a low level, that is, the DFF 532 outputs a positive pulse, that is, a clock pulse is recovered. At the same time, the high-level signal output by the OR gate 533 releases the stored charge in the capacitor C.

In the circuit shown in Figure 7, when point a is high level, MOS tube M2 is turned off and MOS tube M1 is turned on. In this case, the on-resistance of MOS transistor M1 and the capacitor C form an integrator and perform charging operation. The integrator composed of MOS tube M1 and capacitor C can calculate the total area covered by the discontinuous high pulse train of the previous stage, and output a pulse with a frequency of the data rate, and the glitch caused by jitter can be In this process, it is further averaged out by the integrator and will not be output.

FIG. 8 is a circuit diagram of the clock recovery circuit in the case where Scheme 3 is adopted. In the case of using Scheme 2, the filter circuit shown in FIG. 5 includes a hysteresis comparator 521, an integrating circuit 522 and a comparator 523.

The hysteresis comparator 521 used in the clock recovery circuit shown in FIG. 8 is the hysteresis comparator 521 used in the clock recovery circuit shown in FIG. 6 . The integrating circuit 522 and comparator 523 used in the clock recovery circuit shown in FIG. 8 are the same integrating circuit 522 and comparator 523 used in the clock recovery circuit shown in FIG. 7 .

As shown in FIG. 8 , one input terminal of the hysteresis comparator 521 is connected to the output terminal of the pulse detection circuit 510 for obtaining the output signal of the pulse detection circuit 510 , and the other input terminal is used for obtaining the reference voltage Vref.

The output terminal of the hysteresis comparator 521 is connected to the first input terminal of the integrating circuit 522 . In other words, the gates of the MOS transistor M1 and the MOS transistor M2 of the integrating circuit 522 are connected to the output terminal of the hysteresis comparator 521 to obtain the output signal output by the hysteresis comparator 521 . The connection methods of various components in the integrating circuit 522, the comparator 523 and the output circuit 530 in Figure 8 are similar to those in Figure 7, and for the sake of simplicity, they will not be described again here.

When the circuit shown in Figure 8 starts to work, the DFF 532 is first reset through the ACK signal, and the configuration switch 535 is closed. In other words, the ACK signal is a high level when the circuit starts working. After the DFF 532 is reset, the ACK signal returns to a low level. When MOS tube M1 first starts charging capacitor C, the voltage on capacitor C is low, that is, the voltage at point c is low, and the corresponding comparator 523 outputs, that is, the voltage at point d is low. At this time, DFF 532 will not flip, and Q remains low level. When the voltage on the capacitor C exceeds the threshold level (i.e., the input level Hi_TH at the negative input terminal of the comparator 523), the comparator 523 outputs a high level, that is, the potential of point d is pulled high, the state of DFF 532 is reversed, and Q becomes High level; after a period of delay (the delay size is determined by the delay circuit 531), the DFF 532 is reset, and Q becomes a low level, that is, the DFF 532 outputs a positive pulse, that is, a clock pulse is recovered. At the same time, the high-level signal output by the OR gate 533 releases the stored charge in the capacitor C.

In the circuit shown in Figure 8, when the output of hysteresis comparator 521 causes point a to be high level, MOS tube M2 is turned off and MOS tube M1 is turned on. In this case, the on-resistance of MOS transistor M1 and the capacitor C form an integrator and perform charging operation. The integrator composed of MOS tube M1 and capacitor C can cover the discontinuous high pulse train with the previous stage. The total area of the cover is calculated, and the output is a pulse with a frequency of the data rate. The glitches caused by jitter and not processed by the pre-stage hysteresis comparator 521 can be further averaged out by the integrator in this process. will be output.

Those skilled in the art can understand that the hysteresis comparator 521 shown in FIG. 6 and FIG. 8 is just an example of a hysteresis comparator. The hysteresis comparator used in the clock recovery circuit 500 may also be a hysteresis comparator with other structures. Figure 9 is a schematic diagram of a hysteresis comparator.

Figure 9(a), Figure 9(b) and Figure 9(c) are schematic diagrams of three different hysteresis comparators. In some embodiments, the hysteresis comparator 521 shown in FIGS. 6 and 8 may be replaced with (a) in FIG. 9 , (b) in FIG. 9 , or (c) in FIG. 9 . When (a) in FIG. 9, (b) in FIG. 9, or (c) in FIG. 9 is used to replace the hysteresis comparator 521 shown in FIG. 6 and FIG. 8, (a) in FIG. 9, FIG. Vin in (b) in Figure 9 or (c) in Figure 9 is the input terminal of the hysteresis comparator, used to connect the pulse detection circuit 510, Vout is the output terminal of the hysteresis comparator, used for DFF 532 or integration circuit 522 .

Those skilled in the art may realize that in addition to the three hysteresis comparators shown in FIG. 9 , other hysteresis comparators may also be used to replace the hysteresis comparator 521 shown in FIGS. 6 and 8 .

Similarly, the integrating circuit 522 shown in FIGS. 7 and 8 is just an example of an integrating circuit. The integrating circuit applied to the clock recovery circuit 500 may also be an integrating circuit with other structures. Figure 10 is a schematic diagram of the integrating circuit.

(a) in Figure 10, (b) in Figure 10 and (c) in Figure 10 are schematic diagrams of three different integrating circuits. In some embodiments, the integrating circuit 522 shown in FIGS. 7 and 8 may be replaced with (a) in FIG. 10 , (b) in FIG. 10 , or (c) in FIG. 10 . When replacing the integrating circuit 522 shown in FIGS. 7 and 8 with (a) in FIG. 10 , (b) in FIG. 10 or (c) in FIG. 10 , (a) in FIG. 10 , FIG. 10 Vin in (b) or (c) in Figure 10 is the input terminal of the integrating circuit, used to connect the pulse detection circuit 510 or the hysteresis comparator 521, and Vout is the output terminal of the integrating circuit, used for the comparator 523.

Figure 11 is a schematic diagram of an interface circuit provided according to an embodiment of the present application. The interface circuit 1100 shown in FIG. 11 includes a CTLE circuit 1101 and a clock recovery circuit 1102. The clock recovery circuit 1102 may be any clock recovery circuit shown in FIG. 6 to FIG. 8 .

Figure 12 is a schematic structural diagram of a chip provided according to an embodiment of the present application. The chip 1200 shown in FIG. 12 includes an interface circuit 1201 and a logic circuit 1202. The logic circuit 1202 is coupled to the interface circuit 1201 and is used for receiving the signal output by the interface circuit 1201.

The chip shown in Figure 12 can be a system on chip (SoC), a central processor unit (CPU), a graphics processor (graphics processing unit, GPU), or It is an application processor (application processor, AP), etc.

Figure 13 is a schematic structural diagram of a computer device provided according to an embodiment of the present application. As shown in Figure 13, computer device 1300 includes a chip 1301 and a printed circuit board (PCB) 1302. Chip 1301 is provided on PCB 1302.

The computer device 1300 shown in Figure 13 may also include other necessary components, such as memory, sensors, display units, input units, audio circuits, etc.

In some embodiments, computer device 1300 may also include a camera module. The camera module is connected to the chip 1301 and sends data based on C-PHY to the chip 1301.

The computer device shown in Figure 13 may be a mobile phone, a laptop, a tablet, a car, a drone, and other computer devices.

In the embodiments shown in Figures 5 and 12, the interface circuit is a circuit inside the chip. In other embodiments, the interface circuit may also be a discrete device. For example, a mobile phone includes a motherboard, which includes chips. The mainboard is connected to the camera module through a flexible printed circuit (FPC) and the interface circuit.

Similarly, the camera module in the computer device shown in Figure 13 can also be an independent device. In other words, there may be a computer system that includes two independent computer devices, and the two computer devices may be referred to as computer device 1 and computer device 2 respectively. Each of the computer devices 1 and 2 may include components such as chips, memories, and interface circuits.

In some embodiments, the computer device 1 may be a computer device capable of processing video and/or imaging functions. For example, the computer device 1 may be a laptop computer, a desktop computer, or other computer device. The computer device 2 may be a computer device with video and/or photography functions. For example, the computer device 2 may be a digital camera, a digital video camera, a video camera, or other computer device. The computer device 1 includes an interface circuit as shown in FIG. 11 . The computer device 1 is connected to the computer device 2 through the interface circuit. Computer device 2 sends C-PHY based data to computer device 1 . In this way the computer device 1 can process the video/image data acquired by the computer device 2 .

In other embodiments, the computer device 1 may be a computer device capable of processing video and/or image functions. For example, the computer device 1 may be a laptop computer, a desktop computer, or other computer device. The computer device 2 is a computer device having a display function. For example, the computer device 2 may be a monitor, a television, a virtual reality device (virtual reality, VR), an augmented reality (augmented reality, AR) device, etc. In this case, the computer device 2 includes an interface circuit as shown in FIG. 11 . The computer device 2 is connected to the computer device 1 through the interface circuit. Computer device 1 sends C-PHY based data to computer device 2. In this way the computer device 2 can display the video/image data provided by the computer device 1 .

Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each specific application, but such implementations should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be described again here.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any familiar It is understood that those skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application, and they should all be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (19)

1. A chip, characterized in that the chip includes: a pulse detection circuit, a filter circuit and an output circuit, wherein

   The pulse detection circuit is used to obtain an input signal, determine a first output signal according to the input signal, and send the first output signal to the filter circuit, where the input signal corresponds to the C-port physical Input data signal of layer C-PHY protocol;

   The filter circuit is used to filter the first output signal from the pulse detection circuit to obtain a second output signal, and send the second output signal to the output circuit;

   The output circuit is used to determine a clock signal according to the second output signal.
2. The chip according to claim 1, characterized in that the filter circuit includes a hysteresis comparator, an integrating circuit and a comparator, wherein

   The first input terminal of the hysteresis comparator is connected to the output terminal of the pulse detection circuit, and the second input terminal of the hysteresis comparator is used to obtain a reference voltage;

   The first input terminal of the integrating circuit is connected to the output terminal of the hysteresis comparator, and the second input terminal of the integrating circuit is connected to the output circuit for obtaining the first control signal from the output circuit. ;

   The output terminal of the integrating circuit is connected to the input terminal of the comparator, and the output terminal of the comparator outputs the second output signal;

   The output circuit is also used to output the first control signal.
3. The chip according to claim 1, characterized in that the filter circuit includes an integrating circuit and a comparator, wherein

   The first input terminal of the integrating circuit is connected to the output terminal of the pulse detection circuit, and the second input terminal of the integrating circuit is connected to the output circuit for obtaining the first control signal from the output circuit. ;

   The output terminal of the integrating circuit is connected to the input terminal of the comparator, and the output terminal of the comparator outputs the second output signal;

   The output circuit is also used to output the first control signal.
4. The chip according to claim 2 or 3, characterized in that the integrating circuit includes: a first field effect transistor, a second field effect transistor, a third field effect transistor, a first resistor, a second resistor and a capacitor, in

   The gates of the first field effect transistor and the second field effect transistor are connected to the first input end of the integrating circuit, and the gate electrode of the third field effect transistor is connected to the second input end of the integrating circuit. connected, the first port of the capacitor is connected to the output end of the integrating circuit,

   The source of the first field effect transistor is connected to the first port of the capacitor, and the second port of the capacitor is connected to ground;

   The drain of the second field effect transistor is connected to the first port of the capacitor, the source of the second field effect transistor is connected to the first port of the first resistor, and the second port of the first resistor is connected to the first port of the first resistor. Port ground;

   The drain of the third field effect transistor is connected to the first port of the capacitor, the source of the third field effect transistor is connected to the first port of the second resistor, and the second port of the second resistor is connected to the first port of the second resistor. The port is grounded.
5. The chip according to claim 4, wherein the first resistor is an adjustable resistor, and the adjustable resistor includes a plurality of gears.
6. The chip according to any one of claims 2 to 5, wherein the output circuit includes a D flip-flop, a delay circuit and a control circuit,

   The delay circuit is used to obtain the second output signal, perform delay processing on the second output signal, and obtain a delayed signal;

   The control circuit is configured to generate the first control signal according to the second input signal and the delay signal and send the first control signal to the integrating circuit, where the first control signal is the third a logical OR signal of two input signals and the delayed signal;

   The control circuit is further configured to determine a second control signal based on the first control signal, where the second control signal is a logical negation signal of the first control signal;

   The D flip-flop is used to generate the clock circuit according to the second output signal and the second control signal.
7. The chip according to claim 1, characterized in that the filter circuit includes a hysteresis comparator, wherein

   The first input terminal of the hysteresis comparator is connected to the output terminal of the pulse detection circuit, the second input terminal of the hysteresis comparator is used to obtain the reference voltage, and the output terminal of the hysteresis comparator outputs the second output signal.
8. The chip according to any one of claims 1 to 7, characterized in that the pulse detection circuit is specifically used to detect edge changes of the input signal to obtain the first output signal.
9. The chip according to any one of claims 1 to 8, wherein the input signal includes a differential signal AB, a differential signal BC and a differential signal CA, wherein the differential signal AB is an input data signal A and an input data signal The differential signal BC is the differential signal of the input data signal B and the input data signal C, and the differential signal CA is the differential signal of the input data signal C and the input data signal A.
10. The chip according to any one of claims 1 to 9, characterized in that the first output signal is a pulse signal containing glitches, the second output signal is a pulse signal, and the second output signal contains The glitches are less than the glitches contained in the first output signal.
11. A chip, characterized in that the chip includes a pulse detection circuit, a hysteresis comparator and an integrating circuit, wherein,

    The input end of the pulse detection circuit is used to obtain an input signal, and the input signal corresponds to the input data signal of the C-port physical layer C-PHY protocol;

    The first input terminal of the hysteresis comparator is connected to the output terminal of the pulse detection circuit, and the second input terminal of the hysteresis comparator is used to obtain a reference voltage;

    The output terminal of the hysteresis comparator is connected to the first input terminal of the integrating circuit.
12. The chip according to claim 11, characterized in that the integrating circuit includes: a first field effect transistor, a second field effect transistor, a third field effect transistor, a first resistor, a second resistor and a capacitor,

    The gates of the first field effect transistor and the second field effect transistor are connected to the first input end of the integrating circuit, and the gate electrode of the third field effect transistor is connected to the second input end of the integrating circuit. connected, the first port of the capacitor is connected to the output end of the integrating circuit,

    The source of the first field effect transistor is connected to the first port of the capacitor, and the second port of the capacitor is connected to ground;

    The drain of the second field effect transistor is connected to the first port of the capacitor, the source of the second field effect transistor is connected to the first port of the first resistor, and the second port of the first resistor is connected to the first port of the first resistor. Port ground;

    The drain of the third field effect transistor is connected to the first port of the capacitor, the source of the third field effect transistor is connected to the first port of the second resistor, and the second port of the second resistor is connected to the first port of the second resistor. The port is grounded.
13. The chip according to claim 12, wherein the first resistor is an adjustable resistor, and the adjustable resistor includes a plurality of gears.
14. The chip according to any one of claims 11 to 13, characterized in that the chip further includes a comparator and an output circuit, and the output circuit includes a D flip-flop, a delay circuit and a control circuit,

    The first input terminal of the comparator is connected to the output terminal of the integrating circuit, and the second input terminal of the comparator is used to obtain a reference voltage;

    The input terminal of the delay circuit is connected to the output terminal of the comparator, and the output terminal of the delay circuit is connected to the first input terminal of the control circuit;

    The second input terminal of the control circuit is used to obtain a control signal, the first output terminal of the control circuit is connected to the second input terminal of the integrating circuit, and the second output terminal of the control circuit is connected to the D trigger Connect to the reset port of the device;

    The clock port of the D flip-flop is connected to the output terminal of the comparator.
15. A chip, characterized in that the chip includes a logic circuit and an interface circuit, the logic circuit is coupled with the interface circuit, the interface circuit includes a pulse detection circuit and an integrating circuit, wherein,

    The input end of the pulse detection circuit is used to obtain an input signal, and the input signal corresponds to the input data signal of the C-port physical layer C-PHY protocol;

    The first input terminal of the integrating circuit is connected to the output terminal of the pulse detection circuit.
16. The chip according to claim 15, wherein the integrating circuit includes: a first field effect transistor, a second field effect transistor, a third field effect transistor, a first resistor, a second resistor and a capacitor,

    The gates of the first field effect transistor and the second field effect transistor are connected to the first input end of the integrating circuit, and the gate electrode of the third field effect transistor is connected to the second input end of the integrating circuit. connected, the first port of the capacitor is connected to the output end of the integrating circuit,

    The source of the first field effect transistor is connected to the first port of the capacitor, and the second port of the capacitor is connected to ground;

    The drain of the second field effect transistor is connected to the first port of the capacitor, the source of the second field effect transistor is connected to the first port of the first resistor, and the second port of the first resistor is connected to the first port of the first resistor. Port ground;

    The drain of the third field effect transistor is connected to the first port of the capacitor, the source of the third field effect transistor is connected to the first port of the second resistor, and the second port of the second resistor is connected to the first port of the second resistor. The port is grounded.
17. The chip according to claim 16, wherein the first resistor is an adjustable resistor, and the adjustable resistor includes a plurality of gears.
18. The chip according to any one of claims 15 to 17, characterized in that the chip further includes a comparator and an output circuit, and the output circuit includes a D flip-flop, a delay circuit and a control circuit,

    The first input terminal of the comparator is connected to the output terminal of the integrating circuit, and the second input terminal of the comparator is used to obtain a reference voltage;

    The input terminal of the delay circuit is connected to the output terminal of the comparator, and the output terminal of the delay circuit is connected to the first input terminal of the control circuit;

    The second input terminal of the control circuit is used to obtain a control signal, the first output terminal of the control circuit is connected to the second input terminal of the integrating circuit, and the second output terminal of the control circuit is connected to the D trigger Connect to the reset port of the device;

    The clock port of the D flip-flop is connected to the output terminal of the comparator.
19. A computer device, characterized in that the computer device includes a printed circuit board and the chip according to any one of claims 1 to 18, and the chip is fixed on the printed circuit board.