CN117200577A - Voltage converter circuit, control method thereof and radio frequency switch - Google Patents

Abstract

The application discloses a voltage converter circuit, a control method thereof and a radio frequency switch, which can improve the voltage resistance of a radio frequency switch chip, ensure the reliable work of the radio frequency switch and simultaneously can meet the miniaturization requirement of the radio frequency switch.

Description

Voltage converter circuit, control method thereof and radio frequency switch

Technical Field

The application relates to the technical field of radio frequency switches, in particular to a voltage converter circuit, a control method thereof and a radio frequency switch.

Background

With the high-speed development of mobile communication technology, mobile phones, computers and the like have higher requirements on the performance of radio frequency switches, the radio frequency is a key component of wireless products, the radio frequency switches comprise radio frequency switch chips, and radio frequency switches, amplifiers, diplexers, radio frequency filters and the like are distributed on substrates of the chips, wherein the radio frequency switches are used for realizing the switching of the receiving and transmitting of radio frequency signals, the amplifiers are used for realizing the amplification of the radio frequency signals of a receiving channel or a transmitting channel, and the radio frequency filters are used for filtering signals outside a specific frequency band. The band-gap reference voltage circuit is arranged in the radio frequency switch chip, and is used as a general base module of the radio frequency switch chip, and the requirement of a wide voltage range of 2.5V-5V is required to be met.

At present, in a radio frequency front-end WIFI switch chip, an internal bias voltage of a radio frequency switch based on a GPIO interface is generally provided by a voltage source VDD and a control voltage VCTRL, as shown in fig. 1, the voltage source VDD is converted into the internal bias voltage by a voltage converter, the control voltage VCTRL is converted into the internal control voltage by a level converter, and in the radio frequency switch chip in common use at present, the voltage converter includes a bandgap reference voltage circuit, an LDO circuit, a MOS tube, and the like, the working voltage of the bandgap reference voltage circuit and the LDO circuit is 2.5V-5V, the rated voltage of the MOS tube is 2.5V, for an application occasion such as a base station with a 5V voltage requirement, the voltage endurance of the MOS tube is poor, and is very easy to be damaged due to exceeding the rated working voltage of the MOS tube, if the 5V voltage requirement is to be met, the voltage endurance effect is improved, at least two MOS tubes need to be stacked in the voltage converter, and in order to obtain the same current conducting capability, the complexity of the MOS tube and the complexity of the radio frequency switch chip are increased, and the size of the radio frequency switch chip cannot be doubled.

Disclosure of Invention

In view of the above problems in the prior art, the present application provides a voltage converter circuit, which can improve the voltage resistance of a radio frequency switch chip, ensure the reliable operation of the radio frequency switch chip, and meet the miniaturization requirement of the radio frequency switch.

In order to achieve the above purpose, the application adopts the following technical scheme:

the voltage converter circuit comprises a band gap reference voltage circuit, a first LDO circuit and a second LDO circuit, and is characterized by further comprising a first voltage dividing unit, a second voltage dividing unit connected in series with the first voltage dividing unit, a first switch unit and a second switch unit which are connected in parallel, wherein the input ends of the first voltage dividing unit, the first switch unit and the second switch unit are all connected with a voltage source VDD, the output end of the first voltage dividing unit is respectively connected with the input end of the second voltage dividing unit, the control ends of the first switch unit and the second switch unit, the output end of the first switch unit is respectively connected with the input end of the band gap reference voltage circuit and the input end of the first LDO circuit, the output end of the second switch unit is respectively connected with the input end of the second LDO circuit, the first voltage dividing unit comprises a resistor R1, the second voltage dividing unit comprises a plurality of diodes connected in series, and the first switch unit and the second switch unit both comprise MOS transistors.

It is further characterized in that,

the second voltage division unit comprises four diodes D1-D4 which are sequentially connected in series;

the first switch unit comprises an MOS tube N1, the second switch unit comprises an MOS tube N2, and the MOS tubes N1 and N2 are NMOS tubes;

the circuit further comprises a filtering unit, wherein the filtering unit comprises resistors R2 and R3, one ends of the resistors R2 and R3 are connected with the voltage source VDD, the other end of the resistor R2 is connected with the input end of the first switch unit, and the other end of the resistor R3 is connected with the input end of the second switch unit;

further, one ends of the resistors R1, R2 and R3 are connected to the voltage source VDD and the first input end of the first LDO circuit, the other ends of the resistors R2 and R3 are respectively connected in series with the sources of the MOS transistors N1 and N2, the other ends of the resistor R1 are respectively connected to the gates of the MOS transistors N1 and N2 and the anode of the diode D1, the drain electrode of the MOS transistor N1 outputs the bias voltage vreg_ana and is respectively connected to the input end of the bandgap reference voltage circuit and the second input end of the first LDO circuit, the drain electrode of the MOS transistor N2 outputs the bias voltage vreg_dig and is connected to the first input end of the second LDO circuit, and the output end of the bandgap reference voltage circuit includes: the first output end is connected with the first LDO circuit, the second LDO circuit is provided with the reference voltage Vref, the second output end is connected with the first LDO circuit, the first LDO circuit is provided with the bias current Ib1, the third output end is connected with the second LDO circuit, the bias current Ib2 is provided for the second LDO circuit, and the cathode of the diode D4, the fourth output end of the band gap reference voltage circuit, the output end of the first LDO circuit and the output end of the second LDO circuit are all grounded;

further, the voltage source VDD is a high voltage, the high voltage is 5V, and the working voltages of the MOS transistors N1 and N2 are respectively 1/2×vdd;

further, the resistance value of the resistor R1 is 500 kilo ohms, and the resistance values of the resistors R2 and R3 are 1 kilo ohms to 2 kilo ohms.

A method of controlling a voltage converter circuit, the method comprising: s1, a starting voltage source VDD supplies power, MOS tubes in a first switch unit and a second switch unit are conducted, and starting voltage and starting current are provided for the band gap reference voltage circuit;

s2, the band gap reference voltage circuit generates reference voltage Vref and bias currents Ib1 and Ib2, the first LDO circuit is started under the action of the reference voltage Vref and the bias current Ib1 and outputs bias voltage Vreg_ana, the second LDO circuit is started under the action of the reference voltage Vref and the bias current Ib1 and outputs bias voltage Vreg_dig, at the moment, MOS (metal oxide semiconductor) tubes in the first switch unit and the second switch unit are cut off, the band gap reference voltage circuit and the first LDO circuit form a first conduction loop, and the band gap reference voltage circuit and the second LDO circuit form a second conduction loop;

s3, closing the band gap reference voltage circuit, and restarting the MOS transistors N1 and N2.

The radio frequency switch comprises a shell and a radio frequency switch chip packaged in the shell, wherein the radio frequency switch chip comprises a substrate, a voltage converter circuit, a level converter, an oscillator, a negative pressure generating circuit, a driving stage and a radio frequency switch, wherein the voltage converter circuit, the level converter circuit, the oscillator and the negative pressure generating circuit are distributed in the substrate, the input end of the voltage converter circuit is connected with a voltage source VDD, the output end of the voltage converter circuit is respectively connected with the level converter, the oscillator, the negative pressure generating circuit and the driving stage, the voltage converter circuit is used for converting the voltage source VDD into bias voltages Vreg_ana and Vreg_dig, the bias voltages Vreg_dig are respectively provided for the level converter and the driving stage, the control voltage VCTRL is input to the input end of the level converter, the level converter is used for converting the control voltage VCTRL, a control voltage signal BS is output for controlling the driving stage, the oscillator and the negative pressure generating circuit is used for generating a reference voltage Vneg, the driving stage is provided with the reference voltage Vreg, the driving stage is provided with the bias voltage Vreg, the control voltage Vneg is converted into the control voltage Vneg under the action of the control voltage or the control voltage converting circuit, and the switching circuit is turned on the radio frequency switch.

The structure of the application has the advantages that the voltage converter circuit is provided with the first voltage dividing unit and the second voltage dividing unit, the first voltage dividing unit comprises the resistor R1, the second voltage dividing unit comprises a plurality of diodes connected in series, the voltage source VDD is divided by the first voltage dividing unit and the second voltage dividing unit to obtain the reference voltage V, and the reference voltage V is added to the control ends of the first switch unit and the second switch unit, so that the voltage difference between the control ends and the input ends of the first switch unit and the second switch unit is reduced, and the problem that the first switch unit and the second switch unit are damaged due to poor voltage resistance is avoided. And the same current conduction capacity is obtained without increasing the size and the structure of MOS (metal oxide semiconductor) tubes in the first switch unit and the second switch unit, so that the structure design is simple, and the area of the voltage converter is reduced.

After the voltage converter circuit is applied to the radio frequency switch, the area of the voltage converter is greatly reduced after the voltage converter circuit structure is adopted, so that the occupied area of the voltage converter in the radio frequency switch chip is reduced, the structure of the radio frequency switch chip is simplified, the reliable work of the radio frequency switch chip is ensured, and the miniaturization requirement of the radio frequency switch is met.

Drawings

FIG. 1 is a block diagram of a conventional RF switch chip;

FIG. 2 is a block diagram of a voltage converter in a conventional RF switch chip;

FIG. 3 is a schematic circuit diagram of an LDO circuit in a conventional voltage converter;

fig. 4 is a schematic circuit diagram of the MOS transistor of fig. 2 replaced with at least two stacked MOS transistors;

FIG. 5 is a schematic circuit diagram of a RF switch chip of the present application;

FIG. 6 is a simulation diagram of the bias voltages Vreg_ana, vreg_dig and the reference voltage Vneg generated by the voltage converter circuit of the present application.

Detailed Description

For a better understanding of the present application, the technical solutions in the embodiments of the present application will be clearly and fully described below with reference to the accompanying drawings in which it is to be noted that the terms "comprising" and "having" and any variations thereof in the description and claims of the present application and in the above drawings are intended to cover a non-exclusive inclusion, such as a process, method, apparatus, product or device comprising a series of steps or units, not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products or devices.

At present, in a radio frequency switch chip, as shown in fig. 1, an external power supply voltage VDD is mainly converted into two sets of internal bias voltages vreg_ana and vreg_dig by a voltage converter, and the two sets of voltages are lower than 3V, so as to meet the 2.5V safe operating voltage requirement of a MOS tube specified by the national standard. In addition, the high level of the external control voltage signal VCTRL is generally 1.6V-3.6V, and the external control voltage signal VCTRL is also converted into the internal voltage control signal BS through a level converter, wherein the high level of BS is equal to vreg_ana, and the bias voltage vreg_dig supplies power to the oscillator and the negative voltage generating circuit to generate the negative voltage circuit Vneg, and the driving stage for driving the radio frequency switch to be turned on or off is jointly powered by vreg_ana and Vneg to convert the control signal BS into the actual bias voltages Vg1, vg2, vb1, vb2 of the radio frequency switch stage.

Referring to fig. 2, the conventional voltage converter mainly includes a band gap reference voltage circuit (band gap) and an LDO circuit (LDO) connected in sequence, wherein the input ends of the band gap reference voltage circuit (band gap) and the LDO circuit (LDO) are connected with a voltage source VDD, the band gap reference voltage circuit (band gap) is used for generating a reference voltage Vref and providing the reference voltage Vref to the LDO circuit (LDO), the output end of the LDO circuit (LDO) outputs a voltage Vout, and the band gap reference voltage circuit (band gap) and the LDO circuit (LDO) are all operated under VDD (2.5V-5V). Referring to fig. 3, the LDO circuit generally used at present mainly includes an amplifier OPA, a MOS transistor M1, and resistors R1 and R2, the voltage sources of the amplifier OPA and the MOS transistor M1 are VDD, the high voltage of VDD is usually 2.5V to 5V, and the MOS transistor M1 adopts the SOI technology of a 2.5V voltage withstanding device, but when VDD is high voltage 5V, the MOS transistor M1 is easily damaged due to poor voltage withstanding, thereby affecting the reliability of the operation of the whole radio frequency switch chip.

Taking an output power tube PMOS tube M1 of the LDO circuit as an example, when VDD=5V and Vout=2.5V, the output power tube PMOS works in a normal tolerance range; when the whole radio frequency switch chip works in a closed state, the LDO circuit is closed to stop working, at the moment, VDD=5V, vout=0V, the working voltage of the output power tube PMOS M1 is 5V, and the working voltage exceeds the normal voltage range (the normal working rated voltage is 2.5V), so that the device is damaged. The traditional way of solving the problem that the MOS transistor devices are damaged due to poor voltage resistance is to stack a plurality of MOS transistors, see FIG. 3, split an output power transistor PMOS M1 into two PMOS transistors M2 and M3, wherein Vgate is connected with the output end of an LDO operational amplifier OPA, and VMID is equal to VDD/2. When the radio frequency switch chip works in the off state, the drain electrode of the PMOS tube M2 and the source electrode of the PMOS tube M3 are about VDD/2, so that the working voltages of the PMOS tubes M2 and M3 are VDD/2, and even if VDD is as high as 5V, the PMOS tubes M2 and M3 work in the normal voltage range.

However, after the PMOS transistor M1 is split into the stacked structure of the two PMOS transistors M2 and M3, in order to obtain the same current conducting capability, the sizes of the PMOS transistors M2 and M3 are respectively twice as large as that of the PMOS transistor M1, so that the area of the radio frequency switch chip is increased by 4 times, and similar high-voltage processing modes of the stacked circuit of devices are all shown in the operational amplifier of the bandgap reference voltage circuit and the LDO circuit, so that the structural complexity of the whole radio frequency switch chip circuit is greatly improved, and more chip area is occupied.

Aiming at the problems that the MOS tube in the radio frequency switch chip has poor pressure resistance, the structure complexity of the whole radio frequency switch chip circuit is improved by stacking two PMOS tubes to improve the pressure resistance of the radio frequency switch chip, more chip area is occupied, and the miniaturization requirement of the radio frequency switch chip cannot be met, the application provides a specific embodiment of a voltage converter circuit and a radio frequency switch, which is shown in figure 4, wherein the voltage converter circuit comprises a band gap reference voltage circuit 1, a first LDO (LDO_ana) 2, a second LDO (LDO_dig) 3, a first voltage division unit 4, a second voltage division unit 5 connected in series with the first voltage division unit 4, a first switch unit 6 connected in parallel and a second switch unit 7, the input ends of the first voltage dividing unit 4, the first switching unit 6 and the second switching unit 7 are all connected with a voltage source VDD, the output end of the first voltage dividing unit 4 is respectively connected with the input end of the second voltage dividing unit 7, the control ends of the first switching unit 6 and the second switching unit 7, the output end of the first switching unit 6 is respectively connected with the input end of the band-gap reference voltage circuit 1 and the input end of the first LDO circuit 2, the output end of the second switching unit 7 is connected with the input end of the second LDO circuit 3, the output end of the band-gap reference voltage circuit 1 is respectively connected with the first LDO circuit 2 and the second LDO circuit 3, the first voltage dividing unit 4 comprises a resistor R1, the second voltage dividing unit 5 comprises a plurality of diodes which are connected in series, and the first switching unit 6 and the second switching unit 7 are all composed of MOS tubes.

In this embodiment, the second voltage division unit 5 includes four diodes D1 to D4 connected in series in sequence, the first switch unit 6 includes a MOS transistor N1, the second switch unit 7 includes a MOS transistor N2, and the MOS transistors N1 and N2 are NMOS transistors.

The voltage converter circuit further comprises a filtering unit 8, the filtering unit 8 comprises resistors R2 and R3, a voltage source VDD is connected with the input end of the first switching unit 6 through the resistor R2, and the voltage source VDD is connected with the input end of the second switching unit 7 through the resistor R3.

Referring to fig. 4, the specific circuit structure of the voltage converter circuit is: one ends of the resistors R1, R2 and R3 are respectively connected with a voltage source VDD and a first input end of a first LDO circuit, the other ends of the resistors R2 and R3 are respectively connected with sources of MOS tubes N1 and N2 in series, the other ends of the resistor R1 are respectively connected with grids of the MOS tubes N1 and N2 and anodes of a diode D1, a drain electrode of the MOS tube N1 outputs bias voltage Vreg_ana and is respectively connected with an input end of a band gap reference voltage circuit and a second input end of the first LDO circuit, a drain electrode of the MOS tube N2 outputs bias voltage Vreg_dig and is connected with a first input end of a second LDO circuit, and an output end of the band gap reference voltage circuit comprises: the first output end is connected with the first LDO circuit and the second LDO circuit to provide the reference voltage Vref for the first LDO circuit, the second output end is connected with the first LDO circuit to provide the bias current Ib1 for the first LDO circuit, the third output end is connected with the second LDO circuit to provide the bias current Ib2 for the second LDO circuit, and the cathode of the diode D4, the fourth output end of the band gap reference voltage circuit, the output end of the first LDO circuit and the output end of the second LDO circuit are all grounded.

The voltage converter circuit is applied to a radio frequency switch, the radio frequency switch comprises a shell, a radio frequency switch chip packaged in the shell, the radio frequency switch chip comprises a substrate, a voltage converter circuit, a level converter, an oscillator, a negative pressure generating circuit, a driving stage and a radio frequency switch, wherein the voltage converter circuit, the level converter, the oscillator and the negative pressure generating circuit are distributed on the substrate, the input end of the voltage converter circuit is connected with a voltage source VDD, the output end of the voltage converter circuit is respectively connected with the level converter, the oscillator, the negative pressure generating circuit and the driving stage, the voltage converter circuit is used for converting the voltage source VDD into bias voltages Vreg_ana and Vreg_dig, the bias voltages Vreg_dig are respectively provided for the level converter and the driving stage, the control voltage VCTRL is input to the input end of the level converter, the level converter is used for converting the control voltage VCTRL, the control voltage signal BS is output to control the driving stage, the oscillator and the negative pressure generating circuit is used for generating a reference voltage Vneg, the reference voltage neg is provided for the driving stage, the driving stage is used for generating the reference voltage neg, the driving stage is turned on or the voltage converting circuit is turned off under the action of the control voltage signal BS and the reference voltage neg, and the voltage neg is turned on in a control circuit to be shown in a control case of a voltage converter V4.

In this embodiment, the voltage source VDD is 5v, and the working voltages of the mos transistors N1 and N2 are respectively 1/2×vdd; the resistance value of the resistor R1 is 500 kiloohms, the resistance values of the resistors R2 and R3 are 1 kiloohms-2 kiloohms, the resistance value of the resistor R1 is larger, the resistor R1 is used for dividing the voltage source VDD, the resistance values of the resistors R2 and R3 are smaller, the resistor R2 and R3 are used for filtering noise in the voltage source VDD, and the static electricity release capacity of the radio frequency switch chip is improved, so that the working stability of the radio frequency switch chip is further improved.

The working principle of the voltage converter circuit is as follows: s1, a starting voltage source VDD supplies power, a MOS tube N1 in a first switch unit 6 is conducted, starting voltage and starting current are provided for a band-gap reference voltage circuit 1, and the band-gap reference voltage circuit 1 starts to start. The gate voltage of the MOS transistor N1 is a voltage between the first voltage dividing unit and the second voltage dividing unit, where the voltage is obtained by dividing the voltage source VDD by the first voltage dividing unit and the second voltage dividing unit, the second voltage dividing unit includes four diodes D1 to D4 connected in series, and if the conduction voltage drop of a single diode is 0.7V, the conduction voltage drop of the four diodes D1 to D4 connected in series is 2.8V, and the voltage is the reference voltage V, and at this time, the gate-source voltage Vgs1 of the MOS transistor N1 is about 2.8V. The threshold voltages Vth of the MOS transistors N1 and N2 are both 0.4V, the bias voltage vreg_ana=2.8v-0.4v=2.4v, and the rated operating voltage of the MOS transistors N1 and N2 is 2.5V, so that the bias voltage vreg_ana is smaller than the rated operating voltage, and similarly, the bias voltage vreg_dig is calculated and obtained to be 2.4V, and the bias voltage vreg_dig is smaller than the rated operating voltage, thereby avoiding the problem of damage caused by poor voltage resistance of the MOS transistors N1 and N2. At this point the bandgap reference voltage circuit 1 starts to start.

S2, the band gap reference voltage circuit 1 generates a reference voltage Vref and bias currents Ib1 and Ib2, and provides the reference voltage Vref and the bias currents Ib1 and Ib2 for the first LDO circuit 2 and the second LDO circuit 3 respectively, the first LDO circuit is started under the action of the reference voltage Vref and the bias current Ib1 and outputs a bias voltage Vreg_ana, the second LDO circuit is started under the action of the reference voltage Vref and the bias current Ib1 and outputs a bias voltage Vreg_dig, and at the moment, the gate-source voltages Vgs2 of MOS tubes N1 and N2 in the first switch unit and the second switch unit are differences between the bias voltages Vreg_ana and Vgs 1: 2.4v_2.8v= -0.4v, therefore Vgs 2-vth= -0.4-0.4= -0.8v <0, thereby turning off the MOS transistors N1, N2, at this time, the bandgap reference voltage circuit and the first LDO circuit form a first conduction loop, the bandgap reference voltage circuit and the second LDO circuit form a second conduction loop, and the bandgap reference voltage circuit 1 is established to a steady state, thereby providing reliable bias voltages vreg_ana, vreg_dig for subsequent circuits.

S3, closing the band-gap reference voltage circuit, and restarting the MOS transistors N1 and N2.

Fig. 6 shows a simulation diagram of the bias voltages vreg_ana, vreg_dig and the reference voltage Vneg generated by the voltage converter under the control of the clock signal CLK, and the horizontal axis in fig. 6 represents time (time), and the vertical axis represents the bias voltages vreg_dig, vreg_ana, the clock signal CLK and the reference voltage Vneg, respectively, as can be seen from fig. 6, in the initial stage of power supply of the start voltage source VDD, the bias voltages vreg_dig and vreg_ana gradually rise with the clock signal CLK under the control of the clock signal CLK, and the bandgap reference voltage circuit 1 starts and builds up to a steady state, that is, step S1; when the first conduction loop and the second conduction loop are formed after 85 microseconds, the band-gap reference voltage circuit 1 is built to a steady state, the reference voltage Vneg is gradually converted into about 2.5V, and the band-gap reference voltage circuit 1 is built to the steady state, so that reliable bias voltages Vreg_ana and Vreg_dig are provided for subsequent circuits.

The structure and the method have the following advantages:

(1) The voltage converter circuit in the radio frequency switch chip can meet the high voltage conversion requirement without stacking a plurality of MOS tube devices with large-size structures, thereby simplifying the circuit complexity, improving the working reliability and saving the chip area.

(2) Compared with the existing mode that the voltage source VDD directly supplies power to the band gap reference voltage circuit, the voltage converter circuit mainly comprises the first LDO circuit and the second LDO circuit which supply bias voltages Vreg_ana and Vreg_dig to the band gap reference voltage circuit, and the bias voltages Vreg_ana and Vreg_dig are obtained by dividing the voltage source VDD, so that the voltage value is smaller than the voltage source VDD, the power supply rejection ratio of the radio frequency switch chip is improved, the improvement of the power supply rejection ratio is beneficial to suppressing noise in output voltage, and the stability and reliability of the work of the radio frequency switch chip are further improved.

The reference voltage V is obtained through the voltage division of the first voltage division circuit and the second voltage division circuit and is applied to the grid electrodes of the MOS tubes N1 and N2, so that the working voltages of the MOS tubes N1 and N2 are as follows: 2.8V-0.4v=2.4v, the operating voltage is lower than rated operating voltage 2.5V, so the arrangement of the first voltage dividing circuit and the second voltage dividing circuit ensures that the MOS transistors N1 and N2 operate within a normal operating voltage range, and the MOS transistors N1 and N2 are prevented from being damaged due to exceeding the rated operating voltage by 2.5V.

(3) The dimensions of the MOS transistors N1 and N2 are smaller than those of the PMOS transistors M1, M2 and M3 shown in FIG. 3, so that the whole chip area is saved. In addition, the detection shows that when the band gap reference voltage circuit is in a closed state, the leakage current of the whole voltage converter circuit is less than or equal to 5uA, and the design requirement of the radio frequency switch chip is met.

The above is only a preferred embodiment of the present application, and the present application is not limited to the above examples. It is to be understood that other modifications and variations which may be directly derived or contemplated by those skilled in the art without departing from the spirit and concepts of the present application are deemed to be included within the scope of the present application.

Claims (9)

1. The voltage converter circuit comprises a band gap reference voltage circuit, a first LDO circuit and a second LDO circuit, and is characterized by further comprising a first voltage dividing unit, a second voltage dividing unit connected in series with the first voltage dividing unit, a first switch unit and a second switch unit which are connected in parallel, wherein the input ends of the first voltage dividing unit, the first switch unit and the second switch unit are all connected with a voltage source VDD, the output end of the first voltage dividing unit is respectively connected with the input end of the second voltage dividing unit, the control ends of the first switch unit and the second switch unit, the output end of the first switch unit is respectively connected with the input end of the band gap reference voltage circuit and the input end of the first LDO circuit, the output end of the second switch unit is respectively connected with the input end of the second LDO circuit, the first voltage dividing unit comprises a resistor R1, the second voltage dividing unit comprises a plurality of diodes connected in series, and the first switch unit and the second switch unit both comprise MOS transistors.

2. The voltage converter circuit according to claim 1, wherein the second voltage dividing unit includes four diodes D1 to D4 connected in series in sequence.

3. The voltage converter circuit of claim 2, wherein the first switching unit comprises a MOS transistor N1, the second switching unit comprises a MOS transistor N2, and both MOS transistors N1, N2 are NMOS transistors.

4. A voltage converter circuit according to claim 3, further comprising a filter unit comprising resistors R2, R3, the voltage source VDD being connected to the first switching unit input via the resistor R2, the voltage source VDD being connected to the second switching unit input via the resistor R3.

5. The voltage converter circuit of claim 4, wherein one ends of the resistors R1, R2 and R3 are connected to a voltage source VDD and a first input end of a first LDO circuit, the other end of the resistor R2 is connected in series to a source of the MOS transistor N1, the other end of the resistor R3 is connected in series to a source of the MOS transistor N2, the other ends of the resistor R1 are respectively connected to gates of the MOS transistors N1 and N2 and anodes of a diode D1, a drain of the MOS transistor N1 outputs a bias voltage vreg_ana and is respectively connected to an input end of the bandgap reference voltage circuit and a second input end of the first LDO circuit, a drain of the MOS transistor N2 outputs a bias voltage vreg_dig and is connected to a first input end of the second LDO circuit, and an output end of the bandgap reference voltage circuit comprises: the first output end is connected with the first LDO circuit, the second LDO circuit is provided with the reference voltage Vref, the second output end is connected with the first LDO circuit, the first LDO circuit is provided with the bias current Ib1, the third output end is connected with the second LDO circuit, the bias current Ib2 is provided for the second LDO circuit, and the cathode of the diode D4, the fourth output end of the band gap reference voltage circuit, the output end of the first LDO circuit and the output end of the second LDO circuit are all grounded.

6. The voltage converter circuit of claim 1 or 5, wherein the voltage source VDD is a high voltage, the high voltage is 5V, and the operating voltages of the MOS transistors N1, N2 are respectively 1/2 x VDD.

7. The voltage converter circuit of claim 6, wherein the resistance of the resistor R1 is 500 kilo-ohms and the resistances of the resistors R2 and R3 are each 1 kilo-ohms to 2 kilo-ohms.

8. A voltage converter circuit control method for controlling the voltage converter circuit of claim 1 or 7, characterized in that the method comprises: s1, a starting voltage source VDD supplies power, MOS tubes in a first switch unit and a second switch unit are conducted, and starting voltage and starting current are provided for the band gap reference voltage circuit;

s2, the band gap reference voltage circuit generates reference voltage Vref and bias currents Ib1 and Ib2, the first LDO circuit is started under the action of the reference voltage Vref and the bias current Ib1 and outputs bias voltage Vreg_ana, the second LDO circuit is started under the action of the reference voltage Vref and the bias current Ib1 and outputs bias voltage Vreg_dig, at the moment, MOS (metal oxide semiconductor) tubes in the first switch unit and the second switch unit are cut off, the band gap reference voltage circuit and the first LDO circuit form a first conduction loop, and the band gap reference voltage circuit and the second LDO circuit form a second conduction loop;

s3, closing the band gap reference voltage circuit, and restarting the MOS transistors N1 and N2.

9. The radio frequency switch comprises a shell and a radio frequency switch chip packaged in the shell, wherein the radio frequency switch chip comprises a substrate, a voltage converter circuit, a level converter, an oscillator, a negative pressure generating circuit, a driving stage and a radio frequency switch, wherein the voltage converter circuit is distributed in the substrate, the input end of the voltage converter circuit is connected with a voltage source VDD, the output end of the voltage converter circuit is respectively connected with the level converter, the oscillator, the negative pressure generating circuit and the driving stage, the voltage converter circuit is used for converting the voltage source VDD into bias voltages Vreg_ana and Vreg_dig, the bias voltages Vreg_ang are respectively provided for the level converter and the driving stage, the bias voltages Vreg_dig are provided for the oscillator and the negative pressure generating circuit, the control voltage VCTRL is input to the input end of the level converter, the level converter is used for converting the control voltage VCTRL, the driving stage is controlled by outputting a control voltage signal BS, the oscillator and the negative pressure generating circuit is used for generating a reference voltage Vneg, the driving stage is provided with the reference voltage Vrneg, the driving stage is provided with the bias voltage Vreg, the control voltage Vneg is required to be turned off, and the voltage converter is turned off or the driving circuit is required to switch the voltage is turned on by the voltage converter circuit with the voltage conversion circuit of voltage or the voltage conversion circuit of the voltage 7.