CN117174595A - 用于制造半导体器件的方法 - Google Patents

用于制造半导体器件的方法 Download PDF

Info

Publication number
CN117174595A
CN117174595A CN202210593487.3A CN202210593487A CN117174595A CN 117174595 A CN117174595 A CN 117174595A CN 202210593487 A CN202210593487 A CN 202210593487A CN 117174595 A CN117174595 A CN 117174595A
Authority
CN
China
Prior art keywords
ultraviolet
substrate
composite tape
transparent
stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210593487.3A
Other languages
English (en)
Inventor
李建赫
张有晶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stats Chippac Pte Ltd
Original Assignee
Stats Chippac Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Pte Ltd filed Critical Stats Chippac Pte Ltd
Priority to CN202210593487.3A priority Critical patent/CN117174595A/zh
Priority to US18/317,093 priority patent/US20230386888A1/en
Priority to KR1020230063867A priority patent/KR20230165706A/ko
Priority to TW112119075A priority patent/TW202401515A/zh
Publication of CN117174595A publication Critical patent/CN117174595A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/786Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being other than a semiconductor body, e.g. insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Dicing (AREA)
  • Die Bonding (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)

Abstract

本申请提供一种用于制造半导体器件的方法。所述方法包括:将具有多个电子元件的基底附接至复合胶带上,复合胶带具有对紫外辐射敏感的粘合层以及可透紫外线的基膜,其中基底被附接至复合胶带的粘合层;将基底和复合胶带放置在可透紫外线的载台上,其中可透紫外线的载台与复合胶带的可透紫外线的基膜接触;将基底切割为多个半导体器件,其中每个半导体器件具有多个电子元件中的一个电子元件;将屏蔽材料沉积在多个半导体器件上,以在多个半导体器件中的每一个半导体器件上形成屏蔽层;透过可透紫外线的载台向复合胶带照射紫外辐射,以降低粘合层的粘性;以及将多个半导体器件从可透紫外线的载台上分离。

Description

用于制造半导体器件的方法
技术领域
本申请总体上涉及半导体技术,更具体地,涉及用于制造半导体器件的方法。
背景技术
对于电子产品中的电子元件,需要进行电磁干扰(EMI)屏蔽来避免电磁场、静电场等干扰影响电子元件的工作。通常地,可以用一个金属盖或者一个均质涂布层覆盖于半导体封装的外围来作为屏蔽层。然而,现有的电磁屏蔽工艺仅能够逐个地为半导体封装形成屏蔽层,因此其生产率较低。
因此,需要提供一种为半导体封装形成屏蔽层的改进方法。
发明内容
本申请的目的是提供一种生产效率较高的为半导体封装形成屏蔽层的方法。
根据本申请的一个方面,公开了一种用于制造半导体器件的方法,所述方法包括:将具有多个电子元件的基底附接至复合胶带上,所述复合胶带具有对紫外辐射敏感的粘合层以及可透紫外线的基膜,其中所述基底被附接至所述复合胶带的所述粘合层;将所述基底和所述复合胶带放置在可透紫外线的载台上,其中所述可透紫外线的载台与所述复合胶带的所述可透紫外线的基膜接触;将所述基底切割为多个半导体器件,其中每个半导体器件具有所述多个电子元件中的一个电子元件;将屏蔽材料沉积在所述多个半导体器件上,以在所述多个半导体器件中的每一个半导体器件上形成屏蔽层;透过所述可透紫外线的载台向所述复合胶带照射紫外辐射,以降低所述粘合层的粘性;以及将所述多个半导体器件从所述可透紫外线的载台上分离。
根据本申请的另一个方面,公开了一种用于制造半导体器件的方法,所述方法包括:将具有多个电子元件的基底附接至复合胶带上,所述复合胶带具有对紫外辐射敏感的粘合层以及可透紫外线的基膜,其中所述基底被附接至所述复合胶带的所述粘合层;将所述基底和所述复合胶带放置在可透紫外线的载台上,其中所述可透紫外线的载台与所述复合胶带的所述可透紫外线的基膜接触;将屏蔽材料沉积在所述基底上;将所述基底切割为多个半导体器件,其中每个半导体器件具有所述多个电子元件中的一个电子元件;透过所述可透紫外线的载台向所述复合胶带照射紫外辐射,以降低所述粘合层的粘性;以及将所述多个半导体器件从所述可透紫外线的载台上分离。
应当理解,前面的一般性描述和下面的详细描述都只是示例性和说明性的,而不是对本发明的限制。此外,并入并构成本说明书一部分的附图示出了本发明的实施例并且与说明书一起用于解释本发明的原理。
附图说明
本文引用的附图构成说明书的一部分。除非另有明确说明,附图中所示的特征仅示出了本申请的一些实施例而不是本申请的所有实施例,说明书的读者不应做出相反的暗示。
图1A至1I示出了根据本申请一个实施例的用于制造半导体器件的方法过程的截面示意图;
图2A-2E示出根据本申请一个实施例的用于制造半导体器件的另一方法过程的截面示意图;
图3示出了根据本申请一个实施例的用于制造半导体器件的方法的流程图;
图4示出了根据本申请另一实施例的用于制造半导体器件的方法的流程图。
在整个附图中将使用相同的附图标记来表示相同或相似的部分。
具体实施方式
以下本申请的示例性实施例的详细描述参考了构成描述的一部分的附图。附图示出了其中可以实践本申请的具体示例性实施例。包括附图在内的详细描述足够详细地描述了这些实施例,以使本领域技术人员能够实践本申请。本领域技术人员可以进一步利用本申请的其他实施例,并在不脱离本申请的精神或范围的情况下进行逻辑、机械等变化。因此,以下详细描述的读者不应以限制性的方式解释该描述,并且仅以所附权利要求限定本申请的实施例的范围。
在本申请中,除非另有明确说明,否则使用的单数包括了复数。在本申请中,除非另有说明,否则使用“或”是指“和/或”。此外,使用的术语“包括”以及诸如“包含”和“含有”的其他形式不是限制性的。此外,除非另有明确说明,诸如“元件”或“组件”之类的术语覆盖了包括一个单元的元件和组件,以及包括多于一个子单元的元件和组件。此外,本文使用的章节标题仅用于组织目的,不应解释为限制所描述的主题。
如本文所用,空间上相对的术语,例如“下方”、“下面”、“上方”、“上面”、“上”、“上侧”、“下侧”、“左侧”、“右侧”、“水平”、“竖直”等等,可以在本文中使用,以便于描述如附图中所示的一个元件或特征与另一元件或特征的关系。除了图中描绘的方向之外,空间相对术语旨在涵盖设备在使用或操作中的不同方向。该器件可以以其他方式定向(旋转90度或在其他方向),并且本文使用的空间相关描述同样可以相应地解释。应该理解,当一个元件被称为“连接到”或“耦接到”另一个元件时,它可以直接连接到或耦接到另一个元件,或者可以存在中间元件。
图1A至1I示出了根据本申请一个实施例的用于制造半导体器件的方法过程的截面示意图。该方法过程可以执行在一个基底上,该基底上安装有例如半导体晶片或半导体封装的多个电子元件,从而可以在每个电子元件上形成屏蔽层。屏蔽层可以由诸如铜、铝、铁或任何其他适合用于电磁干扰(EMI)屏蔽的材料。电磁屏蔽层可以将引入至电子元件的电磁干扰或由电子元件产生的电磁干扰屏蔽掉。
如图1A所示,提供了基底100。基底100具有顶表面102,以及与顶表面102相对的底表面104。在一些实施例中,基底100可以是印刷电路板或者任何其他需要进一步切割处理的适合的基底结构。基底100可以包括一层或多层绝缘层或钝化层,以及形成在绝缘层或钝化层中的一个或多个互连结构106。每个互连结构106可以包括一个或多个穿过绝缘层的导电通孔108,以及分别形成在顶表面102和底表面104上的一个或多个导电层110和112。基底100可以包括一个或多个预浸渍的聚四氟乙烯、FR-4、FR-1、CEM-1或CEM-3的层压层,以及酚醛棉纸、环氧树脂、树脂、玻璃纤维、无光玻璃、聚酯或其它增强纤维或织物的组合物。该基底100也可为多层柔性层压板、陶瓷、覆铜层压板、玻璃或半导体晶片。基底100中的导电层或重分布层(RDL)可以使用溅射、电镀、无电电镀或其它适合的沉积工艺形成。该导电层可为一或多个Al、Cu、Sn、Ni、Au、Ag、Ti、W或其它适合的导电材料层。
多个电子元件114被安装在基底100的顶表面102上。电子元件114可以被分别电连接到互连结构106。在一些实施例中,电子元件114可以包括半导体晶片或半导体封装。例如,半导体晶片可以是倒装芯片类型,并且可以被安装在顶表面102上,以使得半导体晶片的导电凸点可以被焊接到基底100的一些互连结构106上。在另一些实施例中,半导体晶片可以包括焊盘,其可以被通过引线键合工艺连接到互连结构106上。在图1A所示的实施例中,基底100包括位于底表面104上的平面网格阵列(LGA)触点,然而,在一些其他的实施例中,基底也可以包括位于底表面104上的另一些类型的导电图形或结构,例如球栅阵列(BGA)凸点。
如图1B所示,密封层116可以形成在基底100上,其覆盖电子元件114和顶表面102。密封层116可以由通用模制成型复合树脂构成,例如环氧树脂,但是本申请并不限制于此。密封层116可以保护电子元件114免于接触外部环境。在一些实施例中,可以对密封层116进行研磨操作,以减少密封层116的厚度,并且可选地将电子元件114暴露出来。
如图1C所示,基底100被放置在第一载台118上,而其底表面104朝上,并且密封层116接触第一载台118。第一载台118作用为传送载台,其使得基底100可以被倒置,并且还便于在基底100的底表面104上进行后续处理,正如下文中详细说明的。
如图1D所示,复合胶带120被附接到基底100的底表面104。复合胶带120包括粘合层122,其可以被粘附到底表面104。粘合层122对紫外辐射敏感,从而当被紫外线照射后,粘合层122的某些特性会改变,例如粘合层122的粘性会降低。复合胶带120还包括基膜124,该基膜124与粘合层122层叠在一起。基膜124是可透紫外线的,从而当紫外线光源(图中未示出)从复合胶带120的基膜侧发出紫外线时,紫外线可以穿过基膜124并进入到粘合层122中。在一些实施例中,基膜124是聚酰亚胺薄膜,或者任何适合的可透紫外线薄膜。应当注意的是,尽管图1D中示出的复合胶带120包括两层122和124,但是根据本申请的其他实施例,复合胶带可以包括更多层。例如,一层或多层中间层可以设置于粘合层122和基膜124之间,这些中间层也是可透紫外线的。在另一示例中,第二可透紫外线粘合层可以被设置于基膜的另一侧,其有助于将复合胶带附接到第二载台上。优选地,第二可透紫外线粘合层还可以是对紫外线敏感的。以这样的方式,第二可透紫外线粘合层的粘性也可以随着紫外辐射而降低,从而有助于在后续处理中将复合胶带从第二载台上分离。
仍参考图1D,第二载台126被附接到基底100。具体地,第二载台126可以被设置在基底100的上侧,并且因此与基膜124接触。以这样的方式,基底100可以被夹持在第一载台118和第二载台126之间。第二载台126是可透紫外线的载台,其允许紫外线通过。因为第二载台126和基膜124都是可透紫外线的,所以从外部紫外线光源发出的紫外线可以穿过这两者而进入到紫外线敏感的粘合层122中。在一些实施例中,可透紫外线的第二载台126包括蓝宝石载台或玻璃载台。接着,如图1E所示,第一载台118、第二载台126和夹持在其间的基底100可以被倒置,并且随后第一载台118可以被与基底100分开,使得基底100被放置在第二载台126上。
应当注意的是,尽管在图1C至1E所示的步骤中两个载台(也即第一载台118和第二载台126)被用来夹持基底100,并且将复合胶带120附接到基底100上,但是单个载台也可以被用来实现相同或相似的目的。例如,在如图1B所示的在基底上形成密封层的步骤之后,基底可以被放置在安装有复合胶带的第二载台上。相应地,复合胶带可以被放置在基底和第二载台之间,其中粘合层朝上且与基底100接触,而基膜则朝下并与第二载台126接触。
如图1F所示,在分离第一载台之后,基底100可以被切割,例如使用切割锯或切割刀切割,以将这些电子元件114相互分离。每个电子元件114、位于电子元件114下方的基底100的一部分、以及覆盖电子元件114的密封层116形成了半导体器件。例如,切割锯或刀128可以切割下方没有电子元件的密封层116的一些区域。以这样的方式,可以在每两个相邻的电子元件114之间的基底100和密封层116中形成沟槽130。沟槽130延伸穿过基底100和粘合层122。在一些实施例中,沟槽130可以不延伸到基膜124中,正如图1F所示;在另一些实施例中,沟槽130可以延伸进入基膜124但不进入第二载台126中。可以看出,基膜124可以作为第二载台126的保护膜,从而避免在切割工艺时对第二载台126产生不必要的损伤,并且允许在后续批次的制造中重复使用第二载台126。在一些实施例中,沟槽130的深宽比小于20:1,或者优选地小于10:1。
在切割工艺之后,如图1G所示,可以在分离的半导体器件132上沉积屏蔽材料,从而使得在每个半导体器件132上形成屏蔽层134。具体地,屏蔽材料可以被沉积到两个相邻半导体器件132之前的沟槽130中。以这样的方式,半导体器件132的顶表面和侧壁均覆盖有屏蔽层134。在一些实施例中,屏蔽材料可以通过喷涂、电镀、溅射或任何其他适合的材料沉积工艺形成。屏蔽材料可以由铜、铝、钢、或者任何其他适合电磁干扰屏蔽的材料形成。
如图1H所示,例如紫外线光束的紫外辐射可以从第二载台126下方的光源射出。如上所述,由于第二载台126和基膜124均是可透紫外线的,因此紫外线可以穿过第二载台126和基膜124进入到对紫外线敏感的粘合层122。紫外线对粘合层122的辐射改变了粘合层122的特性,包括降低了粘合层122的粘性。在一些实施例中,辐射可以按行或按列进行,这相比于以往按个/单元来进行辐射处理的方法显著提高了效率。在一些优选的实施例中,辐射还可以按平面来进行,这进一步提高的产率。
此后,如图1I所示,可以对每个半导体器件132施加力,以将它们从第二载台126上分离。由于之前紫外辐射导致粘合层122的粘性下降,因此可较为容易地把半导体器件132从第二载台126上剥离。此外,由于相邻半导体器件132之间的沟槽130延伸得足够深,深入到粘合层122中,因此屏蔽层134可以在半导体器件132的侧壁底部清楚地断裂开,而不会在其上形成不期望出现的金属毛刺,而金属毛刺会损害半导体器件的性能,并且可能导致诸如短路等质量问题。
仍参考图1I,在移除半导体器件132之后,复合胶带120仍处于第二载台126上。相应地,复合胶带120可以进一步地被从第二载台126上分离,从而第二载台126可以被重复使用,用来制造另一批次的半导体器件。换言之,通过循环使用第二载台,整个工艺是可持续的,从而制造成本可以被降低。正如前述,在一些实施例中,第二可透紫外线的粘合层可以被设置在基膜的另一侧,并且优选地,第二可透紫外线的粘合层也可以是对紫外线敏感的。因此,第二可透紫外线的粘合层的粘性可以被通过紫外辐射来降低,并且更容易从第二载台上分离复合胶带。
上述图1A至1I所示的实施例描述了用于制造半导体器件的方法,其中这些半导体器件的顶表面和侧壁上均具有屏蔽层。在一些其他的实施例中,半导体器件的侧壁上也可以不形成屏蔽层。图2A至2E示出了根据本申请另一实施例的用于制造半导体器件的另一方法过程的截面示意图。该方法可以用于至少没有侧壁屏蔽层的半导体器件。应当注意的是,该方法的某些步骤可与图1A至1I所示的方法过程中的某些步骤相同或相似,在此不再赘述。
如图2A所示,提供了基底200。基底200具有顶表面202,以及与顶表面相对的底表面204。基底202可以包括一层或多层绝缘层或钝化层,以及形成在绝缘层或钝化层中的一个或多个互连结构206。多个电子元件214被安装在基底200的顶表面202上。电子元件214可以被分别电连接到互连结构206。在一些实施例中,电子元件214可以包括半导体晶片或半导体封装。密封层216可以形成在基底200上,其覆盖电子元件214和顶表面202。密封层216可以由通用模制成型复合树脂构成,例如环氧树脂。
基底200被通过复合胶带220放置在可透紫外线的载台226上。具体地,复合胶带220包括粘合层222和基膜224,该基膜224与粘合层222层叠在一起。粘合层222粘附到基底200的底表面204,而基膜224被附接到可透紫外线的载台226。粘合层222对紫外线敏感,从而在被紫外线光束照射后,粘合层222的某些特性会改变,例如粘合层222的粘性会降低。基膜224是可透紫外线的,从而当紫外线(图中未示出)从复合胶带220的基膜侧发出紫外线时,紫外线可以穿过基膜224并进入到粘合层222中。基底200、复合胶带220和载台226的结构和材料与图1A至1I所描述的那些部件相类似。
如图2B所示,屏蔽材料可以被沉积到基底200上,从而在基底200上形成屏蔽层234,或者更具体地,在密封层216上形成屏蔽层。在一些实施例中,屏蔽材料可以通过喷涂、电镀、溅射或任何其他适合的材料沉积工艺形成。屏蔽材料可以由铜、铝、钢或任何其他适合电磁干扰屏蔽的材料形成。
此后,如图2C所示,基底200可以被切割,例如使用切割锯或切割刀切割,以将这些电子元件214相互分离。每个电子元件214、位于电子元件214下方的基底200的一部分、以及覆盖电子元件214的密封层216形成了半导体器件。因此,可以在每两个相邻的电子元件214之间的基底200和密封层216中形成沟槽230。沟槽230延伸穿过基底200和粘合层222。在一些实施例中,沟槽230可以不延伸到基膜224中,正如图1C所示;在另一些实施例中,沟槽230可以延伸进入基膜224但不进入载台226中。可以看出,基膜224作为载台226的保护膜,从而避免在切割工艺时对载台226产生不必要的损伤。此外,由于切割工艺是在屏蔽层沉积工艺之前进行的,因此在半导体器件的侧壁上不会形成屏蔽层,或者至少不会在沟槽230中形成屏蔽层。
如图2D所示,例如紫外线光束的紫外辐射可以从载台226下方的光源射出。紫外线可以穿过载台226和基膜224进入到对紫外线敏感的粘合层222,从而改变粘合层222的特性,包括降低了粘合层222的粘性。接着,如图2E所示,可以对每个分离的半导体器件232施加力,以将它们从载台226上分离。由于粘合层122的粘性下降,可较为容易地把半导体器件232从载台226上剥离。此外,由于屏蔽层是在切割工艺中分离为多个,因此在分离的半导体器件中不会形成毛刺。以这样的方式,由于金属毛刺导致的例如短路等质量问题可以被避免。
图3示出了根据本申请一个实施例的用于制造半导体器件的方法。关于该方法的细节可以参考图1A至1I所示的实施例。
如图3所示,在步骤302,将具有多个电子元件的基底附接至复合胶带上。该复合胶带具有对紫外辐射敏感的粘合层以及可透紫外线的基膜,其中所述基底被附接至所述复合胶带的所述粘合层。在步骤304,将所述基底和所述复合胶带放置在可透紫外线的载台上,其中所述可透紫外线的载台与所述复合胶带的所述可透紫外线的基膜接触,。在步骤306,将所述基底切割为多个半导体器件,其中每个半导体器件具有所述多个电子元件中的一个电子元件。在步骤308,将屏蔽材料沉积在所述多个半导体器件上,以在所述多个半导体器件中的每一个半导体器件上形成屏蔽层。在步骤310,透过所述可透紫外线的载台向所述复合胶带照射紫外辐射,以降低所述粘合层的粘性。在步骤312,将所述多个半导体器件从所述可透紫外线的载台上分离。
图4示出了根据本申请一个实施例的用于制造半导体器件的方法。关于该方法的细节可以参考图2A至2E所示的实施例。
如图4所示,在步骤402,将具有多个电子元件的基底附接至复合胶带上。所述复合胶带具有对紫外辐射敏感的粘合层以及可透紫外线的基膜,其中所述基底被附接至所述复合胶带的所述粘合层。在步骤404,将所述基底和所述复合胶带放置在可透紫外线的载台上,其中所述可透紫外线的载台与所述复合胶带的所述可透紫外线的基膜接触,。在步骤406,将屏蔽材料沉积在所述基底上。在步骤408,将所述基底切割为多个半导体器件,其中每个半导体器件具有所述多个电子元件中的一个电子元件。在步骤410,透过所述可透紫外线的载台向所述复合胶带照射紫外辐射,以降低所述粘合层的粘性。在步骤412,将所述多个半导体器件从所述可透紫外线的载台上分离。
本文的讨论包括许多说明性附图,这些说明性附图显示了用于制造半导体器件的方法中的各种步骤。为了说明清楚起见,这些图并未显示每个示例组件的所有方面。本文提供的任何示例组件和/或方法可以与本文提供的任何或所有其他组件和/或方法共享任何或所有特征。
本文已经参照附图描述了各种实施例。然而,显然可以对其进行各种修改和改变,并且可以实施另外的实施例,而不背离如所附权利要求中阐述的本发明的更广泛范围。此外,通过考虑说明书和本文公开的本发明的一个或多个实施例的实践,其他实施例对于本领域技术人员将是明显的。因此,本申请和本文中的实施例旨在仅被认为是示例性的,本发明的真实范围和精神由所附示例性权利要求的列表指示。

Claims (14)

1.一种用于制造半导体器件的方法,其特征在于,所述方法包括:
将具有多个电子元件的基底附接至复合胶带上,所述复合胶带具有对紫外辐射敏感的粘合层以及可透紫外线的基膜,其中所述基底被附接至所述复合胶带的所述粘合层;
将所述基底和所述复合胶带放置在可透紫外线的载台上,其中所述可透紫外线的载台与所述复合胶带的所述可透紫外线的基膜接触;
将所述基底切割为多个半导体器件,其中每个半导体器件具有所述多个电子元件中的一个电子元件;
将屏蔽材料沉积在所述多个半导体器件上,以在所述多个半导体器件中的每一个半导体器件上形成屏蔽层;
透过所述可透紫外线的载台向所述复合胶带照射紫外辐射,以降低所述粘合层的粘性;以及
将所述多个半导体器件从所述可透紫外线的载台上分离。
2.根据权利要求1所述的方法,其特征在于,将所述基底切割为多个半导体器件的步骤包括:
在每两个相邻的电子元件之间形成沟槽,所述沟槽延伸穿过所述基底并且至少延伸至所述复合胶带的所述粘合层中。
3.根据权利要求2所述的方法,其特征在于,所述沟槽不延伸穿过所述可透紫外线的基膜。
4.根据权利要求1所述的方法,其特征在于,所述基底包括一个或多个导电层或者重分布层。
5.根据权利要求1所述的方法,其特征在于,所述电子元件包括一个或多个半导体晶片或半导体封装。
6.根据权利要求1所述的方法,其特征在于,所述可透紫外线的基膜包括聚酰亚胺薄膜。
7.根据权利要求1所述的方法,其特征在于,所述可透紫外线的载台包括蓝宝石载台或玻璃载台。
8.根据权利要求1所述的方法,其特征在于,所述基底包括平面网格阵列触点或球栅阵列凸点。
9.一种用于制造半导体器件的方法,其特征在于,所述方法包括:
将具有多个电子元件的基底附接至复合胶带上,所述复合胶带具有对紫外辐射敏感的粘合层以及可透紫外线的基膜,其中所述基底被附接至所述复合胶带的所述粘合层;
将所述基底和所述复合胶带放置在可透紫外线的载台上,其中所述可透紫外线的载台与所述复合胶带的所述可透紫外线的基膜接触;
将屏蔽材料沉积在所述基底上;
将所述基底切割为多个半导体器件,其中每个半导体器件具有所述多个电子元件中的一个电子元件;
透过所述可透紫外线的载台向所述复合胶带照射紫外辐射,以降低所述粘合层的粘性;以及
将所述多个半导体器件从所述可透紫外线的载台上分离。
10.根据权利要求9所述的方法,其特征在于,所述基底包括一个或多个导电层或重分布层。
11.根据权利要求9所述的方法,其特征在于,所述电子元件包括一个或多个半导体晶片或半导体封装。
12.根据权利要求9所述的方法,其特征在于,所述可透紫外线的基膜包括聚酰亚胺薄膜。
13.根据权利要求9所述的方法,其特征在于,所述可透紫外线的载台包括蓝宝石载台或玻璃载台。
14.根据权利要求9所述的方法,其特征在于,所述基底包括平面网格阵列触点或球栅阵列凸点。
CN202210593487.3A 2022-05-27 2022-05-27 用于制造半导体器件的方法 Pending CN117174595A (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202210593487.3A CN117174595A (zh) 2022-05-27 2022-05-27 用于制造半导体器件的方法
US18/317,093 US20230386888A1 (en) 2022-05-27 2023-05-15 Methods for making semiconductor devices
KR1020230063867A KR20230165706A (ko) 2022-05-27 2023-05-17 반도체 디바이스를 제조하기 위한 방법
TW112119075A TW202401515A (zh) 2022-05-27 2023-05-23 用於製造半導體裝置的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210593487.3A CN117174595A (zh) 2022-05-27 2022-05-27 用于制造半导体器件的方法

Publications (1)

Publication Number Publication Date
CN117174595A true CN117174595A (zh) 2023-12-05

Family

ID=88876757

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210593487.3A Pending CN117174595A (zh) 2022-05-27 2022-05-27 用于制造半导体器件的方法

Country Status (4)

Country Link
US (1) US20230386888A1 (zh)
KR (1) KR20230165706A (zh)
CN (1) CN117174595A (zh)
TW (1) TW202401515A (zh)

Also Published As

Publication number Publication date
KR20230165706A (ko) 2023-12-05
US20230386888A1 (en) 2023-11-30
TW202401515A (zh) 2024-01-01

Similar Documents

Publication Publication Date Title
US10790158B2 (en) Semiconductor device and method of balancing surfaces of an embedded PCB unit with a dummy copper pattern
US8030750B2 (en) Semiconductor device packages with electromagnetic interference shielding
US20200126929A1 (en) Semiconductor device with an electromagnetic interference (emi) shield
US20150008566A1 (en) Method and structure of panelized packaging of semiconductor devices
EP1180792A1 (en) Semiconductor packaging
CN210607192U (zh) 面板组件、晶圆封装体以及芯片封装体
KR102255557B1 (ko) 인캡슐런트로부터 연장되어 나오는 전기 컴포넌트 단자를 갖는 sip를 형성하는 반도체 장치 및 그 방법
TW201834084A (zh) 半導體裝置及形成具有嵌入式電感或封裝的整合式系統級封裝模組之方法
CN102543945A (zh) 用于单元化层叠半导体器件封装的射频屏蔽
US9824979B2 (en) Electronic package having electromagnetic interference shielding and associated method
US11387190B2 (en) Shielded electronic modules and methods of forming the same utilizing plating and double-cut singulation
US11990424B2 (en) Selective EMI shielding using preformed mask
US20230207485A1 (en) Selective EMI Shielding Using Preformed Mask with Fang Design
CN117174595A (zh) 用于制造半导体器件的方法
CN106653734B (zh) 具有电磁干扰屏蔽的半导体装置及其制造方法
US20230207334A1 (en) Production method for semiconductor packages
CN211017006U (zh) 面板组件、晶圆封装体以及芯片封装体
TWI838944B (zh) 半導體裝置與形成嵌入式晶粒基板的方法以及具有其之系統級封裝模組
US20240112975A1 (en) Electronic devices and methods of manufacturing electronic devices
KR20240002912A (ko) 내장형 자기 차폐를 형성하는 반도체 디바이스 및 그 제조방법
KR20230106510A (ko) 슬롯형 기판으로 선택적 emi 차폐를 형성하는 반도체 디바이스 및 그 차폐 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination