CN117174572A - Method for improving flatness local abnormality of silicon carbide substrate - Google Patents
Method for improving flatness local abnormality of silicon carbide substrate Download PDFInfo
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- CN117174572A CN117174572A CN202311248210.8A CN202311248210A CN117174572A CN 117174572 A CN117174572 A CN 117174572A CN 202311248210 A CN202311248210 A CN 202311248210A CN 117174572 A CN117174572 A CN 117174572A
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- 239000000758 substrate Substances 0.000 title claims abstract description 123
- 238000000034 method Methods 0.000 title claims abstract description 46
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 34
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 34
- 230000005856 abnormality Effects 0.000 title abstract description 19
- 238000005498 polishing Methods 0.000 claims abstract description 68
- 238000012545 processing Methods 0.000 claims abstract description 17
- 230000002159 abnormal effect Effects 0.000 claims abstract description 15
- 239000000919 ceramic Substances 0.000 claims abstract description 15
- 238000012360 testing method Methods 0.000 claims abstract description 15
- 238000007517 polishing process Methods 0.000 claims abstract description 11
- 238000009826 distribution Methods 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims description 6
- 238000010586 diagram Methods 0.000 claims description 5
- 239000004744 fabric Substances 0.000 claims description 3
- 238000012216 screening Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 6
- 238000002360 preparation method Methods 0.000 abstract description 4
- 238000012797 qualification Methods 0.000 abstract description 4
- 238000013016 damping Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000012958 reprocessing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
A method for improving local abnormality of flatness of a silicon carbide substrate relates to the technical field of silicon carbide, in particular to a silicon carbide substrate with local abnormality of flatness, which can avoid processing cost loss caused by repeated reworking, improve the qualification rate of finished products, improve the quality of the silicon carbide substrate and provide reliability for the quality of epitaxial materials and the preparation of devices. In the method for improving the local abnormality of the flatness of the silicon carbide substrate, the substrate with abnormal flatness is subjected to thickness test and sorting, then is analyzed and area positioning is carried out according to the distribution of the LTV and the TTV of the flatness, then the patch direction of the substrate on a ceramic disc is determined according to the abnormal position of the flatness, and finally, rough polishing and fine polishing processes with matched removal amount are selected for polishing according to the test values of the LTV and the TTV, so that the uniformity of the flatness of the whole wafer is finally realized.
Description
Technical Field
The invention relates to the technical field of silicon carbide, in particular to a method for improving local abnormality of flatness of a silicon carbide substrate.
Background
At present, silicon carbide material is widely used as one of third-generation semiconductor materials in the fields of microwave communication, new energy automobiles and the like. The flatness of a silicon carbide substrate is an important indicator for measuring the quality of the substrate. The poor flatness of the substrate may affect the adsorption force of the vacuum chuck in the manufacturing process, and the wafer flies during the rotation process, thereby causing damage to the substrate; in addition, substrate flatness failure during epitaxial growth may exacerbate in-plane non-uniformity of thickness and electrical parameters during epitaxial growth and worsen in-plane stress distribution conditions of the substrate, and this condition is particularly pronounced for thick film epitaxial growth.
In the prior art, as shown in fig. 1, in order to prevent a substrate with a large local variation in flatness from entering downstream, the substrate is processed in such a way that the substrate is degraded or reworked to be qualified. If the failure occurs again after the secondary processing, the degradation or processing is required again. The reprocessing process mainly adopts a production line process to process, and the substrate flatness which is reprocessed is easily disqualified again due to uneven wafer surface flattening structure; furthermore, repeated processing can lead to thinner and thinner substrates, which eventually degrade into rejects when the substrate thickness fails to meet customer requirements. Therefore, in the prior art, the repeated processing of the substrate can affect the quality of the substrate, delay time and increase the processing cost.
In other words, problems that may occur with conventional methods: in the processing process of the substrate, the substrate is in different states in the polishing process due to different thicknesses of the substrate, and the flatness of the substrate is finally greatly and partially changed and is disqualified; in the polishing process, the applied equipment pressure acts on the substrate, but the pressure acting born by the substrate is different due to the fact that the thickness difference of the substrate is large, the thick substrate can participate in polishing, but the thin substrate cannot completely participate in polishing, so that local high points are not completely removed, or the substrate cannot be polished uniformly, and reworking is caused; and the result of multiple rework: (1) the thickness of the substrate does not reach the standard, and the final substrate is not qualified; (2) Because the thickness deviation of the substrate is large, when the set pressure is too large, the substrate cannot bear the set pressure and is easy to break, so that larger loss is caused.
Disclosure of Invention
The invention aims to provide a method for improving the flatness local abnormality of a silicon carbide substrate, which can avoid the processing cost loss caused by repeated reworking, improve the qualification rate of finished products, improve the quality of the silicon carbide substrate and provide reliability for the quality of epitaxial materials and the preparation of devices.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a method for improving local anomalies in flatness of a silicon carbide substrate, comprising the steps of:
testing the thickness of the substrate, and screening the substrate according to the thickness value of the substrate, wherein the thickness difference of the substrates processed in the same batch is +/-2.5 mu m;
performing region positioning classification by referring to the flatness distribution diagram and data of the substrate;
patch direction determination: determining the surface mounting direction of the substrate on the ceramic disc according to the position of the abnormal point of the flatness of the substrate;
and (3) process determination: comprehensively matching the surface mounting mode of the substrate with the processing pressure, temperature and time, selecting a proper process for chemical mechanical polishing, and finally realizing the uniformity of the whole piece; and, the chemical mechanical polishing is divided into two steps, rough polishing and fine polishing.
The method for classifying the area positioning by the flatness distribution map and the data of the reference substrate specifically comprises the following steps: according to a clock dial clock dividing method, region positioning is carried out, namely 1 point-2 points, 2 points-3 points, 3 points-4 points, 4 points-5 points, 5 points-6 points, 6 points-7 points, 7 points-8 points, 8 points-9 points, 9 points-10 points, 10 points-11 points, 11 points-12 points, 1 point, 2 points, 3 points, 4 points, 5 points, 6 points, 7 points, 8 points, 9 points, 10 points, 11 points and 12 points.
Specifically, when the direction of the patch is determined, the substrate is fixed on the ceramic disk, so that the high point faces the center of the ceramic disk.
Further, the polishing pad used for rough polishing is a non-woven polishing pad, and the rough polishing process determines: y is 1 =0.05x 1 +0.26 x 2 +0.01 x 3 -12.05；
Wherein y is 1 Represents the removal amount of rough polishing, x 1 Represents the rough polishing pressure, x 2 Represents the rough polishing temperature, x 3 Represents rough polishing time, and x 1 In the range of 150-180KG, x 2 In the range of 25-30 ℃, x 3 The range of (2) is 120min-150min.
Further, the polishing pad used for the fine polishing is a damping cloth polishing pad, and the fine polishing process determines that: y is 2 =0.00084z 1 -0.078 z 2 +0.0048 z 3 +0.86；
Wherein y is 2 Represents the removal amount of fine polishing, z 1 Represents the polishing pressure, z 2 Representing the polishing temperature, z 3 Represents the finish polishing time, and z 1 In the range of 150-200KG, z 2 In the range of 25-30 ℃, z 3 Is in the range of 240min-350min.
Further, the thickness control range of the 4inch semi-insulating substrate is as follows: 490 μm is less than or equal to h- (y) 1 +y 2 )≤515μm；
The thickness control range of the 6inch semi-insulating substrate is as follows: 490 μm is less than or equal to h- (y) 1 +y 2 )≤520μm；
The thickness control range of the 6inch conductive substrate is as follows: h- (y) with a diameter of 330 mu m or less 1 +y 2 ) Less than or equal to 375 mu m, and h is the thickness of the substrate tested in the first step.
Compared with the prior art, the method for improving the flatness local abnormality of the silicon carbide substrate has the following advantages:
in the method for improving the local abnormality of the flatness of the silicon carbide substrate, the thickness test and the sorting are firstly carried out on the substrate with abnormal flatness, then the analysis is carried out according to the distribution of the LTV and the TTV of the flatness, the area positioning is carried out, then the patch direction of the substrate on the ceramic disc is determined according to the abnormal flatness position, and finally the rough polishing and the fine polishing processes with the matched removal amount are selected for polishing according to the test values of the LTV and the TTV, so that the uniformity of the flatness of the whole wafer is finally realized; therefore, the method for improving the flatness local abnormality of the silicon carbide substrate can effectively solve the problem of flatness LTV and TTV abnormality, thereby improving the qualification rate of finished products and the quality of the silicon carbide substrate, providing reliability for the quality of epitaxial materials and the preparation of devices, and avoiding the cost loss caused by repeated reworking.
Drawings
FIG. 1 is a flow chart of a method for improving local anomalies in flatness of a silicon carbide substrate in the prior art;
FIG. 2 is a flow chart of a method for improving local anomalies in flatness of a silicon carbide substrate according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a patch method according to an embodiment of the present invention in a method for improving local anomalies in flatness of a silicon carbide substrate;
fig. 4 is a schematic diagram of distribution structures of LTV before and after a process in a specific embodiment of a method for improving local abnormality of flatness of a silicon carbide substrate according to an embodiment of the present invention.
Detailed Description
In order to facilitate understanding, the method for improving the flatness local abnormality of the silicon carbide substrate provided by the embodiment of the invention is described in detail below with reference to the accompanying drawings.
The embodiment of the invention provides a method for improving local abnormality of flatness of a silicon carbide substrate, which is shown in fig. 2 and comprises the following steps:
testing the thickness of the substrate, and screening the substrate according to the thickness value of the substrate, wherein the thickness difference of the substrates processed in the same batch is +/-2.5 mu m;
performing region positioning classification by referring to the flatness distribution diagram and data of the substrate;
patch direction determination: determining the surface mounting direction of the substrate on the ceramic disc according to the position of the abnormal point of the flatness of the substrate;
and (3) process determination: comprehensively matching the surface mounting mode of the substrate with the processing pressure, temperature and time, selecting a proper process for chemical mechanical polishing, and finally realizing the uniformity of the whole piece; and, the chemical mechanical polishing is divided into two steps, rough polishing and fine polishing.
Compared with the prior art, the method for improving the flatness local abnormality of the silicon carbide substrate has the following advantages:
in the method for improving the local abnormality of the flatness of the silicon carbide substrate, the thickness test and the sorting are firstly carried out on the substrate with abnormal flatness, then the analysis is carried out according to the distribution of the LTV and the TTV of the flatness, the area positioning is carried out, then the patch direction of the substrate on the ceramic disc is determined according to the abnormal flatness position, and finally the rough polishing and the fine polishing processes which are matched with the removal amount are selected according to the test values of the LTV and the TTV for polishing, so that the uniformity of the flatness of the whole wafer is finally realized; therefore, the method for improving the flatness local abnormality of the silicon carbide substrate provided by the embodiment of the invention can effectively solve the problem of flatness LTV and TTV abnormality, thereby improving the qualification rate of finished products and the quality of the silicon carbide substrate, providing reliability for the quality of epitaxial materials and the preparation of devices, and simultaneously avoiding cost loss caused by repeated reworking.
The classifying the area location by using the flatness distribution map and the data of the reference substrate may specifically include: according to a clock dial clock dividing method, region positioning is carried out, namely 1 point-2 points, 2 points-3 points, 3 points-4 points, 4 points-5 points, 5 points-6 points, 6 points-7 points, 7 points-8 points, 8 points-9 points, 9 points-10 points, 10 points-11 points, 11 points-12 points, 1 point, 2 points, 3 points, 4 points, 5 points, 6 points, 7 points, 8 points, 9 points, 10 points, 11 points and 12 points.
Specifically, when the direction of the patch is determined, the substrate is fixed to the ceramic disk so that the high point is oriented toward the center of the ceramic disk.
Further, the polishing pad used in the rough polishing described above may preferably be a nonwoven polishing pad, and the rough polishing process determines: y is 1 =0.05x 1 +0.26 x 2 +0.01 x 3 -12.05；
Wherein y is 1 Represents the removal amount of rough polishing, x 1 Represents the rough polishing pressure, x 2 Represents the rough polishing temperature, x 3 Represents rough polishing time, and x 1 In the range of 150-180KG, x 2 In the range of 25-30 ℃, x 3 The range of (2) is 120min-150min.
Further, the polishing pad used in the fine polishing may preferably be a damping cloth polishing pad, and the fine polishing process determines: y is 2 =0.00084z 1 -0.078 z 2 +0.0048 z 3 +0.86；
Wherein y is 2 Represents the removal amount of fine polishing, z 1 Represents the polishing pressure, z 2 Representing the polishing temperature, z 3 Represents the finish polishing time, and z 1 In the range of 150-200KG, z 2 In the range of 25-30 ℃, z 3 Is in the range of 240min-350min.
Further, the thickness control range of the 4inch semi-insulating substrate is as follows: 490 μm is less than or equal to h- (y) 1 +y 2 )≤515μm；
The thickness control range of the 6inch semi-insulating substrate is as follows: 490 μm is less than or equal to h- (y) 1 +y 2 )≤520μm；
The thickness control range of the 6inch conductive substrate is as follows: h- (y) with a diameter of 330 mu m or less 1 +y 2 ) Less than or equal to 375 mu m, and h is the thickness of the substrate tested in the first step;
the LTV control range is as follows: LTV is less than 2 mu m, and TTV control range is as follows: TTV < 5 μm.
It should be noted here that the local abnormality of flatness is mainly represented by a large local thickness deviation (English: local Thickness Variation, LTV) or total thickness deviation (English: total Thickness Variation, TTV) of the substrate.
The following is a detailed description of a 6inch conductive substrate (see fig. 3 and 4):
detailed description of the preferred embodiments
Substrate A, flatness test result LTV of 2.86 μm, TTV of 3.17 μm, flatness locally failed:
step S1, determining the thickness of a substrate to be 350.21 mu m;
s2, the local abnormal position of the flatness is at 1-2 points;
s3, determining the patch direction according to the substrate flatness abnormal points: the 1-2 point direction of the substrate faces the center of the ceramic disk;
s4, selecting a matching process:
rough polishing: the pressure is 120KG, the temperature is 30 ℃, and the processing time is 120min;
fine polishing: the pressure is 180KG, the temperature is 28 ℃, and the processing time is 300min;
s5, testing the flatness and thickness of the polished substrate;
second embodiment
Substrate B, flatness test result LTV of 3.08 μm, TTV of 3.37 μm, flatness local failure:
step S1, determining the thickness of a substrate to be 355.08 mu m;
s2, the local abnormal position of the flatness is at 5-6 points;
s3, determining the patch direction according to the substrate flatness abnormal points: the 5-6 points of the substrate face the center of the ceramic disk;
s4, selecting a matching process:
rough polishing: the pressure is 150KG, the temperature is 25 ℃, and the processing time is 120min;
fine polishing: the pressure is 200KG, the temperature is 30 ℃, and the processing time is 350min;
s5, testing the flatness and thickness of the polished substrate;
detailed description of the preferred embodiments
Substrate C, flatness test result LTV of 5.56 μm, TTV of 5.81 μm, flatness locally failed:
step S1, determining the thickness of a substrate to be 360.11 mu m;
s2, locally abnormal positions of flatness are 8-9 points;
s3, determining the patch direction according to the substrate flatness abnormal points: the 8-9 point direction of the substrate faces the center of the ceramic disk;
s4, selecting a matching process:
rough polishing: the pressure is 180KG, the temperature is 28 ℃, and the processing time is 150min;
fine polishing: the pressure is 150KG, the temperature is 25 ℃, and the processing time is 240min;
and S5, testing the flatness and thickness of the polished substrate.
Summarizing the numerical values before and after the process:
the foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. A method for improving local anomalies in flatness of a silicon carbide substrate, comprising the steps of:
testing the thickness of the substrate, and screening the substrate according to the thickness value of the substrate, wherein the thickness difference of the substrates processed in the same batch is +/-2.5 mu m;
performing region positioning classification by referring to the flatness distribution diagram and data of the substrate;
patch direction determination: determining the surface mounting direction of the substrate on the ceramic disc according to the position of the abnormal point of the flatness of the substrate;
and (3) process determination: comprehensively matching the surface mounting mode of the substrate with the processing pressure, temperature and time, selecting a proper process for chemical mechanical polishing, and finally realizing the uniformity of the whole piece; and, the chemical mechanical polishing is divided into two steps, rough polishing and fine polishing.
2. The method for improving local anomalies in flatness of a silicon carbide substrate according to claim 1, wherein the classifying of the area location with respect to the flatness profile and data of the substrate specifically comprises: according to a clock dial clock dividing method, region positioning is carried out, namely 1 point-2 points, 2 points-3 points, 3 points-4 points, 4 points-5 points, 5 points-6 points, 6 points-7 points, 7 points-8 points, 8 points-9 points, 9 points-10 points, 10 points-11 points, 11 points-12 points, 1 point, 2 points, 3 points, 4 points, 5 points, 6 points, 7 points, 8 points, 9 points, 10 points, 11 points and 12 points.
3. The method for improving flatness of a silicon carbide substrate according to claim 1, wherein the mounting direction is determined such that the substrate is fixed to the ceramic plate with the high point oriented toward the center of the ceramic plate.
4. A method of improving localized anomalies in flatness of a silicon carbide substrate according to any one of claims 1-3, characterized in that the polishing pad used for rough polishing is a non-woven polishing pad, and the rough polishing process determines: y is 1 =0.05x 1 +0.26 x 2 +0.01 x 3 -12.05；
Wherein y is 1 Represents the removal amount of rough polishing, x 1 Represents the rough polishing pressure, x 2 Represents the rough polishing temperature, x 3 Represents rough polishing time, and x 1 In the range of 150-180KG, x 2 In the range of 25-30 ℃, x 3 The range of (2) is 120min-150min.
5. The method for improving local anomalies in flatness of a silicon carbide substrate according to claim 4, wherein the polishing pad used for the fine polishing is a damped cloth polishing pad, and the fine polishing process determines: y is 2 =0.00084z 1 -0.078 z 2 +0.0048 z 3 +0.86；
Wherein y is 2 Represents the removal amount of fine polishing, z 1 Represents the polishing pressure, z 2 Representing the polishing temperature, z 3 Represents the finish polishing time, and z 1 In the range of 150-200KG, z 2 In the range of 25-30 ℃, z 3 Is in the range of 240min-350min.
6. The method for improving localized anomalies in flatness of a silicon carbide substrate of claim 5, wherein the 4inch semi-insulating substrate thickness control range is: 490 μm is less than or equal to h- (y) 1 +y 2 )≤515μm；
The thickness control range of the 6inch semi-insulating substrate is as follows: 490 μm is less than or equal to h- (y) 1 +y 2 )≤520μm；
The thickness control range of the 6inch conductive substrate is as follows: h- (y) with a diameter of 330 mu m or less 1 +y 2 ) Less than or equal to 375 mu m, and h is the thickness of the substrate tested in the first step.
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| CN214519543U (en) * | 2020-09-30 | 2021-10-29 | 郑州合晶硅材料有限公司 | Single-chip wafer bearing base for polishing |
| CN116352899A (en) * | 2022-11-30 | 2023-06-30 | 安徽微芯长江半导体材料有限公司 | Treatment method for cutting head and tail pieces of silicon carbide crystal |
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2023
- 2023-09-26 CN CN202311248210.8A patent/CN117174572B/en active Active
Patent Citations (7)
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|---|---|---|---|---|
| US20060057850A1 (en) * | 2004-09-10 | 2006-03-16 | Britt Jeffrey C | Method of manufacturing carrier wafer and resulting carrier wafer structures |
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