CN117174024B - Method for reducing overall power consumption of OLED display panel - Google Patents
Method for reducing overall power consumption of OLED display panel Download PDFInfo
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Abstract
The invention provides a method for reducing the overall power consumption of an OLED display panel, which is characterized in that the overall power consumption is further reduced by controlling the grid reset end of a driving tube in a non-display area pixel driving circuit to carry out driving current and/or driving voltage, and normal display is not influenced.
Description
Technical Field
The invention relates to the technical field of OLED display, in particular to a method for reducing the overall power consumption of an OLED display panel.
Background
An OLED Organic Light-Emitting Diode (OLED) is also called an Organic laser display, an Organic Light-Emitting semiconductor. Is found in the laboratory in 1979 by professor Deng Qingyun of american chinese (child w.tang). OLED display technology has the advantages of self-luminescence, wide viewing angle, almost infinite contrast, low power consumption, extremely high reaction speed and the like, and is widely applied.
Low power consumption has been a general pursuit in the art, and in the prior art, a main means of reducing power consumption is to reduce the voltages of the OLED anode voltage (PVDD), the OLED cathode voltage (PVEE), the compensation voltage (Vdata) and the like of the pixel driving circuit, or to increase the luminous efficiency of OLED (i.e. generate a large brightness with a small current) so as to achieve low power consumption. Currently, power consumption is reported to be reduced by reducing the voltage at the gate voltage reset terminal (Vint 1) of the drive tube in the pixel circuit.
Disclosure of Invention
The invention aims to provide a method for reducing the overall power consumption of an OLED display panel, which further reduces the power consumption on the premise of ensuring that display is free from abnormality.
In order to achieve the above object, the present invention is realized by the following technical scheme:
a method for reducing the overall power consumption of an OLED display panel comprises the following steps:
1) Establishing a first control signal for switching the output mode;
2) In a refresh frame, the first control signal starts with a low level, and corresponds to a certain moment in the VBP phase of the horizontal synchronization clock signal, the first control signal switches from the low level to the high level and keeps the high level until the end of the data valid phase, and at the end moment of the data valid phase, the first control signal switches from the high level to the low level and keeps the low level until the end of the refresh frame; wherein, a period of the horizontal synchronous clock signal is sequentially composed of a VBP phase, a data valid phase and a VFP phase;
3) In a high level stage of the first control signal, a grid voltage reset end of a driving tube in the pixel driving circuit selects a normal output mode;
And in a low level stage of the first control signal, a grid voltage reset end of a driving tube in the pixel driving circuit selects a low power consumption output mode.
Further, the normal output mode is to normally display a voltage value and a current value required for the gate voltage reset terminal of the driving tube.
Further, in the low power consumption output mode, the voltage of the gate voltage reset terminal is smaller than the voltage of the normal output mode.
Further, in the low power consumption output mode, the current of the gate voltage reset terminal is smaller than the current of the normal output mode.
Further, the pixel driving circuit is 7T1C or 8T1C.
Further, step 2) further includes, in the non-refresh frame, the first control signal is at a low level.
Further, the method is applied to LTPO pixel circuits.
Compared with the prior art, the invention has the following advantages:
the invention can further reduce the power consumption on the premise of ensuring that the screen display is not abnormal.
Drawings
For a clearer description of the technical solutions of the present invention, the drawings that are needed in the description will be briefly introduced below, it being obvious that the drawings in the following description are one embodiment of the present invention, and that, without inventive effort, other drawings can be obtained by those skilled in the art from these drawings:
FIG. 1 is a schematic diagram of a 7T1C circuit;
Fig. 2 shows the display area and non-display area currents.
FIG. 3 is a schematic diagram of the operation timing diagram of the present invention.
FIG. 4 is a schematic diagram of the operation timing diagram of the present invention at LTPO.
Detailed Description
The following provides a further detailed description of the proposed solution of the invention with reference to the accompanying drawings and detailed description. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for the purpose of facilitating and clearly aiding in the description of embodiments of the invention. For a better understanding of the invention with objects, features and advantages, refer to the drawings. It should be understood that the structures, proportions, sizes, etc. shown in the drawings are for illustration purposes only and should not be construed as limiting the invention to the extent that any modifications, changes in the proportions, or adjustments of the sizes of structures, proportions, or otherwise, used in the practice of the invention, are included in the spirit and scope of the invention which is otherwise, without departing from the spirit or essential characteristics thereof.
Fig. 1 shows a 7T1C pixel circuit comprising 7 TFTs and 1 capacitor, where M3 is a drive tube, vint1 terminal is a drive tube gate reset terminal for voltage reset of the N1 node; vint2 is the OLED anode reset terminal for voltage reset of the OLED anode terminal.
In a general driving circuit, the N1 point and the anode terminal of the OLED share one input terminal, i.e., vint1 and Vint2 are one port (hereinafter referred to as Vint 1/2).
The OLED display panel generally includes a display region (ACTIVE AREA) and a non-display region (porch area). In the non-display area, since the panel GOA has no toggle, the dc state is always maintained, and at this time, the voltage of Vint1/2 in the pixel circuit 7T1C is not actually written into the pixel circuit of the panel, but due to the parasitic resistance capacitance inside the panel and the parasitic capacitance of the TFT, a certain current still exists in Vint1/2 in the non-display area, as shown in fig. 2. Clearly, this current is not only helpful in displaying, but also has additional power dissipation, which is undesirable. Further, the current probe is used to measure four turns of wire, the current is about 4mA in the active area (i.e. the display area), the current is about 3.375mA in the non-display area, and the voltage of Vref is-3V, so that the power consumption p= Pactive + Pporch =4 (-3) +3.375 (-3) = 22.125mw in the next frame can be calculated.
In order to further reduce power consumption, the application provides a method for reducing the overall power consumption of an OLED display panel, which comprises the following steps:
1) Establishing a first control signal for switching the output mode;
2) In a refresh frame, the first control signal starts with a low level, and corresponds to a certain moment in the VBP phase of the horizontal synchronization clock signal, the first control signal switches from the low level to the high level and keeps the high level until the end of the data valid phase, and at the end moment of the data valid phase, the first control signal switches from the high level to the low level and keeps the low level until the end of the refresh frame; wherein, a period of the horizontal synchronous clock signal is sequentially composed of a VBP phase, a data valid phase and a VFP phase;
3) In a high level stage of the first control signal, a grid voltage reset end of a driving tube in the pixel driving circuit selects a normal output mode;
And in a low level stage of the first control signal, a grid voltage reset end of a driving tube in the pixel driving circuit selects a low power consumption output mode.
Optionally, the normal output mode is a voltage value and a current value required for normally displaying the gate voltage reset terminal of the driving tube.
Optionally, in the low power consumption output mode, the voltage of the gate voltage reset terminal is smaller than the voltage of the normal output mode.
Optionally, in the low power consumption output mode, a current of the gate voltage reset terminal is smaller than a current of the normal output mode.
Optionally, the pixel driving circuit is 7T1C or 8T1C.
Optionally, step 2) further includes, in the non-refresh frame, the first control signal is at a low level.
Fig. 3 is a schematic diagram of an operation timing diagram of the present invention, and as shown in fig. 3, taking a frame as an example, three signals are included: the control signal 30 is a newly built control signal for switching the working mode.
Wherein, one period of the horizontal synchronization clock signal 20 is composed of a VBP phase 201, a data valid phase 202 and a VFP phase 203; wherein the VBP phase 201 and the VFP phase 203 correspond to non-display areas, and the data valid phase 202 corresponds to a display area.
One cycle of the control signal 30 is composed of a first low level stage 301, a high level stage 302, and a second low level stage 303 in this order.
In one period of one display frame, i.e. the vertical synchronization clock signal 10, the first control signal 30 starts as a first low level stage 301, and at a certain time 204 of the VBP stage 201, the control signal 30 is pulled up, i.e. changed from the first low level stage 301 to a high level stage 302, the high level stage 302 being kept to the end of the data valid stage 202 of the horizontal synchronization clock signal 20, i.e. at the end of the data valid stage 202, the high level stage 302 is changed to a second low level stage 301 and kept to the end of the present frame.
In the high level stage 302 of the first control signal 30, the driving voltage and driving current at the Vint1/2 end of 7T1C or 8T1C are set to the values required for normal display, so as to ensure normal display of the frame, i.e. the same as the value of Vint1/2 in the data valid stage 202, for example, the driving current is 4mA, and the driving voltage is-3V.
In the first low level stage 301 and the second low level stage 303, the driving voltage and/or driving current at Vint1/2 end of 7T1C or 8T1C is reduced, and the specific value may be half of the value required for normal display, for example, the driving current is 2mA, and the driving voltage is-3V.
Obviously, compared with 22.125mw in the prior art, the power consumption is reduced by 18.6%, and it is seen that adjusting the state of the non-display area is very helpful for power consumption.
It should be noted that the present invention is not limited to specific values and adjustment methods of the driving current and voltage values, and the values are used herein by way of example, and specific adjustment methods may be implemented using well-known techniques.
Also, referring to fig. 3, a control signal may be additionally provided to control the time 204 at which the first control signal 30 is pulled up in the drawing, and the signal may include an input terminal, and a specific pull-up time may be input by the user. The signal is not particularly limited herein.
Optionally, the method is applied to LTPO pixel circuits.
Fig. 4 shows a schematic diagram of the operation sequence of the present invention in LTPO mode, taking a 4 frame display as an example, it is first explained that Vint1 and Vint2 are often applied with different voltages in a LTPO pixel circuit, and Vint3 is also introduced in a LTPO pixel circuit for resetting the N2 node.
As shown in fig. 4, includes a horizontal synchronizing clock signal 10, a vertical synchronizing clock signal 20, a first control signal 30, and a second control signal 40. The horizontal synchronizing clock signal 10 has 4 periods, namely, 4 frames: the first frame 101, the second frame 102, the third frame 103 and the fourth frame 104, the first frame 101 and the fourth frame 104 are refresh frames, and the second frame 102 and the third frame 103 are non-refresh frames; and, the first control signal 30 is used for adjusting the voltage of the Vint1 terminal, and the second control signal 40 is used for adjusting the voltages of the Vint2 and Vint3 terminals (hereinafter referred to as Vint 2/3).
The second control signal 40 remains identical to the first control signal 30 corresponding to the first frame 101 and the fourth frame 104, i.e. the refresh frame phase;
the second control signal 40 corresponds to the second frame 102 and the third frame 103, i.e. the non-refresh frame phase, and is identical to the signal when refreshing the frame, i.e. the second control signal 40 is a periodic signal with the signal when refreshing the frame being one period.
The method provided by the invention can further reduce the overall power consumption under the condition that the OLED display is not abnormal.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described in detail through the foregoing description of the preferred embodiment, it should be understood that the foregoing description is not to be considered as limiting the invention. Many modifications and substitutions of the present invention will become apparent to those of ordinary skill in the art upon reading the foregoing. Accordingly, the scope of the invention should be limited only by the attached claims.
Claims (3)
1. A method for reducing the overall power consumption of an OLED display panel is characterized by comprising the following steps of
The method comprises the following steps:
1) Establishing a first control signal for switching the output mode;
2) In a refresh frame, the first control signal starts with a low level, and corresponds to a certain moment in the VBP phase of the horizontal synchronization clock signal, the first control signal switches from the low level to the high level and keeps the high level until the end of the data valid phase, and at the end moment of the data valid phase, the first control signal switches from the high level to the low level and keeps the low level until the end of the refresh frame; wherein, a period of the horizontal synchronous clock signal is sequentially composed of a VBP phase, a data valid phase and a VFP phase;
3) In a high level stage of the first control signal, a grid voltage reset end of a driving tube in the pixel driving circuit selects a normal output mode;
in a low level stage of the first control signal, a grid voltage reset end of a driving tube in the pixel driving circuit selects a low power consumption output mode;
The normal output mode is to normally display the voltage value and the current value required by the grid voltage reset end of the driving tube;
In the low-power output mode, the current of the grid voltage reset end is smaller than that of the normal output mode;
The pixel driving circuit is 7T1C or 8T1C;
and in the low-power-consumption output mode, the voltage of the grid voltage reset terminal is smaller than that of the normal output mode.
2. The method of claim 1, wherein step 2) further comprises, during a non-refresh frame, the first control signal being low.
3. A method as claimed in any one of claims 1 to 2, applied in LTPO pixel circuits.
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| CN202311173950.XA CN117174024B (en) | 2023-09-12 | 2023-09-12 | Method for reducing overall power consumption of OLED display panel |
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| CN202311173950.XA CN117174024B (en) | 2023-09-12 | 2023-09-12 | Method for reducing overall power consumption of OLED display panel |
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Citations (4)
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|---|---|---|---|---|
| CN110047432A (en) * | 2019-05-30 | 2019-07-23 | 京东方科技集团股份有限公司 | A kind of pixel circuit, its driving method, display panel and display device |
| CN110890068A (en) * | 2019-11-28 | 2020-03-17 | 南京中电熊猫平板显示科技有限公司 | Pixel driving circuit control system and method |
| CN112967653A (en) * | 2019-12-11 | 2021-06-15 | 厦门天马微电子有限公司 | Display panel and display device |
| CN215578568U (en) * | 2021-06-24 | 2022-01-18 | 京东方科技集团股份有限公司 | Display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR102288351B1 (en) * | 2014-10-29 | 2021-08-11 | 삼성디스플레이 주식회사 | Display apparatus and driving method thereof |
| KR20200033359A (en) * | 2018-09-19 | 2020-03-30 | 삼성디스플레이 주식회사 | Display device and method of driving the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110047432A (en) * | 2019-05-30 | 2019-07-23 | 京东方科技集团股份有限公司 | A kind of pixel circuit, its driving method, display panel and display device |
| CN110890068A (en) * | 2019-11-28 | 2020-03-17 | 南京中电熊猫平板显示科技有限公司 | Pixel driving circuit control system and method |
| CN112967653A (en) * | 2019-12-11 | 2021-06-15 | 厦门天马微电子有限公司 | Display panel and display device |
| CN215578568U (en) * | 2021-06-24 | 2022-01-18 | 京东方科技集团股份有限公司 | Display device |
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Address after: Room 10-401, No. 2846 Xingang East Road, Haizhu District, Guangzhou City, Guangdong Province, 510330 (Office only) Patentee after: Weidu Microelectronics (Guangdong) Co.,Ltd. Country or region after: China Address before: 201306 building C, No. 888, Huanhu West 2nd Road, Lingang New District, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Patentee before: Weichuang Microelectronics (Shanghai) Co.,Ltd. Country or region before: China |
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