CN117170996B - Dynamic reconfigurable on-board processing system evaluation platform and method - Google Patents
Dynamic reconfigurable on-board processing system evaluation platform and method Download PDFInfo
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Abstract
The invention provides an evaluation platform and an evaluation method for a dynamic reconfigurable on-board processing system, which relate to the technical field of on-board processing technology and on-board processing evaluation. The invention provides a solution for improving the processing capacity of the satellite and optimizing the processing hardware framework of the satellite.
Description
Technical Field
The invention relates to the technical field of on-board processing and on-board processing evaluation, in particular to a dynamic reconfigurable on-board processing system evaluation platform and method.
Background
A dynamically reconfigurable on-board processing system refers to a processing system that can reconfigure reconfigurable devices at run-time. Processing systems can be classified into coarse-grained reconfigurable systems and fine-grained reconfigurable systems according to the granularity of the system. The coarse-granularity reconfigurable system is a processing system which consists of heterogeneous computing chips and can dynamically reconfigure software, and granularity is thinned to the first level of the heterogeneous computing chips. The fine granularity reconfigurable system is a processing system designed based on an energy-efficient dynamic reconfigurable chip, and granularity is thinned to a reconfigurable processing unit in the chip.
Because the traditional on-board processing system is designed according to specific requirements, the problems of single processing function, long development period and poor flexibility generally exist, and therefore, the novel dynamic reconfigurable on-board processing system facing general processing requirements in recent years gradually becomes the main stream of the on-board processing field.
The novel dynamic reconfigurable on-board processing system has various application scenes and complex technical indexes, and has great difficulty in evaluation and verification. At present, the research on the test and evaluation of the on-board processing system at home and abroad is in a starting stage, and a systematic on-board processing system evaluation platform is not established. Only the ground detection equipment aiming at specific projects can carry out simple test and verification on the functions and performance indexes of the on-board processing, and can not comprehensively and systematically test and evaluate all indexes of the on-board processing system, thereby providing a solution for optimizing on-board processing software and hardware.
Disclosure of Invention
In order to solve the technical problems, the invention provides a dynamic reconfigurable on-board processing system evaluation platform and a method. The dynamic reconfigurable on-board processing system evaluation platform is used for simulating a dynamic reconfigurable on-board processing system, building a test platform, performing test evaluation on a processing algorithm and a hardware architecture of the on-board processing system, and giving comprehensive evaluation on the processing algorithm and the processing hardware architecture, so that a solution is provided for improving the on-board processing capability and optimizing the on-board processing hardware architecture.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the dynamic reconfigurable on-board processing system evaluation platform comprises a load data acquisition simulation subsystem, an on-board processing simulation subsystem and an on-board processing data recording analysis subsystem; the load data acquisition simulation subsystem, the on-board processing simulation subsystem and the on-board processing data recording analysis subsystem are connected in series to form a closed loop system for simulating on-board processing data flow; the load data acquisition simulation subsystem is used for completing the time sequence of simulating the load sending data, the standardization of the load data format and the conversion of the data format; the on-board processing simulation subsystem is used for completing the software and hardware cooperative work process of the on-board processing system; the on-board processing data record analysis subsystem is used for completing the collection and processing of high-speed data, SAR image quality analysis and signal time-frequency domain analysis.
Further, the dynamically reconfigurable on-board processing system evaluation platform comprises hardware and software; the hardware comprises a standardized test bus and various heterogeneous computing hardware; the software realizes the modularization and functional design of the bottom hardware drive, provides algorithm APIs for different test scenes and realizes hierarchical design.
Further, 5 types of processing chips, CPU, GPU, FPGA, NPU and DSP, respectively, were adapted.
Further, a reconfigurable processing chip is included.
Further, the load data acquisition analog subsystem comprises a processor platform, a data transmission unit and a high-performance storage unit.
Further, the on-board processing simulation subsystem comprises a processor platform, a data transmission unit, a GPU computing unit, an FPGA computing unit, an NPU computing unit and a DSP computing unit.
Further, the on-board processing data record analysis subsystem comprises a processor platform, a data transmission unit and a high-performance storage unit.
The invention also provides an evaluation method of the evaluation platform of the dynamic reconfigurable on-board processing system, which is used for connecting the load data acquisition simulation subsystem, the on-board processing simulation subsystem and the on-board processing data record analysis subsystem in series in the evaluation platform of the dynamic reconfigurable on-board processing system when evaluating the processing algorithm of the on-board processing system, loading the algorithm to be evaluated into the on-board processing simulation subsystem, and carrying out prototype verification and performance evaluation on different algorithms by utilizing various heterogeneous computing hardware in the on-board processing simulation subsystem;
the method comprises the steps that load data are obtained, excitation data required by an algorithm are generated by an analog subsystem, a corresponding data set is obtained from a data cloud platform according to an application range of the algorithm, the load data required by an on-board processing algorithm are generated by the data set, then the load data are converted into a standard format, a time sequence of load transmission is simulated, and the load data are transmitted to the on-board processing analog subsystem to serve as the excitation data required by the algorithm; simultaneously, the load data acquisition simulation subsystem generates a synchronous trigger signal to ensure the time synchronization of the three subsystems so as to calculate the processing delay;
after receiving the excitation data, the on-board processing simulation subsystem calculates the excitation data by using an on-board processing algorithm to be evaluated, and after calculation, sends a processing result to the on-board processing data record analysis subsystem;
after receiving the processing result, the on-board processing data recording and analyzing subsystem records the processing result, analyzes and evaluates the algorithm performance index, calculates the processing delay of the whole evaluation process, simultaneously gives an evaluation conclusion, and a user judges whether the algorithm performance and the processing delay meet the requirements according to the evaluation conclusion and formulates the optimization scheme of the next step.
The invention also provides an evaluation method of the dynamic reconfigurable on-board processing system evaluation platform, which is used for connecting a load data acquisition simulation subsystem, a tested on-board processing system and an on-board processing data record analysis subsystem in series when evaluating the hardware architecture performance of the on-board processing system, simulating the data stream transmission and calculation process of on-board processing, respectively running a plurality of different on-board processing general algorithms by using the hardware architecture of the on-board processing system, and evaluating the performance of the hardware architecture of the on-board processing system according to the processing result;
the method comprises the steps that load data are obtained, excitation data required by an algorithm are generated by a simulation subsystem, a corresponding data set is obtained from a data cloud platform according to an application range of the algorithm, the load data required by an on-board processing algorithm are generated by the data set, then the load data are converted into a standard format, a time sequence of load transmission is simulated, and the load data are transmitted to a hardware architecture of a tested on-board processing system to be used as the excitation data required by the algorithm; simultaneously, the load data acquisition simulation subsystem generates a synchronous trigger signal to ensure the time synchronization of the three subsystems so as to calculate the processing delay;
after the hardware architecture of the tested on-board processing system receives the excitation data, calculating the excitation data by using an on-board processing general algorithm, and after calculation, transmitting a processing result to an on-board processing data record analysis subsystem;
after receiving the processing result, the on-board processing data recording and analyzing subsystem records the processing result, analyzes the performance index of the hardware architecture, calculates the processing delay of the whole evaluation process, gives an evaluation conclusion, and a user judges whether the performance of the hardware architecture meets the requirement according to the evaluation conclusion and formulates the next optimization scheme.
The invention also provides an evaluation method of the dynamic reconfigurable on-board processing system evaluation platform, which is used for connecting a load data acquisition simulation subsystem, a tested on-board processing system comprising a hardware architecture and a processing algorithm and an on-board processing data record analysis subsystem in series to simulate the data stream transmission and calculation process of on-board processing when the on-board processing system is evaluated;
the method comprises the steps that load data are obtained, excitation data required by an algorithm are generated by a simulation subsystem, a corresponding data set is obtained from a data cloud platform according to an application range of the algorithm, the load data required by a processing algorithm are generated by the data set, then the load data are converted into a standard format, a time sequence of load transmission is simulated, and the load data are transmitted to hardware of a tested satellite processing system to be used as the excitation data required by the algorithm; simultaneously, the load data acquisition simulation subsystem generates a synchronous trigger signal to ensure the time synchronization of the three subsystems so as to calculate the processing delay;
after receiving excitation data, the tested on-board processing system comprising a hardware architecture and a processing algorithm calculates the excitation data by using an internally loaded algorithm, and after calculation, sends a processing result to an on-board processing data record analysis subsystem;
after receiving the processing result, the on-board processing data recording and analyzing subsystem records the processing result, analyzes the performance index of the processing system, calculates the processing delay of the whole evaluation process, gives an evaluation conclusion, and a user judges whether the performance of the processing system meets the requirement according to the evaluation conclusion and formulates the next optimization scheme.
The beneficial effects are that:
(1) The invention builds the dynamic reconfigurable on-board processing evaluation platform for the first time, provides a high-efficiency general test evaluation platform for the dynamic reconfigurable on-board processing system, and solves the problem that the system lacks a high-efficiency general test means currently;
(2) The evaluation platform has high-performance reconfigurable hardware processing resources, fully exerts the calculation and storage performances of the hardware platform, and meets the requirements of different application scenes and algorithms on a processing architecture;
(3) The invention utilizes the evaluation platform to test and evaluate the hardware architecture and the chip of the processing system, and screens out excellent processing chips and processing architectures according to evaluation conclusion, thereby being capable of providing a hardware solution of a dynamic reconfigurable processor with high calculation power, high cache and high bandwidth, breaking through the limitations of low energy efficiency, limited capacity, high use threshold and the like of the traditional chips, improving the design core technology and product development capability of the on-board processing software and hardware architecture, and providing basis for the architecture design of the dynamic reconfigurable on-board processing evaluation platform;
(4) According to the invention, the characteristics of different on-board processing algorithms, such as algorithm processing performance, processing timeliness and the like, are utilized to test the different on-board processing algorithms, and a proper algorithm is screened out for an on-board processing system;
(5) The method simulates the satellite load data acquisition process and provides a data source for on-board processing;
(6) The invention simulates the software and hardware cooperative work process of the dynamic reconfigurable on-board processing system, and verifies the processing algorithm and the processing chip;
(7) The dynamic reconfigurable on-board processing simulation evaluation technology provided by the invention is researched for the first time at home and abroad, is oriented to comprehensive capability evaluation of various on-board processing chips, processing algorithms and processing systems, and has high universality in the on-board processing evaluation field. Under various specific application scenes, the method has guiding significance for the design and optimization of the on-board processing system.
Drawings
FIG. 1 is a schematic diagram of an on-board process test apparatus;
FIG. 2 is a block diagram of a dynamically reconfigurable on-board processing evaluation platform of the present invention;
FIG. 3 is a block diagram of a processing algorithm evaluation flow;
FIG. 4 is a block diagram of a processing hardware architecture evaluation flow;
FIG. 5 is a block diagram of a processing system performance evaluation flow.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The dynamic reconfigurable on-board processing evaluation platform is a generalized and automatic evaluation platform, and the design of the dynamic reconfigurable on-board processing evaluation platform comprises two aspects of hardware design and software design.
In hardware design, the design is based on the principle of maximum compatibility so as to meet the requirements of different test scenes, and the method comprises the following steps:
1) Adopting a standardized test bus to carry out detailed classification on various signals to be tested of the on-board processing system, and distributing a sufficient number of test channels;
2) Based on the characteristic that the on-board processing system (or the tested equipment) relates to mass data, the data storage, data caching, data access and data transmission capacity of the hardware of the evaluation platform are improved;
3) Based on the characteristics of various processing algorithms, various heterogeneous computing hardware is equipped to adapt to different computing demands of an evaluation platform.
In the aspect of software design, each functional unit is modularized, and an evaluation platform is built by taking a software defined evaluation system as a direction, and the method comprises the following steps:
1) The bottom hardware drive modularization and functional design are carried out, so that the bottom hardware drive modularization and functional design can be conveniently invoked at any time according to requirements;
2) Aiming at different test scenes, rich software, algorithm APIs and easy-to-use test examples are provided, and the test efficiency is improved;
3) Unified standard, design by adopting layering and opening ideas, and improve the compatibility of software.
In addition, the application scene of the on-board processing is complex, the implementation methods of the processing algorithms have great difference, and how to select processing chips with better adaptability for different algorithms is an important problem. The evaluation platform contains various heterogeneous computing resources, can simulate the processing environment of a plurality of types of processing chips, and can rapidly and intuitively evaluate the performance of the same algorithm realized on different types of processing chips.
The evaluation platform is intended to accommodate 5 types of processing chips, including CPU, GPU, FPGA, NPU and DSPs. With subsequent iterations and types of processing chip performance increasing, more types of processing chips can be expanded. And according to specific application scenes, the reconfigurable processing chip can be customized, so that the processing performance and the energy consumption ratio are improved.
The developer can rapidly conduct secondary development on the evaluation platform by using the same algorithm and deploy the secondary development into the corresponding computing unit, and rapidly evaluate the processing performance and timeliness.
As shown in fig. 2, the architecture of the dynamically reconfigurable on-board processing evaluation platform of the present invention is mainly constructed according to the data flow of the on-board processing system. As shown in fig. 1, the on-board processing flow generally includes: the load data simulation generator of a specific project acquires data, then the data is sent to the data recorder through the on-board processing system (or tested equipment), and finally the data is processed and analyzed through processing result analysis software, so that an on-board processing flow corresponding to satellite load acquisition data-on-board processing data-data downloading analysis is provided, and the assessment platform has the capabilities of simulating the load acquisition data process, simulating the on-board processing system, recording and analyzing the on-board processing data, so that the architecture of the assessment platform is divided into 3 subsystems according to functions, namely, the load data acquisition simulation subsystem, the on-board processing simulation subsystem and the on-board processing data recording analysis subsystem are respectively arranged.
The load data acquisition simulation subsystem mainly completes the time sequence of simulating the load sending data, the standardization of the load data format and the conversion of the data format. The on-board processing simulation subsystem completes the software and hardware cooperative work process of the on-board processing system. The on-board processing data recording and analyzing subsystem is used for completing the collection and processing of high-speed data, SAR image quality analysis, signal time-frequency domain analysis and the like.
The assessment platform is designed in the form of a server cabinet, and each subsystem is designed in the form of a rack-mounted server and is installed in the cabinet. The evaluation platform can form a closed loop system simulating on-board processing data flow by connecting all subsystems in series, so that the functions of processing algorithm prototype verification and the like are realized. Meanwhile, the evaluation platform supports access of an on-board processing system (or tested equipment), and the tested equipment can be connected with the evaluation platform through a cable to realize performance evaluation of the tested processing system. Each subsystem in the system communicates (i.e., is interconnected) with a remote server (e.g., a data cloud platform) via a tera ethernet network, and a user can remotely monitor the assessment platform.
Each subsystem is designed as a rack-mounted general server architecture, utilizes powerful and highly dense and scalable computing and storage capabilities for system support, has sufficient computing, memory, storage and connection options, and can be flexibly configured for specific typical applications.
The functions implemented by the assessment platform include: 1) Processing multisource collection and standardization of data; 2) Model simulation and prototype verification of a microwave remote sensing imaging algorithm; 3) Model simulation and prototype verification of a remote sensing image target detection and identification algorithm; 4) Performance index evaluation of an on-board processing system (external device under test).
The load data acquisition simulation subsystem consists of the following three parts, as shown in table 1.
TABLE 1
The load data acquisition analog subsystem bears the following functions in the system: 1) The format of the load data is standardized; 2) Time sequence simulation of load data transmission; 3) Initiating tasks for algorithmic prototype verification or processing system evaluation.
In terms of software, the load data acquisition simulation subsystem runs system task management software and data format standardization software for initiating test evaluation tasks and load data format standardization. The main functions of the system task management software are as follows:
1) Interaction with a user: the user initiates tasks, formats system data, selects processing modules and the like in the software;
2) Initiating a task: the data to be processed is sent to an on-board processing simulation subsystem or tested equipment, and information processing control software and data analysis software are called to complete tasks;
3) Monitoring and recording the working state of the system to form a working log: monitoring the system state in the task process, and forming a work log together with the operation record;
4) Local management of system data: managing local data related to each task;
5) Formatting of system data: formatting the data of different models to generate standard format data. The main functions of the data format normalization software are as follows: (a) unifying the formats of the payload data: the method comprises the steps of unifying the formats of load data of different on-board processing systems by using a load data format standard, wherein the load data comprises acquisition signals, images, auxiliary data and the like; (b) payload data information marking: and carrying out information management marking on the input load data, wherein marking information comprises information such as load data type, generation time, scene, size and the like, and establishing a complete load database.
The on-board processing simulation subsystem consisted of the following six parts, as shown in table 2.
TABLE 2
The on-board processing simulation subsystem bears the following functions in the system: 1) Model simulation and prototype verification of a microwave remote sensing imaging algorithm; 2) Model simulation and prototype verification of a remote sensing image target detection and identification algorithm; 3) Model simulation and prototype verification of an electronic reconnaissance and countermeasure algorithm; 4) Model simulation and prototype verification of radar detection algorithms.
In terms of software, the on-board processing simulation subsystem runs on-board processing simulation control software, which is used for controlling a processing unit to load and transmit data streams, and has the main functions as follows:
1) Receiving system tasks: receiving tasks issued by system task management software, wherein the tasks comprise control parameters such as module selection, data flow control modes and the like;
2) And (3) module loading: loading the selected processing module;
3) Data flow control: and controlling different processing modules to realize data flow control. And outputting the processing result to data record analysis software.
The on-board processing data record analysis subsystem consists of the following three parts, as shown in table 3.
TABLE 3 Table 3
The on-board processing data record analysis subsystem is used for carrying out the following functions in the system: 1) Processing system data records; 2) Performance evaluation analysis of the processing system; 3) Calculating the processing delay of the processing system; 4) Evaluating performance of a microwave remote sensing imaging algorithm; 5) Performing statistical analysis on the target detection and identification results of the remote sensing image; 6) Evaluating the performance of an electronic reconnaissance algorithm; 7) Evaluating performance of a radar detection algorithm; 8) And (5) evaluating the performance of the electronic countermeasure algorithm.
In terms of software, the on-board processing data recording and analyzing subsystem runs data recording software and data analyzing software, and is used for recording and analyzing processing data, and the main functions of the data recording software comprise: 1) Receiving system tasks: receiving tasks issued by system task management software, and completing different data analysis tasks; 2) And (3) data recording: recording the processed data sent by the information processing subsystem to the on-board processed data recording and analyzing subsystem.
The main functions of the data analysis software include: 1) Data analysis: performing data analysis on the processed data, including processing delay analysis of imaging and target detection and identification, detection rate and false alarm rate analysis of target detection, accuracy analysis of target identification and classification and the like; 2) Forming an analysis report: and forming an analysis report for the analysis result.
Based on abundant hardware resources of the evaluation platform, the system has the evaluation verification capability of processing various typical application scenes on the satellite. Specifically, the evaluation platform has the evaluation verification capability of a typical application scene correlation algorithm, and the evaluation verification capability of various functions and performance indexes of the on-board processing equipment. The evaluation processes of the on-board processing algorithm, the hardware architecture and the on-board processing system are respectively described below.
When the evaluation platform is used for evaluating the on-board processing algorithm, the load data acquisition simulation subsystem, the on-board processing simulation subsystem and the on-board processing data record analysis subsystem in the platform are connected in series, the algorithm to be evaluated is loaded into the on-board processing simulation subsystem, and prototype verification and performance evaluation can be carried out on various typical algorithms related to different projects by utilizing powerful heterogeneous computing resources in the on-board processing simulation subsystem. A block flow diagram for evaluating an on-board processing algorithm is shown in fig. 3.
The load data acquisition simulates the excitation data required by the subsystem generation algorithm. Firstly, acquiring a corresponding data set from a data cloud platform (shown in figure 2) according to an algorithm application range, generating load data required by an on-board processing algorithm by using the data set, converting the load data into a standard format, simulating a time sequence of load transmission, and transmitting the load data to an on-board processing simulation subsystem as excitation data required by the algorithm. Meanwhile, the load data acquisition analog subsystem can generate a synchronous trigger signal, so that time synchronization of the three subsystems is ensured to calculate processing delay.
After receiving the excitation data, the on-board processing simulation subsystem calculates the excitation data by using an on-board processing algorithm to be evaluated, and sends a processing result to the data record analysis subsystem after calculation is completed. Here, the on-board processing algorithm to be evaluated needs to be transplanted into the on-board processing simulation subsystem in advance. Because the system has abundant heterogeneous computing resources and software development kits, a developer can rapidly transplant an algorithm to be evaluated into the on-board processing simulation subsystem.
After receiving the processing result, the on-board processing data recording and analyzing subsystem records the processing result, analyzes and evaluates the algorithm performance index and calculates the processing delay of the whole flow, and meanwhile, gives an evaluation conclusion, and a user can judge whether the algorithm performance and the processing delay meet the requirements according to the evaluation conclusion and formulate the next optimization scheme.
Besides the capability of evaluating algorithms, the evaluation platform also has the capability of evaluating the performance of the on-board processing hardware architecture. When the evaluation platform is used for evaluating the on-board processing hardware architecture, a user can connect the load data acquisition simulation subsystem, the on-board processing system (tested equipment) and the on-board processing data record analysis subsystem in series to simulate the data stream transmission and calculation process of on-board processing. The test and evaluation of the hardware architecture is mainly to evaluate the performance of the hardware architecture according to the processing result by respectively running a plurality of different on-board processing general algorithms by using the hardware architecture.
As shown in fig. 4, the load data acquisition simulates the excitation data required by the subsystem generation algorithm. Firstly, corresponding data sets are acquired from a data cloud platform according to an algorithm application range, load data required by an on-board processing algorithm are generated by the data sets, then the load data are converted into a standard format, a time sequence of load transmission is simulated, and the load data are transmitted to a tested on-board processing hardware architecture to be used as excitation data required by the algorithm. Meanwhile, the load data acquisition analog subsystem can generate a synchronous trigger signal, so that time synchronization of the three subsystems is ensured to calculate processing delay.
After receiving the excitation data, the measured on-board processing hardware architecture calculates the corresponding data by using an on-board processing general algorithm, and sends the processing result to an on-board processing data record analysis subsystem after calculation is completed. Here, the general algorithm for processing on the satellite needs to be transplanted into the processing hardware architecture on the satellite to be tested in advance.
After receiving the processing result, the on-board processing data recording and analyzing subsystem records the processing result, analyzes the performance index of the hardware architecture, calculates the processing delay of the whole flow, gives out an evaluation conclusion, and a user can judge whether the performance of the hardware architecture meets the requirement according to the evaluation conclusion and formulate the next optimization scheme.
The evaluation of the on-board processing system refers to the overall test evaluation of the algorithm and hardware architecture. When the evaluation platform is used for evaluating the on-board processing system, a user can connect the load data acquisition simulation subsystem, the on-board processing system (tested equipment comprises a hardware architecture and an algorithm) and the on-board processing data record analysis subsystem in series to simulate the data stream transmission and calculation process of on-board processing.
As shown in fig. 5, the load data acquisition simulates the excitation data required by the subsystem generation algorithm. Firstly, corresponding data sets are acquired from a data cloud platform according to an algorithm application range, load data required by a processing algorithm are generated by the data sets, then the load data are converted into a standard format, the time sequence of load transmission is simulated, and the load data are transmitted to hardware of a tested satellite processing system to be used as excitation data required by the algorithm. Meanwhile, the load data acquisition analog subsystem can generate a synchronous trigger signal, so that time synchronization of the three subsystems is ensured to calculate processing delay.
After receiving the excitation data, the measured on-board processing system calculates the corresponding data by using an internally loaded algorithm, and sends the processing result to the on-board processing data record analysis subsystem after the calculation is completed.
After receiving the processing result, the on-board processing data recording and analyzing subsystem records the processing result, analyzes the performance index of the processing system, calculates the processing delay of the whole flow, gives out an evaluation conclusion, and a user can judge whether the performance of the processing system meets the requirement according to the evaluation conclusion and formulate the next optimization scheme.
It will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (9)
1. The evaluation method of the dynamic reconfigurable on-board processing system is characterized in that the evaluation method is realized through an evaluation platform of the dynamic reconfigurable on-board processing system, and the evaluation platform of the dynamic reconfigurable on-board processing system comprises a load data acquisition simulation subsystem, an on-board processing simulation subsystem and an on-board processing data record analysis subsystem; the load data acquisition simulation subsystem, the on-board processing simulation subsystem and the on-board processing data recording analysis subsystem are connected in series to form a closed loop system for simulating on-board processing data flow; the load data acquisition simulation subsystem is used for completing the time sequence of simulating the load sending data, the standardization of the load data format and the conversion of the data format; the on-board processing simulation subsystem is used for completing the software and hardware cooperative work process of the on-board processing system; the on-board processing data recording and analyzing subsystem is used for completing the collection and processing of high-speed data, SAR image quality analysis and signal time-frequency domain analysis;
when the method is used for evaluating the processing algorithm of the on-board processing system, the load data acquisition simulation subsystem, the on-board processing simulation subsystem and the on-board processing data record analysis subsystem in the dynamic reconfigurable on-board processing system evaluation platform are connected in series, the algorithm to be evaluated is loaded into the on-board processing simulation subsystem, and prototype verification and performance evaluation are carried out on different algorithms by utilizing various heterogeneous computing hardware in the on-board processing simulation subsystem;
the method comprises the steps that load data are obtained, excitation data required by an algorithm are generated by an analog subsystem, a corresponding data set is obtained from a data cloud platform according to an application range of the algorithm, the load data required by an on-board processing algorithm are generated by the data set, then the load data are converted into a standard format, a time sequence of load transmission is simulated, and the load data are transmitted to the on-board processing analog subsystem to serve as the excitation data required by the algorithm; simultaneously, the load data acquisition simulation subsystem generates a synchronous trigger signal to ensure the time synchronization of the load data acquisition simulation subsystem, the on-board processing simulation subsystem and the on-board processing data recording analysis subsystem so as to calculate the processing delay;
after receiving the excitation data, the on-board processing simulation subsystem calculates the excitation data by using an on-board processing algorithm to be evaluated, and after calculation, sends a processing result to the on-board processing data record analysis subsystem;
after receiving the processing result, the on-board processing data recording and analyzing subsystem records the processing result, analyzes and evaluates the algorithm performance index, calculates the processing delay of the whole evaluation process, simultaneously gives an evaluation conclusion, and a user judges whether the algorithm performance and the processing delay meet the requirements according to the evaluation conclusion and formulates the optimization scheme of the next step.
2. The evaluation method of the dynamic reconfigurable on-board processing system is characterized in that the evaluation method is realized through an evaluation platform of the dynamic reconfigurable on-board processing system, and the evaluation platform of the dynamic reconfigurable on-board processing system comprises a load data acquisition simulation subsystem, an on-board processing simulation subsystem and an on-board processing data record analysis subsystem; the load data acquisition simulation subsystem, the on-board processing simulation subsystem and the on-board processing data recording analysis subsystem are connected in series to form a closed loop system for simulating on-board processing data flow; the load data acquisition simulation subsystem is used for completing the time sequence of simulating the load sending data, the standardization of the load data format and the conversion of the data format; the on-board processing simulation subsystem is used for completing the software and hardware cooperative work process of the on-board processing system; the on-board processing data recording and analyzing subsystem is used for completing the collection and processing of high-speed data, SAR image quality analysis and signal time-frequency domain analysis;
when the system is used for evaluating the performance of a hardware architecture of an on-board processing system, a load data acquisition simulation subsystem, a tested on-board processing system and an on-board processing data record analysis subsystem are connected in series, so that the data stream transmission and calculation process of on-board processing are simulated, and the performance of the hardware architecture of the on-board processing system is evaluated according to the processing result by respectively running a plurality of different on-board processing general algorithms by using the hardware architecture of the on-board processing system;
the method comprises the steps that load data are obtained, excitation data required by an algorithm are generated by a simulation subsystem, a corresponding data set is obtained from a data cloud platform according to an application range of the algorithm, the load data required by an on-board processing algorithm are generated by the data set, then the load data are converted into a standard format, a time sequence of load transmission is simulated, and the load data are transmitted to a hardware architecture of a tested on-board processing system to be used as the excitation data required by the algorithm; simultaneously, the load data acquisition simulation subsystem generates a synchronous trigger signal to ensure the time synchronization of the load data acquisition simulation subsystem, the on-board processing simulation subsystem and the on-board processing data recording analysis subsystem so as to calculate the processing delay;
after the hardware architecture of the tested on-board processing system receives the excitation data, calculating the excitation data by using an on-board processing general algorithm, and after calculation, transmitting a processing result to an on-board processing data record analysis subsystem;
after receiving the processing result, the on-board processing data recording and analyzing subsystem records the processing result, analyzes the performance index of the hardware architecture, calculates the processing delay of the whole evaluation process, gives an evaluation conclusion, and a user judges whether the performance of the hardware architecture meets the requirement according to the evaluation conclusion and formulates the next optimization scheme.
3. The evaluation method of the dynamic reconfigurable on-board processing system is characterized in that the evaluation method is realized through an evaluation platform of the dynamic reconfigurable on-board processing system, and the evaluation platform of the dynamic reconfigurable on-board processing system comprises a load data acquisition simulation subsystem, an on-board processing simulation subsystem and an on-board processing data record analysis subsystem; the load data acquisition simulation subsystem, the on-board processing simulation subsystem and the on-board processing data recording analysis subsystem are connected in series to form a closed loop system for simulating on-board processing data flow; the load data acquisition simulation subsystem is used for completing the time sequence of simulating the load sending data, the standardization of the load data format and the conversion of the data format; the on-board processing simulation subsystem is used for completing the software and hardware cooperative work process of the on-board processing system; the on-board processing data recording and analyzing subsystem is used for completing the collection and processing of high-speed data, SAR image quality analysis and signal time-frequency domain analysis;
when the method is used for evaluating the on-board processing system, a load data acquisition simulation subsystem, a tested on-board processing system comprising a hardware architecture and a processing algorithm and an on-board processing data record analysis subsystem in the system are connected in series to simulate the data stream transmission and calculation process of on-board processing;
the method comprises the steps that load data are obtained, excitation data required by an algorithm are generated by a simulation subsystem, a corresponding data set is obtained from a data cloud platform according to an application range of the algorithm, the load data required by a processing algorithm are generated by the data set, then the load data are converted into a standard format, a time sequence of load transmission is simulated, and the load data are transmitted to hardware of a tested satellite processing system to be used as the excitation data required by the algorithm; simultaneously, the load data acquisition simulation subsystem generates a synchronous trigger signal to ensure the time synchronization of the load data acquisition simulation subsystem, the on-board processing simulation subsystem and the on-board processing data recording analysis subsystem so as to calculate the processing delay;
after receiving excitation data, the tested on-board processing system comprising a hardware architecture and a processing algorithm calculates the excitation data by using an internally loaded algorithm, and after calculation, sends a processing result to an on-board processing data record analysis subsystem;
after receiving the processing result, the on-board processing data recording and analyzing subsystem records the processing result, analyzes the performance index of the processing system, calculates the processing delay of the whole evaluation process, gives an evaluation conclusion, and a user judges whether the performance of the processing system meets the requirement according to the evaluation conclusion and formulates the next optimization scheme.
4. A method of evaluating a dynamically reconfigurable on-board processing system according to any of claims 1-3, wherein the dynamically reconfigurable on-board processing system evaluation platform comprises hardware and software; the hardware comprises a standardized test bus and various heterogeneous computing hardware; the software realizes the modularization and functional design of the bottom hardware drive, provides algorithm APIs for different test scenes and realizes hierarchical design.
5. A method of evaluating a dynamically reconfigurable on-board processing system according to any of claims 1-3, characterized in that 5 types of processing chips, CPU, GPU, FPGA, NPU and DSP, respectively, are adapted.
6. A method of evaluating a dynamically reconfigurable on-board processing system according to any of claims 1-3, comprising reconfigurable processing chips.
7. A method of evaluating a dynamically reconfigurable on-board processing system according to any of claims 1-3, wherein the payload data acquisition simulation subsystem comprises a processor platform, a data transfer unit and a high performance storage unit.
8. A method of evaluating a dynamically reconfigurable on-board processing system according to any of claims 1-3, wherein the on-board processing simulation subsystem comprises a processor platform, a data transfer unit, a GPU computing unit, an FPGA computing unit, an NPU computing unit, and a DSP computing unit.
9. A method of evaluating a dynamically reconfigurable on-board processing system according to any of claims 1-3, wherein the on-board processing data record analysis subsystem comprises a processor platform, a data transfer unit and a high performance storage unit.
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