CN117169688A

CN117169688A - Board-level chip testing method and device, storage medium and electronic device

Info

Publication number: CN117169688A
Application number: CN202311117728.8A
Authority: CN
Inventors: 施秋云
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2023-08-31
Filing date: 2023-08-31
Publication date: 2023-12-05

Abstract

The application discloses a testing method and device of a board chip, a storage medium and an electronic device, wherein the testing method of the board chip comprises the following steps: controlling a power supply device connected with the power input end of the board-level chip to be tested to output a preset test voltage, and simultaneously controlling a current value on a load device connected with the power output end of the board-level chip to reach a preset test current; acquiring actual input voltage and actual input current on the power input end of the board-level chip, and simultaneously detecting a voltage value on the power output end of the board-level chip to obtain actual output voltage; according to the test current, the actual input voltage and the actual output voltage, the chip loss parameter, the chip efficiency parameter and the chip operation parameter of the board-level chip are determined, and the problems of lower test efficiency and the like of the board-level chip in the related technology are solved by adopting the technical scheme.

Description

Board-level chip testing method and device, storage medium and electronic device

Technical Field

The embodiment of the application relates to the field of computers, in particular to a method and a device for testing a board-level chip, a storage medium and an electronic device.

Background

Currently, the power consumption of the server CPU (Central Processing Unit ) is increasingly higher, and the high-power consumption CPU requires a main board power supply circuit to carry a larger current. The board-level chip is an integrated circuit chip embedded on the main board and serves as an important device on the main board, and plays a role in regulating voltage between a power supply and an electric load.

Although a series of theoretical parameters are usually marked on the board level chip, the marked theoretical parameter is usually a theoretical value, and related verification is not performed, for example, the chip loss parameter marked on the board level chip is generally obtained through simulation or calculation according to the impedance of the board level chip and the current passing through the chip, after the board level chip is actually deployed, due to the process of the board level chip, the wiring difference, the heat dissipation and other aspects of the motherboard are different, the situation that the parameters shown after the actual deployment are different may occur, and the problems of dead halt, failure, abnormal restarting and the like of a server occur after the actual deployment, so that the actual test of the parameters of the board level chip is critical before the board level chip is deployed, however, the test of the theoretical parameters of the board level chip is single, and each theoretical parameter needs to be welded with different test points and a new test environment after each test is performed, which is time-consuming.

Aiming at the problems of low test efficiency and the like of the board-level chip in the related art, no effective solution is proposed yet.

Disclosure of Invention

The embodiment of the application provides a method and a device for testing a board-level chip, a storage medium and an electronic device, which are used for at least solving the problems of lower testing efficiency and the like of the board-level chip in the related technology.

According to an embodiment of the present application, there is provided a method for testing a board-level chip, including:

controlling a power supply device connected with a power input end of a board-level chip to be tested to output a preset test voltage, and simultaneously controlling a current value on a load device connected with the power output end of the board-level chip to reach a preset test current, wherein the test voltage is larger than or equal to a maximum chip voltage and smaller than or equal to a minimum chip voltage, the maximum chip voltage is a maximum voltage value allowed to be loaded on the board-level chip, the minimum chip voltage is a minimum voltage value allowed to be loaded on the board-level chip, and the test current is smaller than or equal to a maximum load current, and the maximum load current is a maximum current value allowed to be loaded by the load device;

Acquiring actual input voltage and actual input current on the power input end of the board-level chip, and detecting a voltage value on the power output end of the board-level chip to obtain actual output voltage;

according to the test current, the actual input voltage and the actual output voltage determine a chip loss parameter, a chip efficiency parameter and a chip operation parameter of the board-level chip, wherein the chip loss parameter is used for indicating the power loss of the board-level chip, the chip efficiency parameter is used for indicating the power efficiency of the board-level chip, and the chip operation parameter is used for indicating the operation state of the board-level chip.

Optionally, the controlling the power supply device connected to the power input end of the board-level chip to be tested outputs a preset test voltage, including:

obtaining a reference test voltage from a reference test voltage set as the test voltage, wherein the reference test voltage set comprises one or more reference test voltages;

and controlling a power supply device connected with the power input end of the board-level chip to be tested to output the test voltage.

Optionally, before the obtaining a reference test voltage from the reference test voltage set as the test voltage, the method further includes:

Acquiring a normal working voltage corresponding to the board-level chip, wherein the normal working voltage is a voltage which is allowed to be loaded when the board-level chip works normally;

and generating one or more reference test voltages according to the normal working voltage and a first preset proportion to obtain the reference test voltage set.

Optionally, the generating one or more reference test voltages according to the normal working voltage and the first preset proportion includes at least one of the following:

performing addition operation on the normal working voltage and the first target voltage amplitude to obtain the maximum chip voltage; determining the maximum chip voltage as the reference test voltage, wherein the first target voltage amplitude is the product of the normal working voltage and the first preset proportion;

performing subtraction operation on the normal working voltage and the first target voltage amplitude to obtain the minimum chip voltage; determining the minimum chip voltage as the reference test voltage, wherein the first target voltage amplitude is the product of the normal working voltage and the first preset proportion;

and determining the normal working voltage as the reference test voltage.

Optionally, the determining, according to the test current, the actual input voltage and the actual output voltage, a chip loss parameter, a chip efficiency parameter and a chip operation parameter of the board-level chip includes:

determining a difference between the actual input voltage and the actual output voltage as a first difference; determining a product of the actual input current and the first difference as the chip loss parameter;

determining a product of the test current and the actual output voltage as a first value; determining a product of the actual input current and the actual input voltage as a second value; determining a ratio of the first value to the second value as the chip efficiency parameter;

generating a target voltage range according to the test voltage and a second preset proportion, wherein the second preset proportion is smaller than the first preset proportion; under the condition that the actual input voltage falls into the target voltage range, determining the chip operation parameter as a first operation parameter, wherein the chip operation parameter is used for indicating that the operation state of the board-level chip is normal operation; and under the condition that the actual input voltage does not fall into the target voltage range, determining the chip operation parameter as a second operation parameter, wherein the chip operation parameter is the second operation parameter and is used for indicating the operation state of the board-level chip to be abnormal operation.

Optionally, the generating the target voltage range according to the test voltage and the second preset ratio includes:

performing addition operation on the test voltage and a second target voltage amplitude to obtain a first target voltage, wherein the second target voltage amplitude is the product of the test voltage and the second preset proportion;

performing subtraction operation on the test voltage and a second target voltage amplitude to obtain a second target voltage, wherein the second target voltage amplitude is the product of the test voltage and the second preset proportion;

and generating the target voltage range according to the first target voltage and the second target voltage, wherein the upper limit of the target voltage range is the first target voltage, and the lower limit of the target voltage range is the second target voltage.

Optionally, the controlling the current value on the load device connected to the power output end of the board-level chip to reach the preset test current includes:

sequentially obtaining a reference test current from a reference test current set as the test current, wherein the reference test current set comprises one or more reference test currents;

And controlling the current value on a load device connected with the power output end of the board-level chip to reach the test current.

Optionally, before the obtaining a reference test current from the reference test current set as the test current, the method further includes:

acquiring the maximum load current;

generating N reference test currents according to the maximum load current and a preset percentage sequence to obtain the reference test current set, wherein the percentage sequence comprises N percentages, the percentage sequence is an arithmetic sequence, the percentage of the maximum item in the percentage sequence is 100%, the percentage of the minimum item in the percentage sequence is 0%, and N is a positive integer greater than 2.

Optionally, the generating N reference test currents according to the maximum load current and a preset percentage sequence includes:

and multiplying the maximum load current by each percentage in the percentage sequence in turn to obtain N reference test currents.

According to another embodiment of the present application, there is also provided a testing apparatus of a board-level chip, including:

the control module is used for controlling a power supply device connected with a power input end of a board-level chip to be tested to output a preset test voltage, and simultaneously controlling a current value on a load device connected with the power output end of the board-level chip to reach a preset test current, wherein the test voltage is larger than or equal to a maximum chip voltage and smaller than or equal to a minimum chip voltage, the maximum chip voltage is a maximum voltage value allowed to be loaded on the board-level chip, the minimum chip voltage is a minimum voltage value allowed to be loaded on the board-level chip, and the test current is smaller than or equal to a maximum load current, and the maximum load current is a maximum current value allowed to be loaded on the load device;

The first acquisition module is used for acquiring the actual input voltage and the actual input current on the power input end of the board-level chip, and detecting the voltage value on the power output end of the board-level chip to obtain the actual output voltage;

the determining module is configured to determine, according to the test current, the actual input voltage, and the actual output voltage, a chip loss parameter, a chip efficiency parameter, and a chip operation parameter of the board-level chip, where the chip loss parameter is used to indicate power loss of the board-level chip, the chip efficiency parameter is used to indicate power efficiency of the board-level chip, and the chip operation parameter is used to indicate an operation state of the board-level chip.

According to yet another aspect of the embodiments of the present application, there is also provided a computer-readable storage medium having a computer program stored therein, wherein the computer program is configured to execute the above-described test method of the board-level chip when run.

According to still another aspect of the embodiments of the present application, there is further provided an electronic device including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the method for testing the board-level chip through the computer program.

In the embodiment of the application, a power supply device connected with the power input end of the control board chip outputs a preset test voltage, and meanwhile, the current value on a load device connected with the power output end of the board chip reaches a preset test current, wherein the test voltage is allowed to float in a range between the minimum chip voltage and the maximum chip voltage, the test current is allowed to float in a range between 0 and the maximum load current, then, the actual input voltage and the actual input current on the power input end of the board chip and the voltage value on the power output end are obtained, the actual output voltage is obtained, finally, the chip loss parameter of the board chip, the chip efficiency parameter and the chip operation parameter can be determined at the same time according to the test current, different test points do not need to be welded, a new test environment does not need to be disassembled again, and the test time of the board chip is greatly reduced. By adopting the technical scheme, the problems of lower testing efficiency and the like of the board-level chip in the related technology are solved, and the technical effect of improving the testing efficiency of the board-level chip is realized.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.

FIG. 1 is a schematic diagram of a hardware environment of a method for testing a board-level chip according to an embodiment of the application;

FIG. 2 is a flow chart of a method of testing a board chip according to an embodiment of the application;

FIG. 3 is a schematic diagram of a board-level chip test apparatus according to an embodiment of the application;

FIG. 4 is a schematic diagram of a board-level chip tested at maximum chip voltage according to an embodiment of the application;

FIG. 5 is a schematic diagram of a board-level chip tested at normal operating voltages according to an embodiment of the application;

FIG. 6 is a schematic diagram of a board-level chip tested at minimum chip voltage according to an embodiment of the application;

FIG. 7 is a schematic diagram of a test flow of a board-level chip according to an embodiment of the application;

FIG. 8 is a schematic diagram of test software for a board-level chip according to an embodiment of the application;

fig. 9 is a block diagram of a board-level chip testing apparatus according to an embodiment of the present application.

Detailed Description

In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The method embodiments provided by the embodiments of the present application may be performed in a computer terminal, a device terminal, or a similar computing apparatus. Taking a computer terminal as an example, fig. 1 is a schematic diagram of a hardware environment of a testing method of a board-level chip according to an embodiment of the application. As shown in fig. 1, the computer terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing data, and in one exemplary embodiment, may also include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the configuration shown in fig. 1 is merely illustrative and is not intended to limit the configuration of the computer terminal described above. For example, a computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than the equivalent functions shown in FIG. 1 or more than the functions shown in FIG. 1.

The memory 104 may be used to store computer programs, such as software programs of application software and modules, such as computer programs corresponding to the test methods of the board level chip in the embodiment of the present application, and the processor 102 executes the computer programs stored in the memory 104 to perform various functional applications and data processing, that is, to implement the above-mentioned methods. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the computer terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is configured to communicate with the internet wirelessly.

The terms involved in the embodiments of the present application are explained as follows:

DC Source: a direct current power supply;

vin_max: max Vin Voltage, maximum input Voltage, i.e., maximum chip Voltage;

vin_nom: normal Vin Voltage, normal input voltage;

vin_min: min Vin Voltage, the minimum input Voltage, i.e., the minimum chip Voltage.

In this embodiment, a method for testing a board chip is provided and applied to the computer terminal, and fig. 2 is a flowchart of a method for testing a board chip according to an embodiment of the present application, as shown in fig. 2, where the flowchart includes the following steps:

step S202, controlling a power supply device connected with a power input end of a board-level chip to be tested to output a preset test voltage, and simultaneously controlling a current value on a load device connected with the power output end of the board-level chip to reach a preset test current, wherein the test voltage is larger than or equal to a maximum chip voltage and smaller than or equal to a minimum chip voltage, the maximum chip voltage is a maximum voltage value allowed to be loaded on the board-level chip, the minimum chip voltage is a minimum voltage value allowed to be loaded on the board-level chip, and the test current is smaller than or equal to a maximum load current, and the maximum load current is a maximum current value allowed to be loaded on the load device;

Step S204, obtaining the actual input voltage and the actual input current on the power input end of the board-level chip, and detecting the voltage value on the power output end of the board-level chip to obtain the actual output voltage;

step S206, determining, according to the test current, the actual input voltage and the actual output voltage, a chip loss parameter, a chip efficiency parameter and a chip operation parameter of the board-level chip, where the chip loss parameter is used to indicate power loss of the board-level chip, the chip efficiency parameter is used to indicate power efficiency of the board-level chip, and the chip operation parameter is used to indicate an operation state of the board-level chip.

Through the steps, the power supply device connected with the power input end of the control board chip outputs preset test voltage, meanwhile, the current value on the load device connected with the power output end of the board chip reaches preset test current, the test voltage is allowed to float within the range between the minimum chip voltage and the maximum chip voltage, the test current is allowed to float within the range between 0 and the maximum load current, then, the actual input voltage and the actual input current on the power input end of the board chip and the voltage value on the power output end are obtained, the actual output voltage is obtained, finally, the chip loss parameter of the board chip can be determined simultaneously according to the test current, the actual input voltage and the actual output voltage, the chip efficiency parameter and the chip operation parameter do not need to weld different test points, and new test environments do not need to be disassembled again, and the test time of the board chip is greatly shortened. By adopting the technical scheme, the problems of lower testing efficiency and the like of the board-level chip in the related technology are solved, and the technical effect of improving the testing efficiency of the board-level chip is realized.

In the technical solution provided in step S202, fig. 3 is a schematic diagram of a board-level chip test device according to an embodiment of the present application, as shown in fig. 3, the board-level chip may be disposed on a motherboard, and is configured to perform voltage conversion on a voltage output by a direct current power supply (i.e., a power supply device), and provide the converted voltage to an electronic load for use.

The structure of the board-level chip test apparatus is described as follows, and the board-level chip test apparatus includes: the power supply device (such as a direct current power supply), the load device (such as an electronic load), the data detection device (such as universal power 1 and universal power 2) and the data processing device (such as a PC, personal Computer and a personal computer), wherein the power input end of the board-level chip to be tested is connected with the power supply device, the power output end of the board-level chip is connected with the load device, the universal power 1 in the data detection device is connected with the power input end of the board-level chip, the universal power 2 in the data detection device is connected with the power output end of the board-level chip, the power supply device (direct current power supply), the load device (electronic load) and the data detection device (universal power 1 and universal power 2) form an automation equipment set, the automation software is installed on the data processing device (PC), and the automation equipment set is controlled through a GPIB (General-Purpose Interface Bus and a GPIB conversion line is connected to the PC through the USB (Universal Serial Bus and a General-serial bus). And the input and output capacitance welding signal wires of the chip are connected to the universal meter. The DC Source (i.e. the power supply device) is connected to the chip input to supply power to the board-level chip, and the current displayed on the DC Source is the test current. The electronic load is connected to the output of the chip to increase the test current to the chip.

The data processing device is used for controlling a power supply device connected with the power input end of the board-level chip to be tested to output a preset test voltage and controlling a current value on a load device connected with the power output end of the board-level chip to reach a preset test current;

the data detection device is used for acquiring the actual input voltage and the actual input current at the power input end of the board-level chip, and detecting the voltage value at the power output end of the board-level chip to obtain the actual output voltage;

the data processing device is further used for determining a chip loss parameter, a chip efficiency parameter and a chip operation parameter of the board-level chip according to the test current, the actual input voltage and the actual output voltage, wherein the chip loss parameter is used for indicating the power loss of the board-level chip, the chip efficiency parameter is used for indicating the power efficiency of the board-level chip, and the chip operation parameter is used for indicating the operation state of the board-level chip.

Through the mode, the power supply device (direct current power supply), the load device (electronic load) and the data detection device (universal power supply 1 and universal power supply 2) form an automatic equipment set, so that test points of multiple tests are combined, chip loss parameters, chip efficiency parameters and chip operation parameters can be obtained through one-time test, and the test efficiency is greatly improved.

In one exemplary embodiment, the power supply device connected to the power input of the on-board chip to be tested may be controlled to output a preset test voltage by, but is not limited to: obtaining a reference test voltage from a reference test voltage set as the test voltage, wherein the reference test voltage set comprises one or more reference test voltages; and controlling a power supply device connected with the power input end of the board-level chip to be tested to output the test voltage.

Alternatively, in the present embodiment, there may be a plurality of test voltages, but not limited to, any one obtained from a reference test voltage set.

In an exemplary embodiment, before the obtaining a reference test voltage from the reference test voltage set as the test voltage, the method may, but is not limited to, further include obtaining a normal operating voltage corresponding to the board-level chip, where the normal operating voltage is a voltage that allows loading when the board-level chip operates normally; and generating one or more reference test voltages according to the normal working voltage and a first preset proportion to obtain the reference test voltage set.

Alternatively, in this embodiment, a normal operating voltage is corresponding to one board-level chip, that is, a voltage that allows loading when the board-level chip is operating normally. In general, even if normal working voltage is not loaded on the board-level chip, the board-level chip can work, but when the board-level chip is in a voltage limit, the stability of the board-level chip is the worst, and the loss of the board-level chip can be more.

In one exemplary embodiment, generating one or more of the reference test voltages according to the normal operating voltage and a first preset ratio may be, but is not limited to, by at least one of:

And determining the normal working voltage as the reference test voltage.

Optionally, in this embodiment, taking the normal operating voltage as 12V and the first preset proportion as 5% as an example, a manner of generating the test voltage according to the normal operating voltage and the first preset proportion is described, and the first target voltage amplitude is the product of the normal operating voltage and the first preset proportion, that is, 0.6V.

FIG. 4 is a schematic diagram of a board-level chip tested under a maximum chip voltage according to an embodiment of the present application, where the maximum chip voltage is obtained by adding a first target voltage amplitude to the normal operating voltage as shown in FIG. 4; determining the maximum chip voltage as the test voltage, i.e., taking the maximum chip voltage of 12.6V as the test voltage;

FIG. 5 is a schematic diagram of a board-level chip tested under a normal working voltage according to an embodiment of the present application, where, as shown in FIG. 5, a first target voltage amplitude is subtracted from the normal working voltage to obtain the minimum chip voltage; determining the minimum chip voltage as the test voltage, namely, taking the maximum chip voltage of 11.4V as the test voltage;

in a third mode, fig. 6 is a schematic diagram of a board chip tested at a minimum chip voltage according to an embodiment of the present application, and as shown in fig. 6, the normal operating voltage 12V is determined as the test voltage.

In one exemplary embodiment, the current value on the load device connected to the on-board chip power output may be controlled to reach a preset test current by, but not limited to: sequentially obtaining a reference test current from a reference test current set as the test current, wherein the reference test current set comprises one or more reference test currents; and controlling the current value on a load device connected with the power output end of the board-level chip to reach the test current.

Alternatively, in the present embodiment, there may be a plurality of test currents, but not limited to, any one obtained from a reference test current set.

In an exemplary embodiment, before the obtaining a reference test current from the reference test current set as the test current, the method may, but is not limited to, further include: acquiring the maximum load current; generating N reference test currents according to the maximum load current and a preset percentage sequence to obtain the reference test current set, wherein the percentage sequence comprises N percentages, the percentage sequence is an arithmetic sequence, the percentage of the maximum item in the percentage sequence is 100%, the percentage of the minimum item in the percentage sequence is 0%, and N is a positive integer greater than 2.

Alternatively, in this embodiment, taking the value of N as 10 and the maximum load current as Imax as an example, as shown in fig. 4, 5 and 6, the N percentages are 0%,10%, … … and 100% from small to large.

In one exemplary embodiment, N reference test currents may be generated from the maximum load current and a preset percentage sequence by, but not limited to: and multiplying the maximum load current by each percentage in the percentage sequence in turn to obtain N reference test currents.

Alternatively, in this embodiment, as shown in fig. 4, 5 and 6, the N percentages in the percentage sequence are 0%,10%, … … and 100% from small to large. And multiplying the maximum load current by each percentage in the percentage sequence in turn to obtain a reference current set, for example, multiplying the maximum load current by 0%, obtaining a test current of 0, multiplying the maximum load current by 10%, obtaining a test current of 10% Imax, and multiplying the maximum load current by 100%, obtaining a test current of Imax. And finally obtaining a reference current set.

In the technical solution provided in step S204, the actual input voltage, the actual input current and the actual output voltage are required to be obtained through actual measurement, as shown in fig. 4, 5 and 6, the actual input voltage corresponds to Vin, the actual output voltage corresponds to Vout and the actual input current corresponds to Iin, wherein the actual input voltage is measured by the multimeter 1 shown in fig. 3, the actual output voltage is measured by the multimeter 2 shown in fig. 3, and the actual input current can be displayed on the dc power supply shown in fig. 3.

In the technical solution provided in step S206, the chip loss parameter, the chip efficiency parameter and the chip operation parameter of the board-level chip can be determined simultaneously by testing the current, the actual input voltage and the actual output voltage.

In one exemplary embodiment, the actual input current, the actual input voltage, and the actual output voltage may determine chip loss parameters, chip efficiency parameters, and chip operating parameters of the on-board chip from the test current by, but not limited to:

Alternatively, in the present embodiment, the actual input current, the actual input voltage, and the actual output voltage may be, but are not limited to, calculated by the following formula:

chip loss parameter = actual input current (actual input voltage-actual output voltage);

optionally, in this embodiment, the actual output voltage, the test current, the actual input voltage, and the actual input current are not limited to calculating the chip efficiency parameter by the following formula:

chip efficiency parameter = (actual output voltage x test current)/(actual input voltage x actual input current);

optionally, in this embodiment, a method for calculating a chip loss parameter is described: and determining the chip operation parameter as a first operation parameter when the actual input voltage falls into the target voltage range, wherein the operation state of the board-level chip is indicated to be normal operation, and determining the chip operation parameter as a second operation parameter when the actual input voltage does not fall into the target voltage range, wherein the operation state of the board-level chip is indicated to be abnormal operation.

In one exemplary embodiment, the target voltage range may be generated from the test voltage and the second preset ratio by, but not limited to: performing addition operation on the test voltage and a second target voltage amplitude to obtain a first target voltage, wherein the second target voltage amplitude is the product of the test voltage and the second preset proportion; performing subtraction operation on the test voltage and a second target voltage amplitude to obtain a second target voltage, wherein the second target voltage amplitude is the product of the test voltage and the second preset proportion; and generating the target voltage range according to the first target voltage and the second target voltage, wherein the upper limit of the target voltage range is the first target voltage, and the lower limit of the target voltage range is the second target voltage.

Optionally, in this embodiment, taking the second preset ratio as an example, as shown in fig. 4, the test voltage is 12.6V, the second target voltage amplitude is 0.378, the first target voltage is 12.222V, the second target voltage is 12.978V, and the target voltage ranges from 12.222V to 12.978V.

In order to better understand the testing process of the board-level chip, the following description is given with reference to an alternative embodiment, but the testing process of the board-level chip is not limited to the technical solution of the embodiment of the present application.

In this embodiment, a method for testing a board-level chip is provided, and fig. 7 is a schematic diagram of a testing flow of a board-level chip according to an embodiment of the present application, as shown in fig. 7, mainly including the following steps:

step S701: the power loss modularized test environment is built, the anode and the cathode of the chip output end of the main board to be tested are respectively connected to the anode and the cathode of the electronic load, a DC Source (a direct current power supply or called a power supply device) is used for supplying power to the main board, integrated test automation software is installed on a PC, and a calling program is used for ensuring that the software can control all devices;

step S702: and calling test software, setting test parameters such as test voltage, test current and the like, controlling DC Source to electrify the main board, and ensuring that the measurement data of the universal meter are accurate. The DC Source input voltage is then set to vin_max (maximum chip voltage), the electronic load current (i.e., test current) is set to 0A, and the multimeter is controlled. The input voltage, output voltage and input current are measured and automatically recorded in the test report. Reporting an automatic judging test result;

Step S703: judging whether the loading current is Imax (maximum loading current) at the moment, if not, adjusting the loading current to enable the loading current to be increased by 10% of each round, automatically measuring and recording the input voltage, the output voltage and the input current to a report at the moment every time when the loading current is increased, and if not, until Imax;

step S704: judging whether three scenes of input voltage vin_Max (maximum chip voltage), vin_nom (normal working voltage) and vin_Min (minimum chip voltage) are all verified, and automatically testing each input voltage according to the same condition until the test is completed; according to the test result captured in the integrated report, a formula (a chip loss parameter calculation formula, a chip efficiency parameter calculation formula) is imported, the chip loss parameter and the chip efficiency parameter which are actually tested are automatically obtained, meanwhile, the actual input current and the target voltage range are automatically compared (compared), and whether the board-level chip is in a normal working range or not is determined.

It should be noted that, fig. 8 is a schematic diagram of test software of a board-level chip according to an embodiment of the present application, and as shown in fig. 8, an operation interface of the test software may implement rapid standardized development based on a graphical writing capability of a PyQt5 QtDesigner program, so as to facilitate later maintenance.

System architecture of test software: constructing a system architecture based on a QThread standard library under PyQt5, endowing an automatic test system with multithreading capability, and ensuring the fluency of an operation interface; based on Windows system API, the interrupt request of the user is realized, so that the automatic test system can adapt to all Windows platforms, and the suspending and recovering of the millisecond test task thread is realized.

Resource call of test software: and the instrument resource is connected based on the pyvisa standard library, and the global unified management is carried out on the resource call Session at the same time, so that the problems of conflict of multi-thread resource call and instrument resource recovery are solved.

Data processing of test software: after the test is completed, test data (such as test current, actual input voltage and actual output voltage) is automatically obtained and compared with test SPEC (target voltage range) to obtain a test result.

From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising several instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method of the various embodiments of the present application.

FIG. 9 is a block diagram of a board-level chip testing apparatus according to an embodiment of the present application; as shown in fig. 9, includes:

the control module 902 is configured to control a power supply device connected to an electrical input end of a board-level chip to be tested to output a preset test voltage, and simultaneously control a current value on a load device connected to the electrical output end of the board-level chip to reach a preset test current, where the test voltage is greater than or equal to a maximum chip voltage and less than or equal to a minimum chip voltage, the maximum chip voltage is a maximum voltage value allowed to be loaded on the board-level chip, the minimum chip voltage is a minimum voltage value allowed to be loaded on the board-level chip, and the test current is less than or equal to a maximum load current, and the maximum load current is a maximum current value allowed to be loaded by the load device;

a first obtaining module 904, configured to obtain an actual input voltage and an actual input current at the power input end of the board-level chip, and detect a voltage value at the power output end of the board-level chip at the same time, so as to obtain an actual output voltage;

the determining module 906 is configured to determine, according to the test current, the actual input voltage, and the actual output voltage, a chip loss parameter, a chip efficiency parameter, and a chip operation parameter of the board-level chip, where the chip loss parameter is used to indicate power loss of the board-level chip, the chip efficiency parameter is used to indicate power efficiency of the board-level chip, and the chip operation parameter is used to indicate an operation state of the board-level chip.

It should be noted that each of the above modules may be implemented by software or hardware, and for the latter, it may be implemented by, but not limited to: the modules are all located in the same processor; alternatively, the above modules may be located in different processors in any combination.

In one exemplary embodiment, the control module includes:

a first acquisition unit, configured to acquire a reference test voltage from a reference test voltage set as the test voltage, where the reference test voltage set includes one or more reference test voltages;

the first control unit is used for controlling a power supply device connected with the power input end of the board-level chip to be tested to output the test voltage.

In an exemplary embodiment, the apparatus further comprises:

the second acquisition module is used for acquiring normal working voltage corresponding to the board-level chip before acquiring a reference test voltage from the reference test voltage set as the test voltage, wherein the normal working voltage is voltage allowed to be loaded when the board-level chip works normally;

the first generation module is used for generating one or more reference test voltages according to the normal working voltage and a first preset proportion to obtain the reference test voltage set.

In one exemplary embodiment, the first generation module includes at least one of:

the first execution unit is used for executing addition operation on the normal working voltage and the first target voltage amplitude value to obtain the maximum chip voltage; determining the maximum chip voltage as the reference test voltage, wherein the first target voltage amplitude is the product of the normal working voltage and the first preset proportion;

The second execution unit is used for executing subtraction operation on the normal working voltage and the first target voltage amplitude value to obtain the minimum chip voltage; determining the minimum chip voltage as the reference test voltage, wherein the first target voltage amplitude is the product of the normal working voltage and the first preset proportion;

and the first determining unit is used for determining the normal working voltage as the reference test voltage.

In one exemplary embodiment, the determining module includes:

a second determining unit configured to determine a difference between the actual input voltage and the actual output voltage as a first difference; determining a product of the actual input current and the first difference as the chip loss parameter;

a third determining unit configured to determine a product of the test current and the actual output voltage as a first value; determining a product of the actual input current and the actual input voltage as a second value; determining a ratio of the first value to the second value as the chip efficiency parameter;

the generating unit is used for generating a target voltage range according to the test voltage and a second preset proportion, and the second preset proportion is smaller than the first preset proportion; under the condition that the actual input voltage falls into the target voltage range, determining the chip operation parameter as a first operation parameter, wherein the chip operation parameter is used for indicating that the operation state of the board-level chip is normal operation; and under the condition that the actual input voltage does not fall into the target voltage range, determining the chip operation parameter as a second operation parameter, wherein the chip operation parameter is the second operation parameter and is used for indicating the operation state of the board-level chip to be abnormal operation.

In an exemplary embodiment, the generating unit is further configured to:

In one exemplary embodiment, the control module includes:

a second obtaining unit, configured to sequentially obtain a reference test current from a reference test current set as the test current, where the reference test current set includes one or more reference test currents;

and the second control unit is used for controlling the current value on the load device connected with the power output end of the board-level chip to reach the test current.

In an exemplary embodiment, the apparatus further comprises:

a third obtaining module, configured to obtain the maximum load current before obtaining a reference test current from the reference test current set as the test current;

the second generation module is used for generating N reference test currents according to the maximum load current and a preset percentage sequence to obtain the reference test current set, wherein the percentage sequence comprises N percentages, the percentage sequence is an arithmetic sequence, the percentage of the maximum item in the percentage sequence is 100%, the percentage of the minimum item in the percentage sequence is 0%, and N is a positive integer greater than 2.

In an exemplary embodiment, the second generating module includes:

and the multiplying unit is used for sequentially multiplying the maximum load current with each percentage in the percentage sequence to obtain N reference test currents.

Embodiments of the present application also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

In one exemplary embodiment, the computer readable storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.

An embodiment of the application also provides an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

In an exemplary embodiment, the electronic device may further include a transmission device connected to the processor, and an input/output device connected to the processor.

Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.

It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application should be included in the protection scope of the present application.

Claims

1. A method for testing board-level chips, comprising:

2. The method according to claim 1, wherein controlling the power supply device connected to the power input of the board-level chip to be tested to output the preset test voltage comprises:

3. The method of claim 2, wherein prior to said deriving a reference test voltage from a set of reference test voltages as said test voltage, said method further comprises:

4. A method according to claim 3, wherein said generating one or more of said reference test voltages from said normal operating voltage and a first preset ratio comprises at least one of:

And determining the normal working voltage as the reference test voltage.

5. A method according to claim 3, wherein said determining chip loss parameters, chip efficiency parameters and chip operation parameters of said board chip from said test current, said actual input voltage and said actual output voltage comprises:

6. The method of claim 5, wherein generating the target voltage range from the test voltage and a second preset ratio comprises:

7. The method of claim 1, wherein controlling the current value on the load device connected to the board-level chip power output to reach the predetermined test current comprises:

8. The method of claim 7, wherein prior to said deriving a reference test current from a set of reference test currents as said test current, said method further comprises:

acquiring the maximum load current;

9. The method of claim 8, wherein generating N reference test currents from the maximum load current and a preset percentage sequence comprises:

10. A board-level chip testing device, comprising:

11. A computer-readable storage medium, characterized in that the computer-readable storage medium comprises a stored program, wherein the program when run performs the method of any one of claims 1 to 9.

12. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to execute the method according to any of claims 1 to 9 by means of the computer program.