CN117153685A - MOSFET forming method and MOSFET structure - Google Patents

MOSFET forming method and MOSFET structure Download PDF

Info

Publication number
CN117153685A
CN117153685A CN202311111180.6A CN202311111180A CN117153685A CN 117153685 A CN117153685 A CN 117153685A CN 202311111180 A CN202311111180 A CN 202311111180A CN 117153685 A CN117153685 A CN 117153685A
Authority
CN
China
Prior art keywords
substrate
forming
mosfet
side wall
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311111180.6A
Other languages
Chinese (zh)
Inventor
华光平
刘景望
李亮
田磊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN202311111180.6A priority Critical patent/CN117153685A/en
Publication of CN117153685A publication Critical patent/CN117153685A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention provides a method for forming a MOSFET and a MOSFET structure, wherein the method for forming the MOSFET comprises the following steps: providing a substrate; forming a plurality of spaced gate structures within a substrate; forming source ends in the substrates at two sides of the grid structure; forming an interlayer dielectric layer on the surface of the grid structure; forming a through hole in the interlayer dielectric layer and the substrate, wherein the through hole is positioned in the substrate between the grid structures and is contacted with the side surface of the source end; dividing the side wall of the through hole into two parts which are adjacent up and down, wherein the side wall of the first part is positioned on the substrate, the side wall of the second part is positioned in the substrate, and etching the side wall of the first part of the through hole to expose part of the surface of the substrate; and filling metal into the through holes to form contact holes. The invention increases the contact area between the contact hole and the source end, thereby being capable of leading out the current of the source end more easily.

Description

MOSFET forming method and MOSFET structure
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for forming a MOSFET and a MOSFET structure.
Background
Power MOSFETs are a new generation of power semiconductor devices that combine microelectronics and power electronics. The high-voltage power supply has the advantages of high input impedance, high switching speed, high output current, good thermal stability, wide safe working area and the like, and is widely applied to electronic equipment.
The MOSFET structure generally includes a substrate, a trench in the substrate, a gate oxide layer in the trench, and gate polysilicon. And source ends positioned at two ends of the groove, wherein the source ends are positioned in the substrate. The semiconductor device further comprises an interlayer dielectric layer and a metal layer which are sequentially positioned on the gate polysilicon, and further comprises a contact hole structure, wherein the contact hole structure penetrates through the interlayer dielectric layer and enters the substrate to be in contact with the side face of the source end, and the contact hole is straight. Since the channel resistance of the low-voltage trench MOSFET occupies a large proportion of the on-resistance, the purpose can be achieved by shortening the channel resistance in order to reduce the on-resistance. A common method for shortening the channel resistance is to shorten the channel length, however, the junction depth of the source end is also reduced properly while shortening the channel length, otherwise, short channel effect may occur, so that the situation of leakage of the channel is increased.
However, since the contact hole of the MOSFET of the related art is straight, when the junction depth of the source terminal is reduced, the contact area of the contact hole and the source terminal side is reduced, the contact area is reduced, and the contact hole is not easy to draw out the current of the source terminal.
Disclosure of Invention
The invention aims to provide a MOSFET forming method and a MOSFET structure, which can increase the contact area between a contact hole and a source end, so that the current of the source end can be led out more easily.
In order to achieve the above object, the present invention provides a method for forming a MOSFET, including:
providing a substrate;
forming a plurality of spaced gate structures within the substrate;
forming source ends in the substrates at two sides of the grid structure;
forming an interlayer dielectric layer on the surface of the grid structure;
forming a through hole in the interlayer dielectric layer and the substrate, wherein the through hole is positioned in the substrate between the grid structures and is contacted with the side surface of the source end;
dividing the side wall of the through hole into two parts which are adjacent up and down, wherein the side wall of the first part is positioned on the substrate, the side wall of the second part is positioned in the substrate, and etching the side wall of the first part of the through hole to expose part of the surface of the substrate;
and filling metal into the through holes to form contact holes.
Optionally, in the forming method of the MOSFET, the forming method of the plurality of gate structures in the substrate includes:
forming a hard mask layer on the surface of the substrate;
etching the hard mask layer and the substrate to form a groove;
removing the hard mask layer;
and forming a gate oxide layer and gate polysilicon in the trench.
Optionally, in the method for forming a MOSFET, after forming a plurality of gate structures in the substrate, the method further includes: ions are implanted into the substrate between adjacent gate structures to form a well region in the substrate.
Optionally, in the method for forming a MOSFET, ions are implanted into the substrate on both sides of the gate structure, so as to form a source terminal in the substrate on both sides of the gate structure.
Optionally, in the method for forming a MOSFET, the interlayer dielectric layer and the substrate are etched in sequence from the surface of the interlayer dielectric layer toward the substrate, and the etching is stopped in the substrate, so as to form a via hole in the interlayer dielectric layer and the substrate.
Optionally, in the method for forming a MOSFET, a first portion of a sidewall of the via is wet etched to expose a portion of a surface of the substrate.
Optionally, in the method for forming a MOSFET, the interlayer dielectric layer is silicon dioxide.
Optionally, in the method for forming a MOSFET, tungsten metal is filled into the via hole to form a contact hole.
Optionally, in the method for forming a MOSFET, after filling metal into the via hole to form a contact hole, the method further includes: and forming a metal layer on the interlayer dielectric layer, wherein the contact hole communicates the metal layer with the source end.
Correspondingly, the invention also provides a MOSFET structure, which comprises:
a substrate;
a plurality of gate structures located within the substrate;
source ends positioned at two sides of the grid structure;
an interlayer dielectric layer positioned on the surface of the grid structure;
a contact hole in the substrate between the gate structures, and the contact hole is in contact with a side surface of the source terminal;
the side wall of the contact hole is divided into an upper part and a lower part which are adjacent, the side wall of the first part is positioned on the substrate, the side wall of the second part is positioned in the substrate, and the side wall of the first part of the contact hole exposes part of the surface of the substrate.
In the method for forming the MOSFET and the MOSFET structure provided by the invention, the method for forming the MOSFET comprises the following steps: providing a substrate; forming a plurality of spaced gate structures within a substrate; forming source ends in the substrates at two sides of the grid structure; forming an interlayer dielectric layer on the surface of the grid structure; forming a through hole in the interlayer dielectric layer and the substrate, wherein the through hole is positioned in the substrate between the grid structures and is contacted with the side surface of the source end; dividing the side wall of the through hole into two parts which are adjacent up and down, wherein the side wall of the first part is positioned on the substrate, the side wall of the second part is positioned in the substrate, and etching the side wall of the first part of the through hole to expose part of the surface of the substrate; and filling metal into the through holes to form contact holes. The MOSFET structure comprises: a substrate; a plurality of gate structures located within the substrate; source ends positioned at two sides of the grid structure; an interlayer dielectric layer positioned on the surface of the gate structure; a contact hole in the substrate between the gate structures, and the contact hole is in contact with a side surface of the source terminal; the side wall of the contact hole is divided into two parts which are adjacent up and down, the side wall of the first part is positioned on the substrate, the side wall of the second part is positioned in the substrate, and the side wall of the first part of the contact hole exposes part of the surface of the substrate. The invention increases the contact area between the contact hole and the source end, thereby being capable of leading out the current of the source end more easily.
Drawings
Fig. 1 is a flow chart of a method of forming a MOSFET in accordance with an embodiment of the present invention;
fig. 2 is a schematic diagram of a MOSFET after forming a hard mask layer according to an embodiment of the invention;
fig. 3 is a schematic diagram of a MOSFET after forming gate polysilicon according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a MOSFET after forming an interlayer dielectric layer according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a MOSFET after forming a via hole according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a MOSFET after forming a metal layer according to an embodiment of the present invention;
in the figure: 110-substrate, 120-hard mask layer, 130-gate oxide layer, 140-gate polysilicon, 150-well region, 160-source end, 170-interlayer dielectric layer, 180-through hole, 190-contact hole and 200-metal layer.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the following, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances. Similarly, if a method described herein comprises a series of steps, and the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Also, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer and/or one or more intervening layers may also be present. In addition, references to "upper" and "lower" on the respective layers may be made based on the drawings.
Referring to fig. 1, the present invention provides a method for forming a MOSFET, including:
s11: providing a substrate;
s12: forming a plurality of spaced gate structures within the substrate;
s13: forming source ends in the substrates at two sides of the grid structure;
s14: forming an interlayer dielectric layer on the surface of the grid structure;
s15: forming a through hole in the interlayer dielectric layer and the substrate, wherein the through hole is positioned in the substrate between the grid structures and is contacted with the side surface of the source end;
s16: dividing the side wall of the through hole into two parts which are adjacent up and down, wherein the side wall of the first part is positioned on the substrate, the side wall of the second part is positioned in the substrate, and etching the side wall of the first part of the through hole to expose part of the surface of the substrate;
s17: and filling metal into the through holes to form contact holes.
First, referring to fig. 2 and 3, a substrate 110 is provided, and the substrate 110 may be a silicon substrate, for example, a wafer. A hard mask layer 120 is formed on the surface of the substrate 110. The hard mask layer 120 may be a silicon nitride layer or a silicon oxide layer, which may be formed by depositing silicon nitride on the substrate 110 if the silicon nitride layer is formed by depositing silicon dioxide on the surface of the substrate 110 if the silicon oxide layer is formed. Next, a gate formation region is defined by a photolithography process, and the hard mask layer 120 of the gate formation region is removed by an etching process. The etched hard mask layer 120 is used as a mask to anisotropically etch the substrate 110 to form a plurality of trenches, and a certain distance is reserved between every two adjacent trenches. Next, the hard mask layer 120 is removed, exposing the surface of the substrate 110. Next, a gate oxide layer 130 is formed on the inner wall of the trench and the surface of the substrate, and the gate oxide layer 130 may be formed by depositing silicon dioxide. The gate oxide layer 130 forms a recess in the trench, and then the recess is filled with polysilicon, which fills the recess and extends to the surface of the gate oxide layer outside the trench. Next, a polysilicon etch back is performed to remove the polysilicon outside the trench and to etch back the surface of the polysilicon in the trench region to be level with the top surface of the trench to form gate polysilicon 140 in the trench.
Next, referring to fig. 4, the gate oxide layer on the surface of the substrate 110 is removed, the well region 150 is formed on both sides of the trench by implanting ions, which may be phosphorus ions, and then the source terminal 160 is formed on both sides of the trench in the substrate 110 and also in the well region 150 by implanting ions, the source terminal 160 being close to the surface of the substrate 110 and the source terminal 160 being close to the sidewall of the trench. The implanted ions may be boron ions. Next, an interlayer dielectric layer 170 is formed on the surface of the gate polysilicon 140 and the surface of the gate oxide layer.
Next, referring to fig. 5, the interlayer dielectric layer 170 and the substrate 110 are etched to form a via 180, and the via 180 is located in the substrate 110 between the trenches. Initially, the sidewalls of the via 180 are relatively sloped but not curved, of course sloped. The sidewall of the via 180 is divided into two parts, a first part of the sidewall being located on the substrate 110 and a second part of the sidewall being located within the substrate 110. Next, the wet etching of the first portion of the sidewall of the via is continued such that the sidewall exposes a portion of the surface of the substrate 110, i.e., exposes a portion of the surface of the source terminal 160. Next, a metal material, for example, a tungsten material is filled into the via hole 180 to form a contact hole 190. Because of the special shape of the contact hole 190, the contact hole 190 may contact not only the side surface of the source terminal 160 but also a portion of the surface of the source terminal 160, so that the contact area between the contact hole 190 and the source terminal 160 is increased, and the current of the source terminal 160 is easily drawn out. In addition, since the contact hole 190 and the source terminal 160 are in good contact, the contact resistance is low, and the on-resistance of the device is not affected.
Next, referring to fig. 6, a metal layer 200 is formed on the interlayer dielectric layer 170, and the metal layer 200 communicates with the contact hole 190. Since the contact area of the contact hole 190 and the source terminal 160 is increased, it is easy to draw out the current of the source terminal 160 to the metal layer 200.
Next, referring to fig. 6, the present invention further provides a MOSFET structure, including: a substrate 110; a plurality of gate structures located within the substrate 110; source terminals 160 located on both sides of the gate structure; an interlayer dielectric layer 170 on the surface of the gate structure; a contact hole in the substrate 110 between the gate structures, and the contact hole 190 is in contact with a side of the source terminal 160; the sidewall of the contact hole 190 is divided into two parts adjacent to each other, a first part of the sidewall is located on the substrate 110, a second part of the sidewall is located in the substrate 110, and the first part of the sidewall of the contact hole 190 exposes a part of the surface of the substrate 110. The MOSFET structure further includes a well 150 between the gate structures, and a source 160 is located within the well 150. The gate structure includes a gate oxide layer 130 and gate polysilicon 140, both within the substrate 110. The gate oxide 130 isolates the gate polysilicon 140 from the substrate 110.
In summary, in the method for forming a MOSFET and the MOSFET structure provided in the embodiments of the present invention, the method for forming a MOSFET includes: providing a substrate; forming a plurality of spaced gate structures within a substrate; forming source ends in the substrates at two sides of the grid structure; forming an interlayer dielectric layer on the surface of the grid structure; forming a through hole in the interlayer dielectric layer and the substrate, wherein the through hole is positioned in the substrate between the grid structures and is contacted with the side surface of the source end; dividing the side wall of the through hole into two parts which are adjacent up and down, wherein the side wall of the first part is positioned on the substrate, the side wall of the second part is positioned in the substrate, and etching the side wall of the first part of the through hole to expose part of the surface of the substrate; and filling metal into the through holes to form contact holes. The MOSFET structure comprises: a substrate; a plurality of gate structures located within the substrate; source ends positioned at two sides of the grid structure; an interlayer dielectric layer positioned on the surface of the gate structure; a contact hole in the substrate between the gate structures, and the contact hole is in contact with a side surface of the source terminal; the side wall of the contact hole is divided into two parts which are adjacent up and down, the side wall of the first part is positioned on the substrate, the side wall of the second part is positioned in the substrate, and the side wall of the first part of the contact hole exposes part of the surface of the substrate. The invention increases the contact area between the contact hole and the source end, thereby being capable of leading out the current of the source end more easily.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.

Claims (10)

1. A method of forming a MOSFET, comprising:
providing a substrate;
forming a plurality of spaced gate structures within the substrate;
forming source ends in the substrates at two sides of the grid structure;
forming an interlayer dielectric layer on the surface of the grid structure;
forming a through hole in the interlayer dielectric layer and the substrate, wherein the through hole is positioned in the substrate between the grid structures and is contacted with the side surface of the source end;
dividing the side wall of the through hole into two parts which are adjacent up and down, wherein the side wall of the first part is positioned on the substrate, the side wall of the second part is positioned in the substrate, and etching the side wall of the first part of the through hole to expose part of the surface of the substrate;
and filling metal into the through holes to form contact holes.
2. The method of forming a MOSFET of claim 1 wherein forming a plurality of gate structures within said substrate comprises:
forming a hard mask layer on the surface of the substrate;
etching the hard mask layer and the substrate to form a groove;
removing the hard mask layer;
and forming a gate oxide layer and gate polysilicon in the trench.
3. The method of forming a MOSFET of claim 1, further comprising, after forming a plurality of gate structures within the substrate: ions are implanted into the substrate between adjacent gate structures to form a well region in the substrate.
4. The method of forming a MOSFET of claim 1 wherein ions are implanted into the substrate on both sides of the gate structure to form source terminals in the substrate on both sides of the gate structure.
5. The method of forming a MOSFET of claim 1, wherein the interlayer dielectric layer and the substrate are etched sequentially from a surface of the interlayer dielectric layer toward the substrate, and etching is stopped inside the substrate to form a via hole in the interlayer dielectric layer and the substrate.
6. The method of forming a MOSFET of claim 1 wherein a first portion of the sidewall of the via is wet etched to expose a portion of the surface of the substrate.
7. The method of forming a MOSFET of claim 1 wherein said interlayer dielectric layer is silicon dioxide.
8. The method of forming a MOSFET of claim 1 wherein tungsten metal is filled into the via to form a contact hole.
9. The method of forming a MOSFET of claim 1, wherein after filling metal into the via hole to form a contact hole, further comprising: and forming a metal layer on the interlayer dielectric layer, wherein the contact hole communicates the metal layer with the source end.
10. A MOSFET structure formed using the method of forming a MOSFET as recited in any one of claims 1-9, comprising:
a substrate;
a plurality of gate structures located within the substrate;
source ends positioned at two sides of the grid structure;
an interlayer dielectric layer positioned on the surface of the grid structure;
a contact hole in the substrate between the gate structures, and the contact hole is in contact with a side surface of the source terminal;
the side wall of the contact hole is divided into an upper part and a lower part which are adjacent, the side wall of the first part is positioned on the substrate, the side wall of the second part is positioned in the substrate, and the side wall of the first part of the contact hole exposes part of the surface of the substrate.
CN202311111180.6A 2023-08-30 2023-08-30 MOSFET forming method and MOSFET structure Pending CN117153685A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311111180.6A CN117153685A (en) 2023-08-30 2023-08-30 MOSFET forming method and MOSFET structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311111180.6A CN117153685A (en) 2023-08-30 2023-08-30 MOSFET forming method and MOSFET structure

Publications (1)

Publication Number Publication Date
CN117153685A true CN117153685A (en) 2023-12-01

Family

ID=88904010

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311111180.6A Pending CN117153685A (en) 2023-08-30 2023-08-30 MOSFET forming method and MOSFET structure

Country Status (1)

Country Link
CN (1) CN117153685A (en)

Similar Documents

Publication Publication Date Title
US7445982B2 (en) Method of manufacturing a semiconductor integrated circuit device
KR20130031205A (en) Semiconductor device and method for manufacturing the same
US9953971B2 (en) Insulated gate bipolar transistor (IGBT) and related methods
CN113594039A (en) Semiconductor structure and forming method thereof
CN114744044A (en) Trench type silicon carbide MOSFET of triple-protection gate oxide layer and preparation method thereof
CN111883430B (en) Semiconductor device manufacturing method
CN117153685A (en) MOSFET forming method and MOSFET structure
JP4655351B2 (en) Method for manufacturing trench type semiconductor device
CN106024898B (en) Groove power device and manufacturing method
US10840327B2 (en) Combined gate trench and contact etch process and related structure
KR100791773B1 (en) The fabricating method of trench gate mosfet device
KR100275484B1 (en) Method for manufacturing a power device having a trench gate electrode
JP2002184975A (en) Power mosfet and its fabricating method
CN112768356A (en) Trench gate IGBT manufacturing method
CN106992123B (en) Lateral diffusion metal oxide semiconductor element and manufacturing method thereof
EP4369382A1 (en) Dmos device having junction field plate and manufacturing method therefor
US20230100307A1 (en) Method for manufacturing trench-gate mosfet
CN117542795B (en) Semiconductor device and method for manufacturing the same
KR20020072984A (en) Different size trenches and method of forming the same
CN116314299A (en) Shielded gate MOSFET device of enhanced terminal
CN117912955A (en) Method for forming shielded gate MOSFET
KR19990081274A (en) Manufacturing Method of Power Semiconductor Device Having Trench Gate Structure
CN118098975A (en) Forming method of MOSFET device
CN117497419A (en) Method for manufacturing trench MOSFET with self-aligned contact hole
CN116344532A (en) Novel stacked Trench MOS device and method based on Trench gate structure and capable of being integrated in three dimensions

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination