CN117148909A - Short-circuit protection circuit of linear voltage stabilizer and linear voltage stabilizer - Google Patents
Short-circuit protection circuit of linear voltage stabilizer and linear voltage stabilizer Download PDFInfo
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- CN117148909A CN117148909A CN202311403215.3A CN202311403215A CN117148909A CN 117148909 A CN117148909 A CN 117148909A CN 202311403215 A CN202311403215 A CN 202311403215A CN 117148909 A CN117148909 A CN 117148909A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The application provides a short-circuit protection circuit of a linear voltage stabilizer and the linear voltage stabilizer, wherein the short-circuit protection circuit comprises: a seventh PMOS tube, an eighth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a voltage clamping unit and a sampling PMOS tube; the source electrode of the ninth PMOS tube is connected with the drain electrode of the eighth PMOS tube, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube; the drain electrode of the tenth NMOS tube is connected with the source electrode of the eleventh NMOS tube, the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the sampling PMOS tube, the source electrode of the sampling PMOS tube is connected with the power supply voltage, and the grid electrode and the drain electrode of the sampling PMOS tube are in short circuit and connected with the grid electrode of the power tube of the linear voltage stabilizer; the voltage clamping unit is connected between the power supply voltage and the drain electrode of the eleventh NMOS tube.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuits, in particular to a short-circuit protection circuit of a linear voltage stabilizer and the linear voltage stabilizer.
Background
In an automotive electronic system, an automotive battery provides power for in-car equipment, and the battery voltage is typically about 12V, and a high-voltage LDO (linear voltage regulator) is usually required to perform voltage reduction and convert into stable low voltage to supply power for the equipment, such as CAN, MCU and the like. In practical application, the following requirement 1 exists for the LDO, and the LDO is required to have extremely low standby power consumption due to battery power supply; 2. the power line of the automobile battery can have surge voltage, and the LDO is required to have the capability of suppressing the surge voltage; 3. the output of the LDO usually needs to be connected with a capacitor to stabilize the output voltage, and there is a possibility that the output VOUT is shorted, and the chip is burned out due to the fact that the short circuit generates extremely large current (ampere level), so that the LDO needs to limit the short circuit current to protect the chip.
Conventional LDOs with short-circuit protection (fig. 1) typically have two control loops: 1. the main loop is used for stabilizing the output voltage; 2. the short-circuit protection loop is used for limiting output short-circuit current; 3. for surge voltage, the change speed of VIN is very fast and can reach 10V/us, VG cannot timely follow the change of VIN, the power tube MP0 can instantaneously generate larger VGS, instantaneously output large current, generate larger overshoot voltage between VOUT and VFB, and then adjust the voltage of VG through a main loop, so that overshoot is reduced. Since the bandwidth of the main loop and the output slew rate of EA are limited, the adjustment speed of VG is always slower than VIN, and thus output overshoot due to surge voltage is unavoidable, and a larger overshoot voltage may damage the chip. To improve the ability to reject surge voltages, the bandwidth and slew rate of the main loop is typically increased by increasing the quiescent power consumption of EA.
Therefore, how to improve the short-circuit protection function and the surge voltage suppression capability is a problem that needs to be solved at present.
Disclosure of Invention
The application aims to provide a short-circuit protection circuit of a linear voltage stabilizer and the linear voltage stabilizer, which can realize the short-circuit protection function and inhibit the surge.
In order to achieve the above object, the present application provides a short-circuit protection circuit of a linear voltage regulator, comprising: a seventh PMOS tube, an eighth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a voltage clamping unit and a sampling PMOS tube;
the seventh PMOS tube and the eighth PMOS tube form a PMOS current mirror, the grid electrode and the drain electrode of the seventh PMOS tube are in short circuit, the drain electrode of the seventh PMOS tube is connected with a current source, and the current source supplies fixed current to the drain electrode of the seventh PMOS tube; the ninth NMOS tube and the tenth NMOS tube form an NMOS current mirror; the source electrode of the ninth PMOS tube is connected with the drain electrode of the eighth PMOS tube, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube; the grid electrode of the ninth PMOS tube is connected with the voltage signal output end of the pre-stage amplifier, and the output structure of the pre-stage amplifier is a rail-to-rail structure;
the drain electrode of the tenth NMOS tube is connected with the source electrode of the eleventh NMOS tube, the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the sampling PMOS tube, the eleventh NMOS tube is a high-voltage tube, the voltage at one end of the drain electrode of the eleventh NMOS tube is higher than the voltage at one end of the source electrode, and the grid electrode of the eleventh NMOS tube is connected with a low-voltage bias signal generated by the pre-amplifier; the source electrode of the sampling PMOS tube is connected with the power supply voltage, and the grid electrode and the drain electrode of the sampling PMOS tube are in short circuit and connected with the grid electrode of the power tube of the linear voltage stabilizer;
the voltage clamping unit is connected between the power supply voltage and the drain electrode of the eleventh NMOS tube and is used for clamping the lowest voltage at the grid electrode of the sampling PMOS tube.
In an alternative scheme, the seventh PMOS transistor, the eighth PMOS transistor, the ninth NMOS transistor and the tenth NMOS transistor are all low-voltage transistors, and the sampling PMOS transistor is a high-voltage transistor.
In an alternative, the voltage clamping unit includes: a tenth PMOS tube and an eleventh PMOS tube; a tube;
the first PMOS tube and the second PMOS tube form a current mirror structure; the fifth PMOS tube and the sixth PMOS tube form a current mirror structure; the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube form a current mirror structure;
the grid electrode and the drain electrode of the first NMOS tube are in short circuit and connected with the source electrode of the second NMOS tube, the drain electrode and the grid electrode of the second NMOS tube are in short circuit and connected with an analog power supply, and the connection part is used as the output end of the first bias voltage signal; the first bias voltage signal is input to the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube;
the third NMOS tube is a source of a current mirror structure, a grid electrode and a drain electrode of the third NMOS tube are in short circuit and connected to an analog power supply, and the joint of the grid electrode and the drain electrode is used as an output end of a second bias voltage signal; the second bias voltage signal is input to the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube;
the drain electrode of the fifth NMOS tube is connected with the source electrode of the seventh NMOS tube and the drain electrode of the third PMOS tube; the drain electrode of the sixth NMOS tube is connected with the source electrode of the eighth NMOS tube and the drain electrode of the fourth PMOS tube; the drain electrode of the eighth NMOS tube is connected with the drain electrode of the sixth PMOS tube, and the junction is used as the output end of the first-stage amplified voltage signal;
the sources of the third PMOS tube and the fourth PMOS tube are connected with the drain electrode of the second PMOS tube; the grid electrode of the third PMOS tube is connected between two voltage dividing resistors of the linear voltage stabilizer, and the grid electrode of the fourth PMOS tube is connected with a reference voltage;
the sources of the first PMOS tube, the second PMOS tube, the fifth PMOS tube and the sixth PMOS tube are all connected to an analog power supply; the sources of the first NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube are all grounded.
In an alternative scheme, the linear voltage stabilizer further comprises a first resistor, a second resistor, a power tube and an output capacitor;
the grid electrode of the power tube is connected with the grid electrode of the sampling PMOS tube, the source electrode of the power tube is connected with the power supply voltage, the drain electrode of the power tube is connected with the first resistor, the other end of the first resistor is connected with the second resistor, and the other end of the second resistor is grounded; the junction of the first resistor and the second resistor is connected to the grid electrode of the third PMOS tube;
the output capacitor is connected between the drain electrode of the power tube and the ground.
In an alternative scheme, the power tube is a high-voltage PMOS tube.
In an alternative scheme, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, and the sixth PMOS tube are all low-voltage tubes.
The application has the beneficial effects that:
the application integrates the short-circuit protection function into the control main loop of the linear voltage stabilizer, thereby realizing the functions of standby low power consumption (typically 2 uA) and short-circuit protection, and simultaneously having excellent surge voltage suppression capability.
Drawings
The foregoing and other objects, features and advantages of the application will be apparent from the following more particular descriptions of exemplary embodiments of the application as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the application.
Fig. 1 is a circuit diagram of a prior art linear voltage regulator with short-circuit protection.
FIG. 2 is a circuit diagram of a linear voltage regulator according to an embodiment of the present application.
Detailed Description
The application is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present application will become more apparent from the following description and drawings, however, it should be understood that the inventive concept may be embodied in many different forms and is not limited to the specific embodiments set forth herein. The drawings are in a very simplified form and are to non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Example 1
Referring to the circuit in the dashed box on the right side in fig. 2, the present embodiment provides a short-circuit protection circuit of a linear voltage regulator, including:
a seventh PMOS tube P7, an eighth PMOS tube P8, a ninth PMOS tube P9, a ninth NMOS tube N9, a tenth NMOS tube N10, an eleventh NMOS tube HN1, a voltage clamping unit and a sampling PMOS tube MPS;
the seventh PMOS transistor P7 and the eighth PMOS transistor P8 form a PMOS current mirror, a gate and a drain of the seventh PMOS transistor P7 are shorted, a drain of the seventh PMOS transistor P7 is connected to a current source, another end of the current source is grounded, and the current source provides a fixed current to the drain of the seventh PMOS transistor P7; the ninth NMOS tube N9 and the tenth NMOS tube N10 form an NMOS current mirror; the source electrode of the ninth PMOS tube P9 is connected with the drain electrode of the eighth PMOS tube P8, and the drain electrode of the ninth PMOS tube P9 is connected with the drain electrode of the ninth NMOS tube N9; the grid electrode of the ninth PMOS transistor P9 is connected to the voltage signal output end of the pre-amplifier, and the output structure of the pre-amplifier is a rail-to-rail structure (the rail-to-rail structure belongs to a clear structure in the art, and the effect is that the output voltage range is continuous, as in the structure consisting of the sixth PMOS transistor P6, the eighth NMOS transistor N8 and the sixth NMOS transistor N6 in embodiment 2, and the output range is from 0 to avdd); the drain electrode of the tenth NMOS transistor N10 is connected to the source electrode of the eleventh NMOS transistor HN1, the drain electrode of the eleventh NMOS transistor HN1 is connected to the drain electrode of the sampling PMOS transistor MPS, the eleventh NMOS transistor HN1 is a high-voltage transistor, the voltage at one end of the drain electrode of the eleventh NMOS transistor HN1 is higher than the voltage at one end of the source electrode, and the gate electrode of the eleventh NMOS transistor is connected to the low-voltage bias signal generated by the pre-amplifier; the source electrode of the sampling PMOS tube MPS is connected with the power supply voltage VIN, and the grid electrode and the drain electrode of the sampling PMOS tube MPS are in short circuit and connected with the grid electrode of the power tube MP0 of the linear voltage stabilizer;
the voltage clamping unit is connected between the power supply voltage VIN and the drain electrode of the eleventh NMOS tube HN1, and is configured to clamp the lowest voltage at the gate electrode of the sampling PMOS tube MPS.
The drain of the eleventh NMOS transistor HN1 has a high voltage threshold, typically greater than 5V, and the tenth NMOS transistor N10 has a low voltage threshold, so that the source of the eleventh NMOS transistor HN1 needs to output a lower voltage in order to avoid the damage of the tenth NMOS transistor N10, and the gate of the eleventh NMOS transistor HN1 needs to be biased with a low voltage because the voltage of the gate needs to be higher than the voltage of the source.
The grid electrode of the ninth PMOS tube P9 is connected to the output of the front-end first-stage amplifier circuit of the linear voltage stabilizer, the source electrodes of the ninth NMOS tube N9 and the tenth NMOS tube N10 are grounded GND, the source electrodes of the seventh PMOS tube P7 and the eighth PMOS tube P8 are connected to an analog power supply AVDD, and the grid electrode and the drain electrode of the seventh PMOS tube P7 are in short circuit and grounded GND.
In this embodiment, the voltage clamping unit includes: a tenth PMOS tube P10, an eleventh PMOS tube P11 and a twelfth PMOS tube P12; the source electrode of the tenth PMOS transistor P10 is connected to the power voltage VIN, the drain electrode and the gate electrode are shorted and connected to the source electrode of the eleventh PMOS transistor P11, the drain electrode and the gate electrode of the eleventh PMOS transistor P11 are shorted and connected to the source electrode of the twelfth PMOS transistor P12, and the gate electrode and the drain electrode of the twelfth PMOS transistor P12 are shorted and connected to the drain electrode of the eleventh NMOS transistor HN 1.
In another embodiment, the voltage clamping unit may also be in the form of two PMOS transistors, and specifically includes: a tenth PMOS tube and an eleventh PMOS tube; the source electrode of the tenth PMOS tube is connected with the power voltage VIN, the drain electrode and the grid electrode are in short circuit and connected with the source electrode of the eleventh PMOS tube, and the drain electrode and the grid electrode of the eleventh PMOS tube are in short circuit and connected with the drain electrode of the eleventh NMOS tube.
In this embodiment, the seventh PMOS transistor P7, the eighth PMOS transistor P8, the ninth PMOS transistor P9, the ninth NMOS transistor N9, and the tenth NMOS transistor N10 are all low-voltage transistors, and the sampling PMOS transistor MPS is a high-voltage transistor.
The application integrates the short-circuit protection function into the control main loop of the linear voltage stabilizer, thereby realizing the functions of standby low power consumption (typically 2 uA) and short-circuit protection, and simultaneously having excellent surge voltage suppression capability.
Example 2
Referring to fig. 2, the present embodiment provides a linear voltage regulator, which includes the short-circuit protection circuit described in embodiment 1, and further includes a first stage amplifier circuit;
the input end of the first-stage amplifier circuit is connected with an analog power supply AVDD, and the output end of the first-stage amplifier circuit outputs a first bias voltage signal VB1 and a first-stage amplified voltage signal VEA;
the first-stage amplified voltage signal VEA is input to the gate of the ninth PMOS transistor P9; the first bias voltage signal VB1 is input to the gate of the eleventh NMOS transistor HN 1.
In this embodiment, the first stage amplifier circuit includes: the first NMOS tube N1, the second NMOS tube N2, the third NMOS tube N3, the fourth NMOS tube N4, the fifth NMOS tube N5, the sixth NMOS tube N6, the seventh NMOS tube N7, the eighth NMOS tube N8, the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3, the fourth PMOS tube P4, the fifth PMOS tube P5 and the sixth PMOS tube P6; the first PMOS tube P1 and the second PMOS tube P2 form a current mirror structure; the fifth PMOS tube P5 and the sixth PMOS tube P6 form a current mirror structure; the third NMOS tube N3, the fourth NMOS tube N4, the fifth NMOS tube N5 and the sixth NMOS tube N6 form a current mirror structure; the grid electrode and the drain electrode of the first NMOS tube N1 are in short circuit and connected with the source electrode of the second NMOS tube N2, the drain electrode and the grid electrode of the second NMOS tube N2 are in short circuit and connected with an analog power supply AVDD, and the connection part is used as the output end of the first bias voltage signal VB 1; the first bias voltage signal VB1 is input to the gate of the seventh NMOS transistor N7 and the gate of the eighth NMOS transistor N8; the third NMOS tube N3 is a source of a current mirror structure, a grid electrode and a drain electrode of the third NMOS tube N3 are in short circuit and connected to an analog power supply AVDD, and the joint of the grid electrode and the drain electrode is used as an output end of a second bias voltage signal VB 2; the second bias voltage signal VB2 is input to the gate of the fifth NMOS transistor N5 and the gate of the sixth NMOS transistor N6; the drain electrode of the fifth NMOS tube N5 is connected with the source electrode of the seventh NMOS tube N7 and the drain electrode of the third PMOS tube P3; the drain electrode of the sixth NMOS tube N6 is connected with the source electrode of the eighth NMOS tube N8 and the drain electrode of the fourth PMOS tube P4; the drain electrode of the seventh NMOS tube N7 is connected with the drain electrode of the fifth PMOS tube P5; the drain electrode of the eighth NMOS tube N8 is connected with the drain electrode of the sixth PMOS tube P6, and the connection part is used as the output end of the first-stage amplified voltage signal VEA; the sources of the third PMOS tube P3 and the fourth PMOS tube P4 are connected to the drain electrode of the second PMOS tube P2; the grid electrode of the third PMOS tube P3 is connected between two voltage dividing resistors of the linear voltage stabilizer, and the grid electrode of the fourth PMOS tube P4 is connected with a reference voltage VREF; the sources of the first PMOS transistor P1, the second PMOS transistor P2, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are all connected to an analog power supply AVDD; the sources of the first NMOS tube N1, the third NMOS tube N3, the fourth NMOS tube N4, the fifth NMOS tube N5 and the sixth NMOS tube N6 are all grounded to GND.
In this embodiment, the linear voltage regulator further includes a first resistor R1, a second resistor R2, a power tube MP0, and an output capacitor COUT; the grid electrode of the power tube MP0 is connected with the grid electrode of the sampling PMOS tube MPS, the source electrode of the power tube MP0 is connected with the power supply voltage VIN, the drain electrode of the power tube MP0 is connected with the first resistor R1, the other end of the first resistor R1 is connected with the second resistor R2, and the other end of the second resistor R2 is grounded GND; the junction of the first resistor R1 and the second resistor R2 is connected to the gate of the third PMOS tube P3; the output capacitor COUT is connected between the drain of the power tube MP0 and ground.
The power tube is a PMOS tube and is a high-voltage tube. The first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, the eighth NMOS transistor N8, the first PMOS transistor P1, the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, and the sixth PMOS transistor P6 are all low-voltage transistors.
The low-voltage tube refers to a device with VDS withstand voltage less than or equal to 5V; the high-voltage tube refers to a device with VDS withstand voltage not less than 12V. In this embodiment, the analog power AVDD is low voltage 5V, the power voltage VIN is 12V-40V high voltage, and the output voltage vout= (1+r1/R2) VREF. The size ratio of the seventh PMOS tube P7 to the eighth PMOS tube P8 is 1: n; the size ratio of the ninth NMOS transistor N9 to the tenth NMOS transistor N10 is 1: m; the eleventh NMOS tube HN1 is a high-voltage tube for isolating VG (the drain electrode of the eleventh NMOS tube HN 1) from high voltage; the voltage clamping unit formed by the tenth PMOS tube P10, the eleventh PMOS tube P11 and the twelfth PMOS tube P12 is used for clamping the lowest voltage of VG, and the currents of the tenth PMOS tube P10, the eleventh PMOS tube P11 and the twelfth PMOS tube P12 are zero during normal operation; the output current of the linear voltage stabilizer passes through the power tube MP0; sampling PMOS tube MPS is a sampling tube, and sampling output current; the size ratio of the sampling PMOS tube MPS to the power tube MP0 is 1: k, performing K; the output capacitor COUT is used for stabilizing the output voltage. Iload is the load current. The linear voltage regulator of this embodiment may power a Microcontroller (MCU) and a vehicle network transceiver (CAN).
1. When the LDO (linear regulator) is in the light load current Iload_L, the current flowing through the ninth NMOS transistor N9 is
,
The current is smaller than the saturation current of the eighth PMOS tube P8:
referring to fig. 2, ib is a short-circuit protection reference current, since the ninth NMOS transistor N9 and the eighth PMOS transistor P8 are in the same branch, the currents of the two devices must be equal according to KCL law. Therefore, the first stage amplified voltage signal VEA output by the first stage amplifier will rise, and the source terminal voltage of the ninth PMOS transistor P9 (and also the drain terminal of the eighth PMOS transistor P8) will rise, so that the eighth PMOS transistor P8 enters the linear region, i.e. the current flowing through the eighth PMOS transistor P8 when the LDO is lightly loaded is:
during light load, the LDO output current is small, so that the branch currents of the ninth NMOS tube N9 and the ninth NMOS tube N10 are also small, only the first-stage amplifier consumes current, the power consumption of the first-stage amplifier can be designed to be small, and the standby power consumption can be controlled to be extremely low.
2. When the LDO load is gradually increased to iload_h and the current of the ninth NMOS transistor N9 is exactly equal to the saturation current of the eighth PMOS transistor P8, i.e.:
then the output first-stage amplified voltage signal VEA of the first-stage amplifier is reduced, the drain voltage of the eighth PMOS transistor P8 is reduced, and the eighth PMOS transistor P8 just transits from the linear region to the saturation region, at this time:
3. when the load of the LDO further increases (the most extreme case is short-circuited), the current of the eighth PMOS transistor P8 is no longer increased to reach the maximum value because the current of the eighth PMOS transistor P8 is already in the saturation region, and then the ninth NMOS transistor N9, the tenth NMOS transistor N10, and the sampling PMOS transistor MPS also reach the maximum current value, i.e., the maximum output current of the LDO is:
according to the requirement of LDO load capacity, N, IB, K, M parameters which are reasonable in design can be used for limiting the maximum output current Iload_H of the LDO to a safe range, so that the function of short-circuit protection is achieved.
The output current sampled by the sampling PMOS tube MPs is mirrored through a current mirror formed by a ninth NMOS tube N9 and a tenth NMOS tube N10, and compared with the fixed bias current of a seventh PMOS tube P7 mirrored by an eighth PMOS tube P8, the source electrode of the ninth PMOS tube P9 (also the drain electrode of the eighth PMOS tube P8) is controlled by a first-stage amplified voltage signal VEA output by a first-stage amplifier circuit, so that the eighth PMOS tube P8 works in a linear region in light load and is in a saturated region in overcurrent, and the aim of limiting the output current of the LDO is fulfilled. The eighth PMOS tube P8 and the ninth PMOS tube P9 are important loops of the main loop, and integrate the overcurrent protection function into the main loop.
4. When surge voltage occurs, the power supply voltage VIN climbs at an extremely high speed (typically 10V/us), VGS of the power tube MP0 can be instantaneously increased, so that instantaneous large current is output by the power tube MP0, and overshoot is generated by the output voltage VOUT; however, the current of the sampling PMOS tube MPS is also increased proportionally, so that the GATE charge of the power tube MP0 is accelerated, and therefore VG can quickly follow the change of the power voltage VIN, so that the overshoot of the output voltage VOUT is not very large, and the capability of suppressing the surge voltage is achieved.
The linear voltage regulator circuit is manufactured by a semiconductor integrated process.
The above description is only illustrative of the preferred embodiments of the present application and is not intended to limit the scope of the present application, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (9)
1. A short-circuit protection circuit for a linear voltage regulator, comprising:
a seventh PMOS tube, an eighth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a voltage clamping unit and a sampling PMOS tube;
the seventh PMOS tube and the eighth PMOS tube form a PMOS current mirror, the grid electrode and the drain electrode of the seventh PMOS tube are in short circuit, the drain electrode of the seventh PMOS tube is connected with a current source, and the current source supplies fixed current to the drain electrode of the seventh PMOS tube; the ninth NMOS tube and the tenth NMOS tube form an NMOS current mirror; the source electrode of the ninth PMOS tube is connected with the drain electrode of the eighth PMOS tube, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube; the grid electrode of the ninth PMOS tube is connected with the voltage signal output end of the pre-stage amplifier, and the output structure of the pre-stage amplifier is a rail-to-rail structure;
the drain electrode of the tenth NMOS tube is connected with the source electrode of the eleventh NMOS tube, the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the sampling PMOS tube, the eleventh NMOS tube is a high-voltage tube, the voltage at one end of the drain electrode of the eleventh NMOS tube is higher than the voltage at one end of the source electrode, and the grid electrode of the eleventh NMOS tube is connected with a low-voltage bias signal generated by the pre-amplifier; the source electrode of the sampling PMOS tube is connected with the power supply voltage, and the grid electrode and the drain electrode of the sampling PMOS tube are in short circuit and connected with the grid electrode of the power tube of the linear voltage stabilizer;
the voltage clamping unit is connected between the power supply voltage and the drain electrode of the eleventh NMOS tube and is used for clamping the lowest voltage at the grid electrode of the sampling PMOS tube.
2. The short-circuit protection circuit of the linear voltage regulator of claim 1, wherein the seventh PMOS transistor, the eighth PMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are all low voltage transistors, and the sampling PMOS transistor is a high voltage transistor.
3. The short-circuit protection circuit of the linear voltage regulator of claim 1, wherein the voltage clamping unit comprises: a tenth PMOS tube and an eleventh PMOS tube;
the source electrode of the tenth PMOS tube is connected with the power supply voltage, the drain electrode and the grid electrode are in short circuit and connected with the source electrode of the eleventh PMOS tube, and the drain electrode and the grid electrode of the eleventh PMOS tube are in short circuit and connected with the drain electrode of the eleventh NMOS tube.
4. The short-circuit protection circuit of the linear voltage regulator of claim 1, wherein the voltage clamping unit comprises: a tenth PMOS tube, an eleventh PMOS tube and a twelfth PMOS tube;
the source electrode of the tenth PMOS tube is connected with the power supply voltage, the drain electrode and the grid electrode are in short circuit and connected with the source electrode of the eleventh PMOS tube, the drain electrode and the grid electrode of the eleventh PMOS tube are in short circuit and connected with the source electrode of the twelfth PMOS tube, and the grid electrode and the drain electrode of the twelfth PMOS tube are in short circuit and connected with the drain electrode of the eleventh NMOS tube.
5. A linear voltage regulator comprising the short-circuit protection circuit of any one of claims 1-4, further comprising a first stage amplifier circuit;
the input end of the first-stage amplifier circuit is connected with an analog power supply, and the output end of the first-stage amplifier circuit outputs a first bias voltage signal and a first-stage amplified voltage signal;
the first-stage amplified voltage signal is input to the grid electrode of the ninth PMOS tube; the first bias voltage signal is input to the gate of the eleventh NMOS transistor.
6. The linear voltage regulator of claim 5, wherein the first stage amplifier circuit comprises: the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube;
the first PMOS tube and the second PMOS tube form a current mirror structure; the fifth PMOS tube and the sixth PMOS tube form a current mirror structure; the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube form a current mirror structure;
the grid electrode and the drain electrode of the first NMOS tube are in short circuit and connected with the source electrode of the second NMOS tube, the drain electrode and the grid electrode of the second NMOS tube are in short circuit and connected with an analog power supply, and the connection part is used as the output end of the first bias voltage signal; the first bias voltage signal is input to the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube;
the third NMOS tube is a source of a current mirror structure, a grid electrode and a drain electrode of the third NMOS tube are in short circuit and connected to an analog power supply, and the joint of the grid electrode and the drain electrode is used as an output end of a second bias voltage signal; the second bias voltage signal is input to the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube;
the drain electrode of the fifth NMOS tube is connected with the source electrode of the seventh NMOS tube and the drain electrode of the third PMOS tube; the drain electrode of the sixth NMOS tube is connected with the source electrode of the eighth NMOS tube and the drain electrode of the fourth PMOS tube; the drain electrode of the eighth NMOS tube is connected with the drain electrode of the sixth PMOS tube, and the junction is used as the output end of the first-stage amplified voltage signal;
the sources of the third PMOS tube and the fourth PMOS tube are connected with the drain electrode of the second PMOS tube; the grid electrode of the third PMOS tube is connected between two voltage dividing resistors of the linear voltage stabilizer, and the grid electrode of the fourth PMOS tube is connected with a reference voltage;
the sources of the first PMOS tube, the second PMOS tube, the fifth PMOS tube and the sixth PMOS tube are all connected to an analog power supply; the sources of the first NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube are all grounded.
7. The linear voltage regulator of claim 6, further comprising a first resistor, a second resistor, a power tube, and an output capacitor;
the grid electrode of the power tube is connected with the grid electrode of the sampling PMOS tube, the source electrode of the power tube is connected with the power supply voltage, the drain electrode of the power tube is connected with the first resistor, the other end of the first resistor is connected with the second resistor, and the other end of the second resistor is grounded; the junction of the first resistor and the second resistor is connected to the grid electrode of the third PMOS tube;
the output capacitor is connected between the drain electrode of the power tube and the ground.
8. The linear voltage regulator of claim 7, wherein the power tube is a high voltage PMOS tube.
9. The linear voltage regulator of claim 6, wherein the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are low voltage transistors.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311403215.3A CN117148909B (en) | 2023-10-27 | 2023-10-27 | Short-circuit protection circuit of linear voltage stabilizer and linear voltage stabilizer |
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| CN202311403215.3A CN117148909B (en) | 2023-10-27 | 2023-10-27 | Short-circuit protection circuit of linear voltage stabilizer and linear voltage stabilizer |
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| CN117148909B CN117148909B (en) | 2023-12-26 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101165983A (en) * | 2006-10-16 | 2008-04-23 | 深圳安凯微电子技术有限公司 | Current limiting short circuit protection circuit |
| US20110235222A1 (en) * | 2010-03-26 | 2011-09-29 | Panasonic Corporation | Output short to ground protection circuit |
| CN109656300A (en) * | 2019-02-27 | 2019-04-19 | 电子科技大学 | A kind of Fast Load response LDO based on dual power rail power supply |
| CN111338421A (en) * | 2019-12-09 | 2020-06-26 | 重庆西南集成电路设计有限责任公司 | Two-bus power supply linear voltage stabilizer capable of constant current-limiting switching and dual-mode voltage stabilizing circuit |
| CN113778160A (en) * | 2021-09-14 | 2021-12-10 | 无锡英迪芯微电子科技股份有限公司 | No-reference self-starting linear voltage stabilizer |
-
2023
- 2023-10-27 CN CN202311403215.3A patent/CN117148909B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101165983A (en) * | 2006-10-16 | 2008-04-23 | 深圳安凯微电子技术有限公司 | Current limiting short circuit protection circuit |
| US20110235222A1 (en) * | 2010-03-26 | 2011-09-29 | Panasonic Corporation | Output short to ground protection circuit |
| CN109656300A (en) * | 2019-02-27 | 2019-04-19 | 电子科技大学 | A kind of Fast Load response LDO based on dual power rail power supply |
| CN111338421A (en) * | 2019-12-09 | 2020-06-26 | 重庆西南集成电路设计有限责任公司 | Two-bus power supply linear voltage stabilizer capable of constant current-limiting switching and dual-mode voltage stabilizing circuit |
| CN113778160A (en) * | 2021-09-14 | 2021-12-10 | 无锡英迪芯微电子科技股份有限公司 | No-reference self-starting linear voltage stabilizer |
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