CN117135928A

CN117135928A - Integrated circuit structure and forming method thereof

Info

Publication number: CN117135928A
Application number: CN202210610766.6A
Authority: CN
Inventors: 王立为; 李鸿志; 周福兴; 李士勤
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2022-05-17
Filing date: 2022-05-31
Publication date: 2023-11-28
Also published as: US20230380174A1

Abstract

The invention provides an integrated circuit structure and a forming method thereof. The conductive layer is located above the substrate. A plurality of memory elements are stacked over the conductive layer in a vertical direction. The bonding pad is located above the conductive layer. The source line extends upward from the bonding pad and has a lower portion and an upper portion. The lower part is embedded in the bonding pad, and the upper part is provided with a side wall connected with one side wall of the bonding pad. The top of the source line has a first lateral dimension larger than a second lateral dimension of the bonding pad.

Description

Integrated circuit structure and forming method thereof

Technical Field

The present disclosure relates to integrated circuit structures, and more particularly, to integrated circuit structures and methods of forming the same.

Background

The present disclosure relates to semiconductor elements, and in particular, to three-dimensional (3D) memory elements and methods of forming such semiconductor elements.

The semiconductor industry has experienced a rapid increase due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density results from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.

Disclosure of Invention

The present disclosure provides an integrated circuit structure. The integrated circuit structure comprises a substrate, a conductive layer, a plurality of memory elements, bonding pads and source lines. The conductive layer is located above the substrate. A plurality of memory elements are stacked over the conductive layer in a vertical direction. The bonding pad is located above the conductive layer. The source line extends upward from the bonding pad and has a lower portion and an upper portion. The lower part is embedded in the bonding pad, and the upper part is provided with a side wall connected with one side wall of the bonding pad. The top of the source line has a first lateral dimension. The first lateral dimension is greater than a second lateral dimension of one of the bond pads.

In some embodiments, the first lateral dimension of the top of the source line is at least 1.5 times greater than a third lateral dimension of the source line at a location at the same height as a top of the bond pad.

In some embodiments, the integrated circuit structure further comprises: a dielectric material laterally surrounds the source line and the bond pad. The first lateral dimension of the top of the source line is larger than a third lateral dimension of the dielectric material on the bonding pad.

In some implementations, the memory elements each include a gate layer. The gate layer of the memory element extends laterally over the conductive layer, and an upper portion of the source line overlaps the gate layer of the memory element.

In some embodiments, the integrated circuit structure further comprises: a plurality of insulating layers alternately stacked with the memory elements in the vertical direction. The upper portion of the source line overlaps the insulating layer.

The present disclosure provides a method of forming an integrated circuit structure. The method for forming the integrated circuit structure comprises the following steps: forming a multi-layered stacked structure including a plurality of insulating layers and a plurality of sacrificial layers alternately stacked in a vertical direction on a substrate; forming a first via in the multi-layer stack structure; forming a memory layer, a channel layer and a first dielectric material in the first via; forming a second via in the multi-layer stack structure; forming a memory array in a multi-layer stack structure; depositing a second dielectric material over the memory array and in the second via; forming a source line in the second via.

In some embodiments, the method of forming an integrated circuit structure further comprises: forming a bonding pad in the second via, wherein the second dielectric material laterally surrounds the source line and the bonding pad, and a first lateral dimension of a top end of the source line is larger than a second lateral dimension of the second dielectric material on the bonding pad.

In some embodiments, wherein forming the second dielectric material further comprises: a dry etching process is performed on the second dielectric material to remove a overhang of the second dielectric material above the second via. The dry etching process includes introducing carbon monofluoride (C _x F _y ) And (c) introducing a gas over the second dielectric material, wherein x and y are integers, and y/x is less than 3.

In some embodiments, the fluorocarbon gas comprises C ₄ F ₆ 、C ₄ F ₈ 、C ₅ F ₈ 、C ₃ F ₈ Or any combination of the foregoing gases.

In some embodiments, the top of the second via has a first lateral dimension. The first lateral dimension is at least 1.5 times greater than a second lateral dimension of the intermediate portion of the second through hole.

Drawings

The embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various features are not drawn to scale according to standard specifications in the industry. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1-13, 14A, 15A, and 16 illustrate cross-sectional views of methods of forming integrated circuit structures at various stages according to some embodiments of the present disclosure.

Fig. 14B and 15B illustrate cross-sectional views of methods of forming integrated circuit structures at various stages according to some embodiments of the present disclosure.

Fig. 14C and 15C illustrate cross-sectional views of methods of forming integrated circuit structures at various stages according to some embodiments of the present disclosure.

Description of the reference numerals

100: integrated circuit structure

101: semiconductor substrate

102: isolation layer

103: conductive layer

103t: top surface

104: isolation layer

105: contact plug

105t: top surface

107: storage layer

108: channel layer

109: dielectric material

110: multi-layer stack structure

110t: top surface

111-115: sacrificial layer

120: gate layer

121-126: insulating layer

127: memory cell

131: bonding pad

133: dielectric material

133a: upper curved surface

133b: lower inclined surface

135: bonding pad

135s: side wall

135t: top end

137: metal plug

137m: lower part of

137t: top end

137u: upper part

137w: bottom end

137a: upper concave side wall

137b: concave side wall

139: interlayer dielectric layer

141: connecting conductive column

143: bit line

200: integrated circuit structure

233: dielectric material

233a: inclined plane

237: metal plug

237t: top end

237w: bottom end

237a: upper inclined side wall

237b: concave side wall

300: integrated circuit structure

333: dielectric material

333a: upper inclined plane

333b: lower inclined plane

333c: intermediate surface

337: metal plug

337t: top end

337w: bottom end

337a: upper side wall

337b: lower side wall

337c: intermediate surface

C1: sharp angle

D1: transverse dimension

D2: transverse dimension

O1: contact opening

O2: through hole

O21: upper part O3: through hole

O31: upper part

O32: lower part of

P1: etching process

P2: planarization process

P3: etching back process

P4: etching process

P5: etching back process

P6: dry etching process

P7: planarization process

P8: dry etching process

P9: dry etching process

R: groove

R1: round corner

R2: sharp angle

R3: sharp angle

R4: sharp angle

S1: space of

W1: width of (L)

W2: width of (L)

W3: width of (L)

Wb: width of (L)

Wm: width of (L)

Wt: width of (L)

X: direction of

Y: direction of

Z: direction of

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "under … …," "under … …," "lower," "over … …," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, "about," "approximately," or "substantially" shall generally refer to within 20%, or within 10%, or within 5% of a given value or range. However, those skilled in the art will recognize that the values or ranges referenced throughout the description are merely examples, and may decrease as integrated circuits scale down. The numbers given herein are approximations to the by the use of the antecedent "about," "substantially," or "substantially," unless expressly stated otherwise.

For the development of semiconductor devices, a memory device with high storage density is one direction of development. Thus, a three-dimensional (3D) integrated circuit (integrated circuit, IC) memory element, such as: three-dimensional NAND can provide high storage density by its multi-layer structure. However, the more the number of layers stacked in the three-dimensional NAND, the greater the difficulty in forming the source line in the three-dimensional NAND, which may result in the formation of a gap in the source line. After planarization on the source line, the etching gas (e.g., fluorine) will be trapped/trapped in the gap and affect subsequent processes (e.g., fluorine leakage).

Accordingly, in various embodiments, the present disclosure provides a top widening etch process (top widen etching process) that can avoid forming seams in the source lines. Specifically, the top widening etching process is performed by introducing a polymer etching gas on a dielectric material at a low pressure to modify a source line channel, and then a source line is formed in the modified source line channel. The top widening etch process may increase the ability of the plasma to impinge vertically down on the dielectric material to enlarge the upper portion of the source line channel while simultaneously removing only minimally the lower portion of the dielectric material in the source line channel. Accordingly, a difference between upper and lower portions of the source line channel may be increased to improve a gap fill process tolerance (gap fill window) of a deposition process performed subsequently to form the source line and to avoid forming a gap in the source line.

Fig. 1-13, 14A, 15A, and 16 illustrate cross-sectional views of methods of forming an integrated circuit structure 100 at various stages according to some embodiments of the present disclosure. Referring to fig. 1, in some embodiments, an isolation layer 102, a conductive layer 103, and an isolation layer 104 are sequentially formed on a semiconductor substrate 101. In some embodiments, the conductive layer 103 may be used as a common source line of the memory device. Next, a plurality of contact openings O1 are formed through the isolation layer 102, the conductive layer 103, and the isolation layer 104 to expose a plurality of portions of the semiconductor substrate 101. Next, a plurality of contact plugs 105 are respectively formed in the plurality of contact openings O1 to electrically contact the semiconductor substrate 101 through the conductive layer 103.

In some embodiments, the method for forming the contact plug 105 includes performing an etching process to remove portions of the isolation layer 102, the conductive layer 103 and the isolation layer 104, thereby forming a plurality of contact openings O1. Next, a conductive material, such as: polysilicon, by a deposition process such as: a low pressure chemical vapor deposition (low pressure chemical vapor deposition, LPCVD) process is formed on the isolation layer 104 to fill the plurality of contact openings O1. Next, a planarization process, such as: a chemical mechanical polishing (chemical mechanical polish, CMP) process is performed using the isolation layer 104 as a stop layer to remove conductive material located over the isolation layer 104, thereby forming the contact plug 105. Thus, each contact plug 105 has a top surface 105t, the top surface 105t being substantially higher than the top surface 103t of the conductive layer 103 and substantially flush with the top surface 104t of the isolation layer 104.

In some embodiments, the material of the semiconductor substrate 101 may include a p-type doped semiconductor material or an n-type doped semiconductor material or an undoped semiconductor material, for example: polysilicon, germanium, or any other suitable semiconductor material. In some embodiments, the isolation layers 102, 104 may comprise dielectric materials, such as: silicon oxide, silicon nitride, silicon oxynitride, silicate, any combination of the foregoing, or any suitable dielectric material. In some embodiments, the material of the contact plug 105 may include TiN, taN, ti, ta, cu, al, ag, W, ir, ru, pt, any combination of the foregoing materials, or other suitable conductive material.

Referring to fig. 2, a multi-layered stack structure 110 including insulating layers 121 to 126 and sacrificial layers 111 to 115 alternately stacked is formed on a semiconductor substrate 101. The insulating layers 121-126 and the sacrificial layers 111-115 are stacked extending parallel to each other and alternating along the direction Z. The insulating layers 121 and 126 serve as the bottom-most layer and top-most layer of the multi-layer stack structure 110, respectively. In some embodiments, the multi-layer stack 110 may also be referred to as a film-like stack.

In some embodiments, the sacrificial layers 111-115 may comprise silicon nitride compounds, such as: silicon nitride, silicon oxynitride, silicon carbide nitride, or any combination of the foregoing. In some embodiments, the topmost sacrificial layer 115 may also be referred to as a virtual source line silicon nitride layer, while the sacrificial layers 111-114 may also be referred to as virtual word line silicon nitride layers. In some embodiments, the insulating layers 121-126 may comprise dielectric materials, such as: silicon oxide, silicon nitride, silicon oxynitride, silicate, or any combination of the foregoing. In some embodiments, the topmost insulating layer 126 may also be referred to as a hard mask oxide layer. However, it should be noted that in embodiments of the present disclosure, the material of sacrificial layers 111-115 is different from the material of insulating layers 121-126. For example, the sacrificial layers 111-115 may be made of silicon nitride, and the insulating layers 121-126 may be made of silicon oxide. In some embodiments, the sacrificial layers 111-115 and the insulating layers 121-126 may be formed by low pressure chemical vapor deposition (low pressure chemical vapor deposition, LPCVD).

Referring to fig. 3, an etching process P1, for example: a via process hole etch process is performed to form a plurality of vias O2 through the multi-layer stack structure 110 to expose the contact plugs 105. In some embodiments, the etching process P1 may be an anisotropic etching process, such as: reactive ion etching (reactive ion etching, RIE) process. The etching process P1 is performed on the multi-layered stack 110 using a patterned hard mask layer (not shown) as an etching mask. The via O2 may be a circular hole-like via extending through the multi-layer stack structure 110 in the direction z and extending to the top surface 105t of the contact plug 105. The exposed portions of the sacrificial layers 111-115 and the insulating layers 121-126 may serve as sidewalls of the via hole O2.

Referring to fig. 4, a memory layer 107 and a channel layer 108 are sequentially formed on the sidewall of the via O2. Thus, the memory layer 107 is disposed between the channel layer 108 and the sacrificial layers 111-115. In some embodiments, the storage layer 107 may comprise a composite layer. The aforementioned composite layer has, but is not limited to, an oxide-nitride-oxide (ONO) structure, or an oxide-nitride-oxide (ONONO) structure, and is conformally formed to cover the sidewalls and bottom of the via O2 above the multilayer stack structure 110. Next, an etching process is performed to remove the portion of the aforementioned composite layer on the top surface 110t of the multi-layer stack structure 110 and the bottom of the via O2, such that the top surface 105t of the contact plug 105 is exposed.

The channel layer 108 is then conformally deposited over the storage layer 107, so that the integrated circuit structure 100 may include vertical channel flash memory elements. The channel layer 108 is in electrical contact with the top surface 105t of the contact plug 105. In some embodiments, the channel layer 108 may comprise a semiconductor material, such as: polysilicon, germanium, or other doped or undoped semiconductor material. For example, the material of the channel layer 108 may include undoped polysilicon.

Referring to fig. 5, a dielectric material 109 is deposited over the channel layer 108 and fills in the via O2. In some embodiments, the material of the dielectric material 109 may comprise silicon oxide. In some embodiments, dielectric material 109 may be made using the same materials as insulating layers 121-126. In some embodiments, dielectric material 109 may be made using a different material than insulating layers 121-126.

Referring to fig. 6, a planarization process P2 (e.g., a chemical mechanical polishing (chemical mechanical polishing, CMP) process) is performed to remove excess dielectric material 109 and channel layer 108 over the top surface 110t of the multi-layer stack 110. After this step, the channel layer 108 surrounds the dielectric material 109 in the via O2. The memory layer 107 surrounds the channel layer 108 located in the via O2.

Referring to fig. 7, an etch back (etching back) process P3 is performed on the dielectric material 109, the channel layer 108, and the memory layer 107 to reproduce the upper portion O21 of the via O2. In some embodiments, the etch-back process P3 may be a wet etching process, such as: the semiconductor substrate 101 is immersed in hydrofluoric acid (hydrofluoric acid, HF). In some embodiments, the etch-back process P3 may be a dry etching process. For example, the dry etching process may be performed using hydrofluoric acid/ammonia (HF/NH ₃ ) Or nitrogen trifluoride/ammonia (NF) ₃ /NH ₃ ) As an etching gas.

Referring to fig. 8, a bonding pad 131 is formed in the upper portion O21 of the via O2 and is located on the dielectric material 109 to form an electrical contact with the channel layer 108. In some embodiments, the bond pad 131 is formed by depositing polysilicon, germanium, or doped semiconductor material over the multi-layer stack structure 110. Generally, the aforementioned doped semiconductor material may use an N-type dopant (n+), for example: phosphorus or arsenic. A planarization process may then be performed to remove excess semiconductor material above the top surface 110t of the multi-layer stack 110. After this step is performed, the bonding pad 131 may be formed as shown in fig. 7. In some embodiments, the bond pad 131 may be P-doped (P ⁺ ) And a polysilicon bonding pad.

Referring to fig. 9, an etching process P4 is performed to form a via O3 passing through the multi-layered stack structure 110 in the direction Z and terminating at the top surface 103t of the conductive layer 103, whereby the via O3 may partially expose the sacrificial layers 111-115 and the insulating layers 121-126. In some embodiments, the etching process P4 may be an anisotropic etching process, such as: reactive ion etching (reactive ion etching, RIE) process. The etching process P4 is performed on the multi-layer stack 110 using a patterned hard mask layer (not shown) as an etching mask. As shown in fig. 9, when the etching process P4 is completed, the through hole O3 may be formed to have a bowl-shaped cross-sectional profile. Specifically, when a cross section is under the foot, the width of the through hole O3 may increase from the bottom portion of the through hole O3 to the middle portion of the through hole O3, and decrease from the middle portion of the through hole O3 to the top portion of the through hole O3. In some embodiments, the via O3 may have a maximum width at the same level as one of the sacrificial layers 111-115 and the insulating layers 122-125 in the multi-layer stack 110. In some embodiments, the through hole O3 may have a maximum width Wm at a middle position of the through hole O3, the maximum width Wm being greater than widths Wb and Wt of bottom and top ends of the through hole O3. In some embodiments, the maximum width Wm of the via O3 is at the same level as the top surface of the highest one of the sacrificial layers 111-115. In some implementations, the via O3 may also be referred to as a source line channel (source line trench, SLT). In some embodiments, the width may also be referred to as the lateral dimension.

Referring to fig. 10, sacrificial layers 111-115 are used, for example: phosphoric acid (H) ₃ PO ₄ ) And removed through the via O3 to expose a portion of the memory layer 107. Thus, the space S1 is formed to inherit the shape of the sacrificial layers 111 to 115.

Referring to fig. 11, a plurality of gate layers 120 are formed in the space S1 through the via holes O3. Accordingly, a plurality of memory cells 127 may be defined at locations where the gate layer 120, the memory layer 107, and the channel layer 108 meet to form a memory cell array in the multi-layer stack structure 110. In some implementations, the memory cells 127 may also be referred to as memory elements. In some embodiments, the material of the gate layer 120 may include polysilicon, metal, or other suitable conductive material. In some embodiments, the gate layer 120 may include a plurality of metal layers, such as: tiN/W, taN/W, taN/Cu or other suitable metal layers. In some embodiments, the gate layer 120 may include a dielectric layer, such as: alOx. For example, each gate layer 120 may be a multi-layer structure including a high dielectric constant material layer (e.g., hfO) _x Layers or AlO _x Layer), tiN layer, and tungsten layer. In some implementations, lateral ends of at least one of the plurality of gate layers 120 may be recessed toward the storage layer 107.

Referring to fig. 12, a dielectric material 133 is deposited over the multi-layer stack structure 110 and fills in the via O3 to line the sidewalls of the via O3. In some embodiments, the material of the dielectric material 133 may include a dielectric material, for example: silicon oxide, silicon nitride, silicon oxynitride, silicate, any combination of the foregoing, or any suitable dielectric material. In some embodiments, the material of the dielectric material 133 may be the same as that of the insulating layers 121-126. In some embodiments, the material of the dielectric material 133 may be different from the material of the insulating layers 121-126. Next, an etching process is performed to remove the dielectric material 133 from the portion of the top surface 103t of the conductive layer 103 so that the conductive layer 103 is exposed.

Referring to fig. 13, a bonding pad 135 is formed in the bottom portion of the via hole O3 to make electrical contact with the conductive layer 103. In some embodiments, the bond pad 135 is formed by depositing polysilicon, germanium, or doped semiconductor material over the multi-layer stack structure 110. Generally, the doped semiconductor material may use an N-type dopant (N ⁺ ) For example: phosphorus or arsenic. A planarization process may then be performed to remove excess semiconductor material above the top surface 110t of the multi-layer stack 110. Next, an annealing (annealing) process is performed on the bonding pad 135. Next, an etch back (etching back) process P5 is performed on the bonding pad 135 to reproduce the upper portion O31 of the through hole O3. In some embodiments, the etch-back process P5 may be a wet etching process, such as: the semiconductor substrate 101 is immersed in hydrofluoric acid (hydrofluoric acid, HF). In some embodiments, the etch-back process P5 may be a dry etching process. For example, the dry etching process may be performed using hydrofluoric acid/ammonia (HF/NH ₃ ) Or nitrogen trifluoride/ammonia (NF) ₃ /NH ₃ ) As an etching gas. After this step is performed, the bond pad 135 may be formed as shown in fig. 13. In some embodiments, the bond pad 135 may be P-doped (P ⁺ ) And a polysilicon bonding pad. In some embodiments, the bond pad 135 has a recess R on its top surface due to the nature of the deposition.

Referring to fig. 14A, a dry etching process P6 is performed on the dielectric material 133 to remove the sharp corner C1 (see fig. 13) on the dielectric material 133 near the via hole O3, so that the lateral dimension D1 of the upper portion O31 of the via hole O3 can be enlarged, thereby improving the gap filling process tolerance of the subsequent one or more deposition processes (e.g., the process for forming the metal plug 137 located in the via hole O3 as shown in fig. 15A) and avoiding the formation of a gap (sea) in the metal plug 137. In some embodiments, the dry etching process P6 may also be referred to as a top widening etching process. In some embodiments, sharp corner C1 may also be referred to as a overhanging portion.

If the lateral dimension D1 of the upper portion O31 of the via O3 is smaller than the lateral dimension D2 of the via O3 at a level with the topmost end of the bond pad 135 (e.g., a via having a bowl-shaped profile), the gap-filling process tolerance of the via O3 may be too small to allow a subsequent deposition process to be properly performed in the via having the bowl-shaped profile, and thus a gap may be formed in the metal plug in the via O3. After the planarization process is performed on the metal plug, the etching gas (e.g., fluorine) will be trapped/trapped in the gap and affect subsequent processes (e.g., fluorine leakage).

Accordingly, the present disclosure provides a method that may avoid the formation of a gap in the metal plug in the via O3. Specifically, the dry etching process P6 is performed by introducing a polymer etching gas into a process chamber having the semiconductor substrate 101 therein. After introducing the polymer chemistry into the process chamber, a plasma (plasma) is triggered to form. The dry etching process P6 moves ions in the plasma up and down with respect to the surface of the semiconductor substrate 101.

In some embodiments, the wafer support structure below the semiconductor substrate 101 may serve as a plate of the capacitive coupling structure, while the conductive plasma above the semiconductor substrate 101 provides the complementary electrode. A Radio Frequency (RF) bias power of the dry etching process P6 is electrically connected to the wafer support to generate an electric field orthogonal to the surface of the semiconductor substrate 101, which accelerates plasma ions into and out of the surface of the semiconductor substrate 101. Ion sputtering etches the surface of the semiconductor substrate 101 by physically bombarding the surface, thereby removing sharp corners C1 of the dielectric material 133 (see fig. 13).

In some embodimentsIn this way, the dry etching process P6 may be a plasma etching process, and uses a polymer gas (e.g., carbon fluoride (C) _x F _y ) Oxygen (O) ₂ ) And argon (Ar) and under low pressure, which increases the ability of the plasma to impinge vertically downward on the dielectric material 133 to enlarge the upper portion O31 of the via O3 while simultaneously removing only minimally the lower portion of the dielectric material 133 in the via O3. Accordingly, the difference between the upper portion O31 and the lower portion O32 of the via hole O3 may be increased to improve the gap-filling process tolerance of the subsequent deposition process. By way of example and not limitation of the present disclosure, the lateral dimension D1 of the via O3 may be at least 1.5 times greater than the lateral dimension D2 of the via O3, wherein the lateral dimension D2 is located at a level with the topmost end of the bond pad 135.

In some embodiments, the high polymerization gas (e.g., carbon fluoride (C) _x F _y ) A gas, where x and y are integers, respectively, and y/x is less than 3) may provide more plasma species for sputter etching the upper layer of dielectric material 133. In some embodiments, the fluorocarbon gas may comprise C ₄ F ₆ 、C ₄ F ₈ 、C ₅ F ₈ 、C ₃ F ₈ Or any combination of the foregoing gases. In some embodiments, the etching gas used in the dry etching process P6 may be different from the etching gas used in the etch-back process P5 (see fig. 13) and/or the etching process P4 (see fig. 9). During the etching, the flow rate of the polymer gas into the processing chamber in the dry etching process P6 may be in the range of about 20 to 50sccm (e.g., 20, 30, 40, or 50 sccm), and the flow rate of the argon gas into the processing chamber may be in the range of about 200 to 500sccm (e.g., 200, 250, 300, 350, 400, 450, or 500 sccm).

In some embodiments, the pressure in the dry etching process P6 may be in the range of about 10 to 100mT (e.g., about 10, 20, 30, 40, 50, 60, 70, 80, 90, or 100 mT). In some embodiments, the dry etching process P6 may be performed at a pressure lower than that of the etch-back process P5 (see fig. 13) and/or the etching process P4 (see fig. 9). In some embodiments, the duration of the dry etching process P6 may be greater than about 15 seconds. During execution of the dry etching process P6, a plasma may be formed by opening a top RF source generator having a frequency in the range of about 1 to 3MHz (e.g., 1, 1.5, 2, 2.5, or 3 MHz) and a power in the range of about 800 to 1200 (e.g., 800, 900, 1000, 1100, or 1200W), and an RF bias generator having a frequency in the range of about 25 to 35MHz (e.g., 25, 27, 30, or 35 MHz) and a power in the range of about 3000 to 4000 (e.g., 3000, 3500, or 4000W). In some embodiments, the increase of the rf bias power of the rf bias generator may increase the difference in width between the upper portion O31 and the lower portion O32 of the via O3, so that the gap-filling process tolerance of the subsequent deposition process may be improved.

Accordingly, the dry etching process P6 may inhibit formation of overhangs (overhangs) on the dielectric material 133, thereby improving the gap-filling process tolerance of one or more subsequent deposition processes (e.g., the process of forming the metal plugs 137 as shown in FIG. 15A) as compared to the case where the dry etching process P6 is not performed. The sputter etching in the dry etching process P6 may result in forming rounded corners R1 on the dielectric material 133, the rounded corners R1 including an upper curved surface 133a and a lower inclined surface 133b having a steeper slope than the curved surface 133 a. The formation of the upper curved surface 133a and the lower inclined surface 133b widens the remaining portion of the upper portion O31 of the via O3 in the dielectric material 133 as it extends away from the bond pad 135, thereby improving the gap-fill process tolerance of one or more subsequent deposition processes. In some embodiments, the remaining portion of the dielectric material 133 above the via O3 as shown in fig. 14A may also be referred to as a red wine glass profile. In some implementations, the present disclosure may also be applied to other dielectric materials or conductance etches (conducing etchings) in dynamic random access memory (dynamic random access memory, DARM), NOR flash memory (NOR flash memory), or NAND flash memory (NAND flash memory).

Referring to fig. 15A, a metal plug 137 is formed at an upper portion O31 of the via hole O3. Specifically, a conductive material is deposited over the multi-layer stack structure 110 and fills in the via O3. Next, a planarization process P7, such as a chemical mechanical polishing (chemical mechanical polishing, CMP) process, is performed to remove excess conductive material over the top surface 110t of the multi-layer stack structure 110. After this step is performed, a metal plug 137 is formed in the through-hole O3. The metal plug 137 may be electrically insulated from the gate layer 120 by the dielectric material 133 and electrically contact the conductive layer 103 by the bonding pad 135. In some embodiments, the metal plug 137 may also be referred to as a source line. In some embodiments, the metal plugs 137 may comprise TiN, taN, ti, ta, cu, al, ag, W, ir, ru, pt, any combination of the above materials, or other suitable conductive materials.

The metal plug 137 extends upward from the bonding pad 135 and has a lower portion 137m and an upper portion 137u. The lower portion 137m of the metal plug 137 is embedded in the bonding pad 137. In some embodiments, an upper portion 137u of the metal plug 137 may have an upper concave sidewall 137a, and a lower portion 137m of the metal plug 137 may have a lower concave sidewall 137b. The upper concave side wall 137a of the upper portion 137u of the metal plug 137 may be connected to the side wall 135s of the bonding pad 135. The metal plug 137 may have a width that increases from its bottom end 137w to its top end 137 t. The width W1 of the top end 137t of the metal plug 137 is greater than the width of the bonding pad 135. In some embodiments, the width W1 of the top end 137t of the metal plug 137 may be at least 1.5 times greater than the width W2 of the metal plug 137 flush with the top end 135t of the bonding pad 135. In some embodiments, the top 137t or the upper portion 137u of the metal plug 137 may overlap the gate layer 120. In some embodiments, the lateral dimension of the top end 137t of the metal plug 137 may be greater than the maximum lateral dimension of the via O3. In some embodiments, no gaps are present in the metal plugs 137. The dielectric material 133 laterally surrounds the metal plugs 137 and the bond pads 135. In some embodiments, the width W1 of the top 137t of the metal plug 137 may be greater than the width W3 of the dielectric material 133 on the bonding pad 135. In some embodiments, an upper portion 137u of the metal plug 137 may overlap the insulating layers 122-125.

Referring to fig. 16, an inter-layer dielectric (ILD) layer 139 is formed over the dielectric material 133 and the metal plug 137. Next, a plurality of bit lines (bit lines) 143 are electrically connected to the bonding pads 131 through interconnection conductive pillars 141 formed in the interlayer dielectric layer 139. Next, after a series of back end of line (BEOL) processes (not shown) are performed, a base circuit structure 100 including a plurality of memory cells 127 is formed as shown in fig. 16. In some embodiments, the memory cells 127 defined by the gate layer 120, the memory layer 107, and the channel layer 108 may be electrically coupled to a decoder (not shown) through the bit lines 143, for example: a row decoder or a column decoder. The current from the bit line 143 may flow to ground through the channel layer 108, the contact plug 105, the conductive layer 103 (as a bottom common source line), the bond pad 131, and the metal plug 134. In other words, a current path for performing the read/program operation does not flow through the semiconductor substrate 101. Accordingly, a current path for performing a read/write operation can be shortened, and thus the operating resistance and power consumption of the memory element can be reduced.

In some embodiments, the interlayer dielectric 139 may comprise a dielectric material, such as: silicon oxide, silicon nitride, silicon oxynitride, silicate, any combination of the foregoing, or any suitable dielectric material. In some embodiments, the material of the bit line 143 may include TiN, taN, ti, ta, cu, al, ag, W, ir, ru, pt, any combination of the above materials, or other suitable conductive materials. In some embodiments, the material of the interconnect conductive posts 141 may comprise TiN, taN, ti, ta, cu, al, ag, W, ir, ru, pt, any combination of the foregoing materials, or other suitable conductive materials.

Fig. 14B and 15B illustrate cross-sectional views of methods of forming integrated circuit structure 200 at various stages according to some embodiments of the present disclosure. The process of forming the integrated circuit structure 200 is substantially the same as the process of forming the integrated circuit structure 100 described above, and is not repeated here for the sake of clarity. The profile of the metal plug 237 in fig. 14B and 15B is different from the profile of the metal plug 137 in fig. 1-13, 14A, 15A, 16.

Fig. 14B illustrates an integrated circuit structure 200 corresponding to the steps of fig. 14A, according to some embodiments of the present disclosure. As shown in fig. 14B, the dry etching process P8 may be a plasma etching process and performed using a polymer gas and at a low pressure, which increases the ability of the plasma to strike the dielectric material 233 vertically downward. The etching gas may comprise a high polymerization gas, such as: C4F6, C4F8, C5F8, C3F8, or combinations thereof. The dry etch process P8 may inhibit formation of overhangs (overhangs) on the dielectric material 233 compared to a case where the dry etch process P8 is not performed, thereby improving the gap fill process tolerance of one or more subsequent deposition processes (e.g., the process of forming the metal plugs 237 as shown in fig. 15B). The sputter etch in dry etch process P8 may result in the formation of sharp corners R2 on dielectric material 233, sharp corners R2 including bevel 233a. The formation of the bevel 233a widens the remaining portion of the upper portion O31 of the via O3 in the dielectric material 233 as it extends away from the bond pad 135, thereby improving the gap-fill process tolerance of one or more subsequent deposition processes. In some embodiments, the remaining portion of the dielectric material 233 shown in fig. 14B above the via O3 may also be referred to as an angled profile.

Fig. 15B illustrates an integrated circuit structure 200 corresponding to the steps of fig. 14B, according to some embodiments of the present disclosure. As shown in fig. 15B, the metal plug 237 may have an upper sloped sidewall 237a and a lower concave sidewall 237B. The metal plug 237 may have a width that increases from its bottom end 237w to its top end 237 t. Specifically, the width of the top end 237t of the metal plug 237 may be at least 1.5 times greater than the width of the metal plug 237 flush with the top end 135t of the bond pad 135. In some embodiments, the lateral dimension of the top end 237t of the metal plug 237 may be at least greater than the maximum lateral dimension of the via O3. In some embodiments, no gaps are present in metal plugs 237.

Fig. 14C and 15C illustrate cross-sectional views of methods of forming integrated circuit structure 300 at various stages according to some embodiments of the present disclosure. The process of forming the integrated circuit structure 300 is substantially the same as the process of forming the integrated circuit structure 100 described above, and is not repeated here for the sake of clarity. The profile of metal plug 337 in fig. 14C and 15C is different from the profile of metal plug 137 in fig. 1-13, 14A, 15A, and 16.

FIG. 14C depicts a corresponding diagram according to some embodiments of the present disclosure14A, and a step of the integrated circuit structure 300. As shown in fig. 14C, the dry etching process P9 may be a plasma etching process and performed using a high molecular gas at a low pressure, which increases the ability of the plasma to strike the dielectric material 333 vertically downward. The etching gas may comprise a high polymerization gas, such as: c (C) ₄ F ₆ 、C ₄ F ₈ 、C ₅ F ₈ 、C ₃ F ₈ Or a combination thereof. The dry etching process P9 may inhibit formation of overhangs (overhangs) on the dielectric material 333, thereby improving the gap-fill process tolerance of one or more subsequent deposition processes (e.g., the process of forming the metal plug 337 as shown in fig. 15C) as compared to the case where the dry etching process P9 is not performed.

Sputter etching in dry etch process P9 may result in formation of sharp corners R3, R4 on dielectric material 333, sharp corners R3, R4 including upper bevel 333a, lower bevel 333b, and intermediate surface 333c. The upper ramp 333a is laterally retracted from the top of the lower ramp 333b, and the intermediate surface 337c connects the top of the lower ramp 333b to the bottom of the upper ramp 333 a. The formation of the upper and lower ramps 333a, 333b widens the remaining portion of the upper portion O31 of the via O3 in the dielectric material 333 as it extends away from the bond pad 135, thus improving the gap-fill process tolerance of one or more subsequent deposition processes. In some embodiments, the remaining portion of the upper portion O31 of the via O3 in the dielectric material 333 as shown in fig. 14C may also be referred to as a stepped profile.

Fig. 15C illustrates an integrated circuit structure 300 corresponding to the steps of fig. 14C, according to some embodiments of the present disclosure. As shown in fig. 15C, the metal plug 337 includes an upper side wall 337a, a lower side wall 337b receding laterally from a bottom of the upper side wall 337a, and an intermediate surface 337C connecting the bottom of the upper side wall 337a to a top of the lower side wall 337 b. The metal plug 337 may have a width that increases from its bottom end 337w to its top end 337 t. Specifically, the width of the top end 337t of the metal plug 337 may be at least 1.5 times greater than the width of the metal plug 337 flush with the top end 135t of the bond pad 135. In some embodiments, the lateral dimension of the top end 337t of the metal plug 337 may be at least greater than the maximum lateral dimension of the through hole O3. In some embodiments, no gap is present in metal plug 337.

Thus, based on the discussion above, it can be seen that the present disclosure has advantages. However, it should be understood that other embodiments may provide additional advantages, and that not all advantages are necessarily disclosed in the present invention. Furthermore, no particular advantage is required for use in all embodiments. In various embodiments of the present disclosure, a top widening etch process is provided that can avoid the formation of seams in the source lines. Specifically, the top widening etching process is performed by introducing a polymer etching gas on a dielectric material at a low pressure to modify a source line channel, and then a source line is formed in the modified source line channel. The top widening etch process may increase the ability of the plasma to impinge vertically down on the dielectric material to enlarge the upper portion of the source line channel while simultaneously removing only minimally the lower portion of the dielectric material in the source line channel. Accordingly, a difference between upper and lower portions of the source line channel may be increased to improve a gap fill process tolerance (gap fill window) of a deposition process performed subsequently to form the source line and to avoid forming a gap in the source line.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the embodiments of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. An integrated circuit structure, comprising:

a substrate;

a conductive layer over the substrate;

a plurality of memory elements stacked over the conductive layer in a vertical direction;

a bonding pad located above the conductive layer; and

a source line extending upward from the bonding pad and having a lower portion embedded in the bonding pad and an upper portion having a sidewall connected to a sidewall of the bonding pad, wherein a top end of the source line has a first lateral dimension larger than a second lateral dimension of the bonding pad.

2. The integrated circuit structure of claim 1, wherein the first lateral dimension of the top of the source line is at least 1.5 times greater than a third lateral dimension of the source line at a location at a same height as a top of the bond pad.

3. The integrated circuit structure of claim 1, further comprising:

a dielectric material laterally surrounding the source line and the bond pad, wherein the first lateral dimension of the top of the source line is greater than a third lateral dimension of the dielectric material on the bond pad.

4. The integrated circuit structure of claim 1, wherein the memory elements each include a gate layer, the gate layers of the memory elements extend laterally over the conductive layer, and the upper portion of the source line overlaps the gate layers of the memory elements.

5. The integrated circuit structure of claim 4, further comprising:

a plurality of insulating layers alternately stacked with the memory elements in the vertical direction, wherein the upper portion of the source line overlaps the insulating layers.

6. A method of forming an integrated circuit structure, comprising:

forming a multi-layered stacked structure including a plurality of insulating layers and a plurality of sacrificial layers alternately stacked in a vertical direction on a substrate;

forming a first through hole in the multi-layer stack structure;

forming a memory layer, a channel layer and a first dielectric material in the first through hole;

forming a second through hole in the multi-layer stack structure;

forming a memory array in the multi-layer stack structure;

forming a second dielectric material over the memory array and in the second via; and

a source line is formed in the second via.

7. The method of forming an integrated circuit structure of claim 6, further comprising: forming a bonding pad in the second via, wherein the second dielectric material laterally surrounds the source line and the bonding pad, and a first lateral dimension of a top end of the source line is larger than a second lateral dimension of the second dielectric material on the bonding pad.

8. The method of forming an integrated circuit structure of claim 6, wherein forming the second dielectric material further comprises: performing a dry etching process on the second dielectric material to remove the second dielectric material located at the second positionA overhang over the two vias, the dry etching process comprising introducing a fluorocarbon (C _x F _y ) And (c) introducing a gas over the second dielectric material, wherein x and y are integers, and y/x is less than 3.

9. The method of forming an integrated circuit structure of claim 8, wherein the carbon fluoride gas comprises C ₄ F ₆ 、C ₄ F ₈ 、C ₅ F ₈ 、C ₃ F ₈ Or any combination of the foregoing gases.

10. The method of claim 6, wherein a top end of the second via has a first lateral dimension that is at least 1.5 times greater than a second lateral dimension of a middle portion of the second via.