TWI798088B - Integrated circuit structure and method for forming the same - Google Patents

Abstract

An integrated circuit structure includes a substrate, a conductive layer, a plurality of memory devices, and a source line. The conductive layer is over the substrate. The memory devices are stacked in a vertical direction over the conductive layer. The bonding pad is over the conductive layer. The source line extends upwardly from the bonding pad and has a lower portion inlaid in the bonding pad and an upper portion having a sidewall coterminous with a sidewall of the bonding pad. A top end of the source line has a first lateral dimension greater than a second lateral dimension of the bonding pad.

Description

Integrated Circuit Structure and Formation Method

The present disclosure relates to an integrated circuit structure, and more particularly, to a method of forming an integrated circuit structure.

The present disclosure relates generally to semiconductor devices, and more particularly to 3-dimensional (3D) memory devices and methods of forming such semiconductor devices.

The semiconductor industry has experienced rapid growth due to the increasing bulk density of various electronic components such as transistors, diodes, resistors, capacitors, etc. In most cases, improvements in bulk density come from repeated reductions in minimum feature size, which allow more components to fit into a given area.

The present disclosure provides an integrated circuit structure. The integrated circuit structure includes a substrate, a conductive layer, a plurality of memory elements, bonding pads and source lines. A conductive layer is over the substrate. A plurality of memory elements are stacked on the conductive layer in a vertical direction. Bond pads are over the conductive layer. Source Line Self Bonding Pad It extends upward and has a lower part and an upper part. The lower part is embedded in the bonding pad, and the upper part has a side wall connected to the side wall of the bonding pad. The top of the source line has a first lateral dimension. The first lateral dimension is greater than a second lateral dimension of one of the bond pads.

In some embodiments, the first lateral dimension of the top of the source line is at least 1.5 times larger than a third lateral dimension of the source line at a position equal to a top of the bonding pad.

In some embodiments, the integrated circuit structure further includes: a dielectric material laterally surrounding the source line and the bonding pad. The first lateral dimension of the top of the source line is greater than a third lateral dimension of the dielectric material on the bonding pad.

In some embodiments, the memory elements each include a gate layer. The gate layer of the memory element extends laterally above the conductive layer, and the upper part of the source line overlaps the gate layer of the memory element.

In some embodiments, the integrated circuit structure further includes: a plurality of insulating layers alternately stacked with the memory device in the vertical direction. The upper portion of the source line overlaps the insulating layer.

The present disclosure provides a method of forming an integrated circuit structure. The method for forming an integrated circuit structure includes: forming a multilayer stack structure comprising a plurality of insulating layers alternately stacked in a vertical direction and a plurality of sacrificial layers on a substrate; forming a first via in the multilayer stack structure hole; forming a memory layer, a channel layer, and a first dielectric material in a first through hole; forming a second through hole in a multilayer stack structure; forming a memory array in a multilayer stack structure; depositing a second dielectric material on the memory above the body array and in the second via; forming The source line is in the second through hole.

In some embodiments, the method of forming an integrated circuit structure further includes: forming a bonding pad in the second via hole, wherein the second dielectric material laterally surrounds the source line and the bonding pad, the source line A first lateral dimension of a tip is greater than a second lateral dimension of the second dielectric material on the bond pad.

In some embodiments, forming the second dielectric material further includes: performing a dry etching process on the second dielectric material to remove an overhang portion above the second via hole in the second dielectric material. The aforementioned dry etching process includes introducing carbon monofluoride (C _x F _y ) gas over the second dielectric material, wherein x and y are integers, and y/x is less than 3.

In some embodiments, the fluorinated carbon gas comprises C ₄ F ₆ , C ₄ F ₈ , C ₅ F ₈ , C ₃ F ₈ , or any combination thereof.

In some embodiments, the top of the second through hole has a first lateral dimension. The first lateral dimension is at least 1.5 times larger than a second lateral dimension of the middle portion of the second through hole.

100: Integrated circuit structure

101: Semiconductor substrate

102: isolation layer

103: Conductive layer

103t: top surface

104: isolation layer

104t: top surface

105: Contact plug

105t: top surface

107: memory layer

108: Channel layer

109: Dielectric material

110: Multi-layer stack structure

110t: top surface

111-115: sacrificial layer

120: gate layer

121-126: insulation layer

127: memory unit

131: Bonding Pad

133: Dielectric material

133a: Upper surface

133b: lower inclined surface

135: Bonding Pad

135s: side wall

135t: top

137: metal plug

137m: lower part

137t: top

137u: upper part

137w: Bottom

137a: upper concave side wall

137b: lower concave side wall

139: interlayer dielectric layer

141: interconnection conductive column

143: bit line

200: Integrated circuit structure

233: Dielectric material

233a: Bevel

237: metal plug

237t: top

237w: Bottom

237a: Upper sloped side wall

237b: lower concave side wall

300: Integrated circuit structure

333: Dielectric material

333a: upper bevel

333b: lower bevel

333c: middle surface

337: metal plug

337t: top

337w: Bottom

337a: upper side wall

337b: lower side wall

337c: middle surface

C1: sharp corner

D1: horizontal dimension

D2: Horizontal dimension

O1: contact opening

O2: through hole

O21: upper part O3: through hole

O31: upper part

O32: lower part

P1: Etching process

P2: Planarization process

P3: Etch back process

P4: Etching process

P5: Etch back process

P6: Dry etching process

P7: Planarization process

P8: Dry etching process

P9: Dry etching process

R: Groove

R1: Fillet

R2: sharp corner

R3: sharp corner

R4: sharp corner

S1: space

W1: width

W2: width

W3: width

Wb: width

Wm: width

Wt: width

X: direction

Y: Direction

Z: Direction

Aspects of the present disclosure are best understood from the following Detailed Description when read with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

1 to 13, 14A, 15A, and 16 illustrate integrated circuit structures at various stages according to some embodiments of the present disclosure. A cross-sectional view of the formation method.

FIG. 14B and FIG. 15B illustrate cross-sectional views at various stages of a method of forming an integrated circuit structure according to some embodiments of the present disclosure.

FIG. 14C and FIG. 15C illustrate cross-sectional views at various stages of a method of forming an integrated circuit structure according to some embodiments of the present disclosure.

The following disclosure provides many different implementations, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, the formation of a first feature on or over a second feature in the following description may include embodiments where the first feature is formed in direct contact with the second feature, and may also include that additional features may be formed on the first feature and the second feature. An embodiment in which the first feature and the second feature may not be in direct contact between the second features. Additionally, the present disclosure may repeat reference numbers and/or letters in various instances. This repetition is for simplicity and clarity and by itself does not indicate a relationship between the various implementations and/or configurations discussed.

In addition, for ease of description, spatially relative terms may be used herein, such as "below", "beneath", "lower", "at ... .over", "upper" and the like, to describe the relationship between one element or feature and another (multiple) element or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be be interpreted similarly.

As used herein, "about," "approximately," "approximately," or "substantially" shall generally mean within 20%, or within 10%, or within 5% of a given value or range. However, those skilled in the art will recognize that values or ranges cited throughout the description are examples only and may decrease as the scale of integrated circuits decreases. Quantities given herein are approximate, meaning that the terms "approximately," "about," "approximately," or "substantially" can be inferred where not expressly stated.

For the development of semiconductor devices, memory devices with high storage density are a development direction. Therefore, a 3-dimensional (3D) integrated circuit (IC) memory device, such as a 3-dimensional NAND, can provide high storage density through its multi-layer structure. However, the more layers are stacked in the 3D NAND, the more difficult it is to form the source lines in the 3D NAND, which may result in the formation of gaps in the source lines. After the planarization process is performed on the source line, etching gas (eg, fluorine) will be trapped/stuck in the gap and affect subsequent processes (eg, fluorine leakage).

Accordingly, in various embodiments, the present disclosure provides a top widen etching process that avoids the formation of seams in the source lines. Specifically, the top widening etch process is to modify the source line trench by introducing a polymer etching gas on the dielectric material under low pressure to perform the top widen etch process, and then modify the source line trench will form the source line. The top widening etch process increases the ability of the plasma to strike the dielectric material vertically down to enlarge the upper portion of the source line trench while removing only minimal dielectric in the source line trench. lower part of the material. Therefore, the difference between the upper portion and the lower portion of the source line trench can be increased to improve the gap fill window tolerance of the subsequent deposition process performed to form the source line and avoid the source line. A gap is formed in the line.

1 to 13, 14A, 15A, and 16 are cross-sectional views of various stages of a method of forming an integrated circuit structure 100 according to some embodiments of the present disclosure. Referring to FIG. 1 , in some embodiments, the isolation layer 102 , the conductive layer 103 and the isolation layer 104 are sequentially formed on the semiconductor substrate 101 . In some embodiments, the conductive layer 103 can be used as a common source line of the memory device. Next, a plurality of contact openings O1 are formed to pass through the isolation layer 102 , the conductive layer 103 and the isolation layer 104 to expose a plurality of positions of the semiconductor substrate 101 . Next, a plurality of contact plugs 105 are respectively formed in the plurality of contact openings O1 to electrically connect to the semiconductor substrate 101 through the conductive layer 103 .

In some embodiments, the method for forming the contact plug 105 includes performing an etching process to remove part of the isolation layer 102 , the conductive layer 103 and the isolation layer 104 , thereby forming a plurality of contact openings O1 . Next, a conductive material, such as polysilicon, is formed on the isolation layer 104 through a deposition process, such as a low pressure chemical vapor deposition (LPCVD) process, to fill the plurality of contact openings O1. Next, a planarization process, such as chemical mechanical polish (CMP) process is performed using the isolation layer 104 as a stop layer to remove the conductive material above the isolation layer 104 to form the contact plug 105 . Therefore, each contact plug 105 It has a top surface 105t, the top surface 105t is substantially higher than the top surface 103t of the conductive layer 103, and is substantially flush with the top surface 104t of the isolation layer 104.

In some embodiments, the material of the semiconductor substrate 101 may include p-type doped or n-type doped semiconductor material or undoped semiconductor material, such as polysilicon, germanium or any other suitable semiconductor material. In some embodiments, the material of the isolation layers 102 and 104 may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicate, any combination of the foregoing materials, or any suitable dielectric material. In some embodiments, the material of the contact plug 105 may include TiN, TaN, Ti, Ta, Cu, Al, Ag, W, Ir, Ru, Pt, any combination of the foregoing materials, or other suitable conductive materials.

Referring to FIG. 2 , a multi-layer stack structure 110 comprising alternately stacked insulating layers 121 - 126 and sacrificial layers 111 - 115 is formed on a semiconductor substrate 101 . The insulating layers 121 - 126 and the sacrificial layers 111 - 115 are arranged parallel to each other and alternately stacked along the direction Z. The insulating layer 121 and the insulating layer 126 serve as the bottommost layer and the topmost layer of the multilayer stack structure 110 respectively. In some embodiments, the multi-layer stack structure 110 may also be called a film-like stack structure.

In some embodiments, the material of the sacrificial layers 111 - 115 may include silicon nitride compounds, such as silicon nitride, silicon oxynitride, silicon carbide nitride, or any combination of the aforementioned materials. In some embodiments, the top sacrificial layer 115 may also be called a dummy source line silicon nitride layer, and the sacrificial layers 111 - 114 may also be called a dummy word line silicon nitride layer. in some implementations Among them, the material of the insulating layers 121-126 may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicate, or any combination of the aforementioned materials. In some embodiments, the top insulating layer 126 may also be referred to as a hard mask oxide layer. However, it should be noted that, in the embodiments of the present disclosure, the material of the sacrificial layers 111-115 is different from that of the insulating layers 121-126. For example, the material of the sacrificial layers 111-115 can be silicon nitride, and the material of the insulating layers 121-126 can be silicon oxide. In some embodiments, the sacrificial layers 111-115 and the insulating layers 121-126 can be formed by low pressure chemical vapor deposition (LPCVD).

Referring to FIG. 3 , an etching process P1 , such as a hole etch process, is performed to form a plurality of via holes O2 through the multilayer stack structure 110 to expose the contact plugs 105 . In some embodiments, the etching process P1 may be an anisotropic etching process, such as a reactive ion etching (RIE) process. The etching process P1 is performed on the multilayer stack structure 110 by using a patterned hard mask layer (not shown) as an etching mask. The via hole O2 may be a circular hole-shaped via hole extending along the direction Z through the multilayer stack structure 110 , and extending to the top surface 105 t of the contact plug 105 . The exposed portions of the sacrificial layers 111-115 and the insulating layers 121-126 can be used as sidewalls of the via hole O2.

Please refer to FIG. 4, the memory layer 107 and the channel layer 108 are sequentially formed on the sidewall of the through hole O2. Therefore, the memory layer 107 is disposed between the channel layer 108 and the sacrificial layers 111-115. In some embodiments, the memory layer 107 may include composite layers. The aforementioned composite layer has but is not limited to oxidation Material layer-nitride layer-oxide layer (oxide-nitride-oxide; ONO) structure, oxide layer-nitride layer-oxide layer-nitride layer-oxide layer (oxide-nitride-oxide; ONONO) structure Or oxide layer-nitride layer-oxide layer-nitride layer-oxide layer-nitride layer-oxide layer (oxide-nitride-oxide; ONONONO) structure, and conformally formed to cover the multilayer stack structure 110, the sidewall and the bottom of the through hole O2. Next, an etching process is performed to remove the above composite layer on the top surface 110t of the multilayer stack structure 110 and the bottom of the via hole O2, so that the top surface 105t of the contact plug 105 is exposed.

Next, a channel layer 108 is conformally deposited over the memory layer 107 so that the integrated circuit structure 100 can include vertical channel flash memory devices. The channel layer 108 is in electrical contact with the top surface 105t of the contact plug 105 . In some embodiments, the channel layer 108 may include semiconductor materials, such as polysilicon, germanium or other doped or undoped semiconductor materials. For example, the material of the channel layer 108 may include undoped polysilicon.

Referring to FIG. 5, a dielectric material 109 is deposited over the channel layer 108 and filled in the via hole O2. In some implementations, the material of the dielectric material 109 may include silicon oxide. In some embodiments, the dielectric material 109 can be made of the same material as the insulating layers 121-126. In some embodiments, the dielectric material 109 may be made of a material different from the insulating layers 121-126.

Please refer to FIG. 6, the planarization process P2 (for example: chemical mechanical polishing (CMP) process) is is performed to remove excess dielectric material 109 and channel layer 108 above the top surface 110t of the multilayer stack structure 110 . After this step, the channel layer 108 surrounds the dielectric material 109 in the via O2. The memory layer 107 surrounds the channel layer 108 located in the through hole O2.

Referring to FIG. 7 , an etching back process P3 is performed on the dielectric material 109 , the channel layer 108 and the memory layer 107 to reproduce the upper portion O21 of the through hole O2 . In some embodiments, the etch-back process P3 may be a wet etching process, for example, immersing the semiconductor substrate 101 in hydrofluoric acid (HF). In some implementations, the etch-back process P3 may be a dry etching process. For example, the dry etching process may be performed using hydrofluoric acid/ammonia (HF/NH ₃ ) or nitrogen trifluoride/ammonia (NF ₃ /NH ₃ ) as the etching gas.

Referring to FIG. 8 , the bonding pad 131 is formed in the upper portion O21 of the via hole O2 and located on the dielectric material 109 to form electrical contact with the channel layer 108 . In some embodiments, the bonding pads 131 are formed by depositing polysilicon, germanium or doped semiconductor material over the multilayer stack structure 110 . In general, n-type dopants (N ⁺ ), such as phosphorus or arsenic, can be used for the aforementioned doped semiconductor materials. Next, a planarization process may be performed to remove excess semiconductor material above the top surface 110 t of the multilayer stack structure 110 . After this step is performed, the bonding pads 131 can be formed as shown in FIG. 8 . In some embodiments, the bonding pad 131 may be a p-type doped (P ⁺ ) polysilicon bonding pad.

Please refer to FIG. 9, the etching process P4 is performed to form a multilayer stack structure 110 along the direction Z and terminate at the top of the conductive layer 103 The through hole O3 on the surface 103t, whereby the through hole O3 can partially expose the sacrificial layers 111-115 and the insulating layers 121-126. In some embodiments, the etching process P4 may be an anisotropic etching process, such as a reactive ion etching (RIE) process. The etching process P4 is performed on the multilayer stack structure 110 using a patterned hard mask layer (not shown) as an etching mask. As shown in FIG. 9, when the etching process P4 is completed, the via hole O3 may be formed to have a bowl-shaped cross-sectional profile. Specifically, in a cross-sectional view, the width of the through hole O3 can gradually increase from the lower part of the through hole O3 to the middle part of the through hole O3, and gradually decrease from the middle part of the through hole O3 to the upper part of the through hole O3. . In some embodiments, the via O3 may have a maximum width at the same level as one of the sacrificial layers 111 - 115 and the insulating layers 122 - 125 in the multilayer stack 110 . In some embodiments, the through hole O3 may have a maximum width Wm at a middle position of the through hole O3, and the maximum width Wm is greater than the width Wb and the width Wt of the bottom and top ends of the through hole O3. In some embodiments, the maximum width Wm of the via hole O3 is located at the same level as the top surface of the tallest one of the sacrificial layers 111 - 115 . In some embodiments, the through hole O3 may also be called a source line trench (SLT). In some embodiments, width may also be referred to as a lateral dimension.

Please refer to FIG. 10 , the sacrificial layers 111 - 115 are made of phosphoric acid (phosphoric acid; H ₃ PO ₄ ), and removed through the through hole O3 to expose part of the memory layer 107 . Therefore, the space S1 is formed to inherit the shape of the sacrificial layers 111-115.

Please refer to FIG. 11 , a plurality of gate layers 120 are formed in the space S1 through the via hole O3. Therefore, a plurality of memory cells 127 can be defined at the intersection of the gate layer 120 , the memory layer 107 and the channel layer 108 to form a memory cell array in the multilayer stack structure 110 . In some embodiments, the memory unit 127 can also be called a memory element. In some embodiments, the material of the gate layer 120 may include polysilicon, metal or other suitable conductive materials. In some embodiments, the gate layer 120 may include multiple metal layers, such as TiN/W, TaN/W, TaN/Cu or other suitable metal layers. In some embodiments, the gate layer 120 may include a dielectric layer, such as AlO _x . For example, each gate layer 120 may be a multi-layer structure including a high dielectric constant material layer (for example: HfO _x layer or AlO _x layer), a TiN layer and a tungsten layer. In some embodiments, a lateral end of at least one of the plurality of gate layers 120 may be recessed toward the memory layer 107 .

Referring to FIG. 12, a dielectric material 133 is deposited over the multilayer stack structure 110 and filled in the via O3 to line the sidewall of the via O3. In some embodiments, the material of the dielectric material 133 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicate, any combination of the foregoing materials, or any suitable dielectric material. In some embodiments, the material of the dielectric material 133 may be the same as that of the insulating layers 121-126. In some embodiments, the material of the dielectric material 133 may be different from the material of the insulating layers 121-126. Next, an etching process is performed to remove the portion of the dielectric material 133 located on the top surface 103t of the conductive layer 103 so that the conductive layer 103 is exposed.

Please refer to FIG. 13 , the bonding pad 135 is formed in the through hole O3 to form electrical contact with the conductive layer 103 . In some embodiments, the bonding pads 135 are formed by depositing polysilicon, germanium or doped semiconductor material over the multilayer stack structure 110 . In general, n-type dopants (N ⁺ ), such as phosphorus or arsenic, can be used for the aforementioned doped semiconductor materials. Next, a planarization process may be performed to remove excess semiconductor material above the top surface 110 t of the multilayer stack structure 110 . Next, an annealing process is performed on the bonding pads 135 . Next, an etching back process P5 is performed on the bonding pad 135 to reproduce the upper portion O31 of the through hole O3. In some embodiments, the etch-back process P5 may be a wet etching process, for example, immersing the semiconductor substrate 101 in hydrofluoric acid (HF). In some embodiments, the etch-back process P5 may be a dry etching process. For example, the dry etching process may be performed using hydrofluoric acid/ammonia (HF/NH ₃ ) or nitrogen trifluoride/ammonia (NF ₃ /NH ₃ ) as the etching gas. After this step is performed, bond pads 135 may be formed as shown in FIG. 13 . In some embodiments, the bonding pad 135 may be a p-type doped (P ⁺ ) polysilicon bonding pad. In some embodiments, due to the nature of the deposition, the bond pad 135 has a groove R on its top surface.

Please refer to FIG. 14A, perform a dry etching process P6 on the dielectric material 133 to remove the sharp corner C1 (see FIG. 13 ) close to the through hole O3 on the dielectric material 133, so that the lateral dimension of the upper part O31 of the through hole O3 D1 may be enlarged to improve the gap-fill process tolerance of one or more subsequent deposition processes (eg, the process used to form metal plug 137 in via O3 as shown in FIG. 15A ), And avoid forming a seam in the metal plug 137 . In some embodiments, the dry etching process P6 may also be called a top widening etching process. In some embodiments, the pointed Corner C1 may also be referred to as an overhang.

If the lateral dimension D1 of the upper portion O31 of the via O3 is smaller than the lateral dimension D2 of the via O3 at a position flush with the topmost end of the bonding pad 135 (for example: a via hole with a bowl-shaped profile), the clearance of the via O3 The fill process tolerance may be too small for the subsequent deposition process to properly proceed in the via with the bowl-shaped profile, so that a gap is formed in the metal plug in the via O3. After the planarization process on the metal plug, etching gas (eg, fluorine) will be trapped/stuck in the gap and affect subsequent processes (eg, fluorine leakage).

Therefore, the present disclosure provides a method for avoiding the formation of a gap in the metal plug in the via O3. Specifically, the dry etching process P6 is performed by introducing a polymer etching gas into the processing chamber having the semiconductor substrate 101 therein. After the polymer chemical is introduced into the processing chamber, a plasma is triggered to form. The dry etching process P6 causes ions in the plasma to move up and down relative to the surface of the semiconductor substrate 101 .

In some embodiments, the wafer support structure below the semiconductor substrate 101 may serve as a plate of the capacitive coupling structure, while the conductive plasma above the semiconductor substrate 101 provides a complementary electrode. The radio frequency (radio frequency; RF) bias power of the dry etching process P6 is electrically connected to the wafer support to generate an electric field perpendicular to the surface of the semiconductor substrate 101. The aforementioned electric field can accelerate plasma ions entering and leaving the semiconductor substrate. The surface of material 101. Ion sputtering etches the surface of the semiconductor substrate 101 by physically bombarding the surface, thereby removing the sharp corner C1 of the dielectric material 133 (see FIG. 13 ).

In some embodiments, the dry etching process P6 can be a plasma etching process, and uses a polymer gas (eg: carbon fluoride (C _x F _y )), oxygen (O ₂ ) and argon (Ar) at a low pressure This increases the ability of the plasma to strike the dielectric material 133 vertically downward to enlarge the upper portion O31 of the via O3 while only minimally removing the lower portion of the dielectric material 133 in the via O3. Therefore, the difference between the upper portion O31 and the lower portion O32 of the via hole O3 can be increased to improve the gapfill process tolerance of the subsequent deposition process. By way of example and not limitation of the present disclosure, the lateral dimension D1 of the via O3 may be at least 1.5 times greater than the lateral dimension D2 of the via O3 , wherein the lateral dimension D2 is located flush with the topmost end of the bonding pad 135 .

In some embodiments, a highly polymeric gas (eg, carbon fluoride (C _x F _y ) gas, where x and y are integers, and y/x is less than 3) can provide more plasma species for splashing The upper layer of dielectric material 133 is shot etched. In some embodiments, the fluorinated carbon gas may comprise C ₄ F ₆ , C ₄ F ₈ , C ₅ F ₈ , C ₃ F ₈ , or any combination thereof. In some embodiments, the etching gas used in the dry etching process P6 may be different from the etching gas used in the etch-back process P5 (see FIG. 13 ) and/or the etching process P4 (see FIG. 9 ). During the etching process, the flow rate of the polymer gas flowing into the processing chamber in the dry etching process P6 can be in the range of about 20 to 50 sccm (for example: 20, 30, 40 or 50 sccm), and the flow rate of the argon gas flowing into the processing chamber can be from 20 to 50 sccm. In the range of about 200 to 500 seem (eg: 200, 250, 300, 350, 400, 450 or 500 seem).

In some embodiments, the pressure in the dry etching process P6 may be in the range of about 10 to 100 mT (for example: about 10, 20, 30, 40, 50, 60, 70, 80, 90 or 100mT). In some embodiments, dry etching process P6 may be performed at a lower pressure than etch-back process P5 (see FIG. 13 ) and/or etching process P4 (see FIG. 9 ). In some embodiments, the duration of the dry etching process P6 may be greater than about 15 seconds. During the execution of the dry etching process P6, the plasma can be formed by turning on the top RF source generator and the RF bias voltage generator, wherein the frequency of the top RF source generator is in the range of about 1 to 3 MHz (for example: 1, 1.5, 2, 2.5 or 3MHz), while the power is in the range of about 800 to 1200 (for example, 800, 900, 1000, 1100 or 1200W), and the frequency of the RF bias generator is in the range of about 25 to 35MHz (for example: 25, 27 , 30 or 35MHz), and the power is in the range of about 3000 to 4000 (for example, 3000, 3500 or 4000W). In some embodiments, the increase of the RF bias power of the RF bias generator can increase the width difference between the upper part O31 and the lower part O32 of the through hole O3, so that the gap filling process tolerance of the subsequent deposition process can be improved. improve.

Accordingly, the dry etching process P6 can suppress the formation of overhangs on the dielectric material 133 compared to the case where the dry etching process P6 is not performed, thereby improving the gap-fill process tolerance of one or more subsequent deposition processes ( For example: the process of forming the metal plug 137 as shown in FIG. 15A). The sputter etching in the dry etching process P6 may result in the formation of a fillet R1 on the dielectric material 133 , and the fillet R1 includes an upper curved surface 133 a and a lower inclined surface 133 b having a steeper slope than the curved surface 133 a. The upper curved surface 133a and the lower inclined surface 133b are formed such that the remaining portion of the upper portion O31 of the through hole O3 in the dielectric material 133 moves away from the joint as it extends Pad 135 is widened, thereby improving gapfill process tolerance for one or more subsequent deposition processes. In some embodiments, the remaining portion of the upper portion O31 of the through hole O3 in the dielectric material 133 as shown in FIG. 14A may also be called a wine glass-shaped profile. In some embodiments, the present disclosure can also be applied to dynamic random access memory (dynamic random access memory; DARM), NOR flash memory (NOR flash memory) or NAND flash memory (NAND flash memory) Other dielectric materials or conductance etch.

Referring to FIG. 15A, the metal plug 137 is formed on the upper portion O31 of the through hole O3. Specifically, a conductive material is deposited on the multi-layer stack structure 110 and filled in the through hole O3. Next, a planarization process P7 (such as a chemical mechanical polishing (CMP) process) is performed to remove excess conductive material above the top surface 110 t of the multilayer stack structure 110 . After this step is performed, a metal plug 137 is formed in the via O3. The metal plug 137 can be electrically insulated from the gate layer 120 through the dielectric material 133 and electrically connected to the conductive layer 103 through the bonding pad 135 . In some embodiments, the metal plug 137 may also be called a source line. In some embodiments, the material of the metal plug 137 may include TiN, TaN, Ti, Ta, Cu, Al, Ag, W, Ir, Ru, Pt, any combination of the foregoing materials, or other suitable conductive materials.

The metal plug 137 extends upward from the bonding pad 135 and has a lower portion 137m and an upper portion 137u. The lower portion 137 m of the metal plug 137 is embedded in the bonding pad 135 . In some embodiments, the upper portion 137u of the metal plug 137 may have an upper concave sidewall 137a, and the metal plug 137 The lower portion 137m of the can have a lower concave side wall 137b. The upper concave sidewall 137a of the upper portion 137u of the metal plug 137 can be connected to the sidewall 135s of the bonding pad 135 . The metal plug 137 may have a width that increases from its bottom end 137w to its top end 137t. The width W1 of the top end 137 t of the metal plug 137 is greater than the width of the bonding pad 135 . In some embodiments, the width W1 of the top end 137 t of the metal plug 137 may be at least 1.5 times greater than the width W2 of the metal plug 137 flush with the top end 135 t of the bonding pad 135 . In some embodiments, the top 137t or the upper portion 137u of the metal plug 137 can overlap the gate layer 120 . In some embodiments, the lateral dimension of the top end 137t of the metal plug 137 may be larger than the maximum lateral dimension of the through hole O3. In some embodiments, there is no gap in the metal plug 137 . Dielectric material 133 laterally surrounds metal plug 137 and bond pad 135 . In some embodiments, the width W1 of the top end 137 t of the metal plug 137 may be greater than the width W3 of the dielectric material 133 on the bonding pad 135 . In some embodiments, the upper portion 137u of the metal plug 137 may overlap the insulating layers 122-125.

Please refer to FIG. 16 , an inter-layer dielectric (inter-layer dielectric; ILD) layer 139 is formed above the dielectric material 133 and the metal plug 137 . Next, a plurality of bit lines 143 are electrically connected to the bonding pads 131 through interconnecting conductive pillars 141 formed in the interlayer dielectric layer 139 . Next, after performing a series of back end of line (BEOL) processes (not shown), the base circuit structure 100 including a plurality of memory cells 127 is formed as shown in FIG. 16 . In some embodiments, the memory cell defined by the gate layer 120, the memory layer 107, and the channel layer 108 The cell 127 can be electrically coupled to a decoder (not shown), such as a row decoder or a column decoder, through the bit line 143 . The current from the bit line 143 can flow through the channel layer 108 , the contact plug 105 , the conductive layer 103 (as the bottom common source line), the bonding pad 131 and the metal plug 134 to the ground line. In other words, the current path for performing read/program operations does not flow through the semiconductor substrate 101 . Therefore, a current path for performing read/write operations can be shortened, and thus the operation resistance and power consumption of the memory element can be reduced.

In some embodiments, the material of the interlayer dielectric layer 139 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicate, any combination of the foregoing materials, or any suitable dielectric material. In some embodiments, the material of the bit line 143 may include TiN, TaN, Ti, Ta, Cu, Al, Ag, W, Ir, Ru, Pt, any combination of the foregoing materials, or other suitable conductive materials. In some embodiments, the material of the interconnection conductive pillar 141 may include TiN, TaN, Ti, Ta, Cu, Al, Ag, W, Ir, Ru, Pt, any combination of the foregoing materials, or other suitable conductive materials.

FIG. 14B and FIG. 15B illustrate cross-sectional views of the formation method of the integrated circuit structure 200 at various stages according to some embodiments of the present disclosure. The process of forming the integrated circuit structure 200 is basically the same as the aforementioned process of forming the integrated circuit structure 100 , and will not be repeated here for clarity. The profile of the metal plug 237 in FIG. 14B and FIG. 15B is different from the profile of the metal plug 137 in FIGS. 1-13, 14A, 15A, and 16.

FIG. 14B illustrates an integrated circuit structure 200 corresponding to the steps of FIG. 14A according to some embodiments of the present disclosure. As shown in FIG. 14B , the dry etching process P8 can be a plasma etching process, which uses polymer gas and is performed under low pressure, which increases the ability of the plasma to strike the dielectric material 233 vertically downward. The etching gas may include high polymer gas, such as C ₄ F ₆ , C ₄ F ₈ , C ₅ F ₈ , C ₃ F ₈ or combinations thereof. Compared to the case where dry etching process P8 is not performed, dry etching process P8 can inhibit the formation of overhangs on dielectric material 233, thereby improving the gap-fill process tolerance of one or more subsequent deposition processes (eg: The process of forming the metal plug 237 as shown in FIG. 15B). The sputter etching in the dry etching process P8 may result in the formation of a sharp corner R2 on the dielectric material 233, and the sharp corner R2 includes a slope 233a. The formation of the slope 233 a widens the remaining portion of the upper portion O31 of the via O3 in the dielectric material 233 as it extends away from the bond pad 135 , thereby improving gapfill process tolerance for one or more subsequent deposition processes. In some embodiments, the remaining portion of the upper portion O31 of the through hole O3 in the dielectric material 233 as shown in FIG. 14B may also be referred to as an angular profile.

FIG. 15B illustrates an integrated circuit structure 200 corresponding to the steps of FIG. 14B according to some embodiments of the present disclosure. As shown in FIG. 15B, the metal plug 237 may have an upper sloped sidewall 237a and a lower concave sidewall 237b. Metal plug 237 may have a width that increases from its bottom end 237w to its top end 237t. Specifically, the width of the top end 237 t of the metal plug 237 may be at least 1.5 times larger than the width of the metal plug 237 at the level with the top end 135 t of the bonding pad 135 . In some embodiments, the lateral dimension of the top end 237t of the metal plug 237 may be at least larger than the maximum lateral dimension of the through hole O3. In some embodiments, there is no gap in the metal plug 237 .

FIG. 14C and FIG. 15C illustrate cross-sectional views of the method of forming the integrated circuit structure 300 at various stages according to some embodiments of the present disclosure. The process of forming the integrated circuit structure 300 is basically the same as the aforementioned process of forming the integrated circuit structure 100 , and will not be repeated here for clarity. The profile of the metal plug 337 in FIG. 14C and FIG. 15C is different from the profile of the metal plug 137 in FIGS. 1-13, 14A, 15A, and 16.

FIG. 14C illustrates an integrated circuit structure 300 corresponding to the steps of FIG. 14A according to some embodiments of the present disclosure. As shown in FIG. 14C , the dry etching process P9 can be a plasma etching process, which uses a polymer gas and is performed at a low pressure, which increases the ability of the plasma to strike the dielectric material 333 vertically downward. The etching gas may include high polymer gas, such as C ₄ F ₆ , C ₄ F ₈ , C ₅ F ₈ , C ₃ F ₈ or combinations thereof. Compared to the case where dry etching process P9 is not performed, dry etching process P9 can suppress the formation of overhangs on dielectric material 333, thereby improving the gap-fill process tolerance of one or more subsequent deposition processes (eg: The process of forming the metal plug 337 as shown in FIG. 15C).

The sputter etching in the dry etching process P9 can result in the formation of sharp corners R3 , R4 on the dielectric material 333 , and the sharp corners R3 , R4 include an upper slope 333 a , a lower slope 333 b and a middle surface 333 c . The upper ramp 333a is set back laterally from the top of the lower ramp 333b, and an intermediate surface 337c connects the top of the lower ramp 333b to the bottom of the upper ramp 333a. The formation of the upper slope 333a and the lower slope 333b makes the remaining portion of the upper portion O31 of the via O3 in the dielectric material 333 widen as it extends away from the bonding pad 135, thereby improving the interval between one or more subsequent deposition processes. Gap fill process tolerance. In some embodiments, the remaining portion of the upper portion O31 of the through hole O3 in the dielectric material 333 as shown in FIG. 14C may also be referred to as a stepped profile.

FIG. 15C illustrates an integrated circuit structure 300 corresponding to the steps of FIG. 14C according to some embodiments of the present disclosure. As shown in FIG. 15C, the metal plug 337 includes an upper sidewall 337a, a lower sidewall 337b set back laterally from the bottom of the upper sidewall 337a, and an intermediate surface 337c connecting the bottom of the upper sidewall 337a to the top of the lower sidewall 337b. Metal plug 337 may have a width that increases from its bottom end 337w to its top end 337t. Specifically, the width of the top 337 t of the metal plug 337 may be at least 1.5 times larger than the width of the metal plug 337 at the level with the top 135 t of the bonding pad 135 . In some embodiments, the lateral dimension of the top end 337t of the metal plug 337 may be at least larger than the maximum lateral dimension of the through hole O3. In some embodiments, there is no gap in the metal plug 337 .

For the development of semiconductor devices, memory devices with high storage density are a development direction. Therefore, a 3-dimensional (3D) integrated circuit (IC) memory device, such as a 3-dimensional NAND, can provide high storage density through its multi-layer structure. However, the more layers are stacked in the 3D NAND, the more difficult it is to form the source lines in the 3D NAND, which may result in the formation of gaps in the source lines. After the planarization process is performed on the source line, etching gas (eg, fluorine) will be trapped/stuck in the gap and affect subsequent processes (eg, fluorine leakage).

Therefore, based on the above discussion, it can be seen that the present disclosure has advantages. It should be understood, however, that other embodiments may provide additional advantages, and not all All advantages must be revealed in this article. Furthermore, no particular advantage needs to be used in all embodiments. Various embodiments of the present disclosure provide a top widening etch process that avoids the formation of seams in the source lines. Specifically, the top widening etch process is to modify the source line trench by introducing a polymer etching gas on the dielectric material under low pressure to perform the top widen etch process, and then modify the source line trench will form the source line. The top widening etch process increases the ability of the plasma to strike the dielectric material vertically downward to enlarge the upper portion of the source line trenches while only minimally removing the lower portion of the dielectric material in the source line trenches. parts. Therefore, the difference between the upper portion and the lower portion of the source line trench can be increased to improve the gap fill window tolerance of the subsequent deposition process performed to form the source line and avoid the source line. A gap is formed in the line.

The foregoing summary summarizes features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and substitutions can be made herein without departing from the spirit and scope of the present disclosure. and categories.

100: Integrated circuit structure

101: Semiconductor substrate

102: isolation layer

103: Conductive layer

103t: top surface

104: isolation layer

105: Contact plug

107: memory layer

108: Channel layer

109: Dielectric material

110: Multi-layer stack structure

110t: top surface

120: gate layer

121-126: insulation layer

127: memory unit

131: Bonding Pad

133: Dielectric material

133a: Upper surface

133b: lower inclined surface

135: Bonding Pad

D1: horizontal dimension

D2: Horizontal dimension

O1: contact opening

O3: through hole

O31: upper part

O32: lower part

P6: Dry etching process

R1: Fillet

S1: space

Z: Direction

X: direction

Claims (10)

An integrated circuit structure, comprising: a substrate; a conductive layer located above the substrate; a plurality of memory elements stacked above the conductive layer in a vertical direction, and including a plurality of gate layers, the The gate layer extends laterally above the conductive layer; a plurality of insulating layers are alternately stacked with the gate layers in the vertical direction to form a multilayer stack structure, and the multilayer stack structure has a through hole exposing the conductive layer. a hole; a bonding pad located in the via hole of the multilayer stack structure and contacting the conductive layer; and a source line located in an upper portion of the via hole of the multilayer stack structure and upward from the bonding pad Extending and having a lower portion and an upper portion, the lower portion of the source line is embedded in the bonding pad, the upper portion of the source line has a side wall connected to the side wall of the bonding pad, wherein the source line A top end has a first lateral dimension that is greater than a second lateral dimension of the bonding pad. The integrated circuit structure as claimed in claim 1, wherein the first lateral dimension of the top end of the source line is at least larger than a third lateral dimension of the source line at a position equal to a top end of the bonding pad 1.5 times the size. The integrated circuit structure as claimed in claim 1, further comprising: a dielectric material laterally surrounding the source line and the bonding pad, wherein the first lateral dimension of the top end of the source line is larger than that on the bonding pad A third lateral dimension of the dielectric material. The integrated circuit structure as claimed in claim 1, wherein the upper portion of the source line overlaps the gate layers of the memory devices. The integrated circuit structure as claimed in claim 1, wherein the upper portion of the source line overlaps the insulating layers. A method for forming an integrated circuit structure, comprising: forming a multilayer stack structure comprising a plurality of insulating layers and a plurality of sacrificial layers alternately stacked in a vertical direction on a substrate; forming in the multilayer stack structure A first through hole; forming a memory layer, a channel layer and a first dielectric material in the first through hole; forming a second through hole in the multilayer stack structure; forming a memory array; forming a second dielectric material above the memory array and in the second through hole; and forming a source line in the second through hole. The method for forming an integrated circuit structure as described in Claim 6, Further comprising: forming a bonding pad in the second via hole, wherein the second dielectric material laterally surrounds the source line and the bonding pad, and a top end of the source line has a first lateral dimension larger than that located at the bonding pad. A second lateral dimension of the second dielectric material on the pad. The method for forming an integrated circuit structure as described in Claim 6, wherein forming the second dielectric material further includes: performing a dry etching process on the second dielectric material to remove the second dielectric material located on the second dielectric material. An overhang above the two via holes, the dry etching process includes introducing carbon monofluoride (C _x F _y ) gas over the second dielectric material, wherein x and y are integers, and y/x is less than 3 . The method for forming an integrated circuit structure as claimed in claim 8, wherein the fluorinated carbon gas comprises C ₄ F ₆ , C ₄ F ₈ , C ₅ F ₈ , C ₃ F ₈ or any combination thereof. The method for forming an integrated circuit structure as claimed in item 6, wherein a top end of the second through hole has a first lateral dimension, and the first lateral dimension is at least larger than a first lateral dimension of a middle portion of the second through hole 1.5 times the horizontal dimension.

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