CN114284209A - Manufacturing method of semiconductor device, semiconductor device and memory - Google Patents
Manufacturing method of semiconductor device, semiconductor device and memory Download PDFInfo
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- CN114284209A CN114284209A CN202111650909.8A CN202111650909A CN114284209A CN 114284209 A CN114284209 A CN 114284209A CN 202111650909 A CN202111650909 A CN 202111650909A CN 114284209 A CN114284209 A CN 114284209A
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Abstract
The embodiment of the invention discloses a manufacturing method of a semiconductor device, the semiconductor device and a memory. The method comprises the following steps: providing a substrate and a plurality of metal wires positioned on the substrate, wherein the metal wires are distributed at intervals; forming a hollow dielectric layer between the plurality of metal lines; and forming an interlayer dielectric layer on the metal wire and the hollow dielectric layer, wherein the etching rates of the interlayer dielectric layer and the hollow dielectric layer are different. The embodiment of the invention can at least partially avoid the damage of the air gap between the metal wires, reduce the capacitance between the metal wires and improve the working efficiency of the semiconductor device.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device, the semiconductor device and a memory.
Background
In a semiconductor device, when a contact structure is formed on a metal line, a contact hole needs to be etched in a film layer above the metal line so as to form the contact structure connected with the metal line in the contact hole. However, the etching of the contact holes may be biased, that is, the contact holes may be partially etched to the metal lines, and another portion may be etched into the film layer between the metal lines, thereby damaging Air gaps (Air gaps) in the film layer between the metal lines and affecting the performance of the semiconductor device.
Disclosure of Invention
Embodiments of the present invention provide a manufacturing method of a semiconductor device, and a memory, which can at least partially prevent an air gap between metal lines from being damaged, so as to reduce capacitance between the metal lines and improve working efficiency of the semiconductor device.
The embodiment of the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a substrate and a plurality of metal wires positioned on the substrate, wherein the metal wires are distributed at intervals;
forming a hollow dielectric layer between the plurality of metal lines;
and forming an interlayer dielectric layer on the metal wire and the hollow dielectric layer, wherein the etching rates of the interlayer dielectric layer and the hollow dielectric layer are different.
Furthermore, the etching rate of the hollow dielectric layer is less than that of the interlayer dielectric layer.
Further, the step of providing a substrate and a plurality of metal lines on the substrate includes:
forming a metal layer on the substrate;
forming at least one opening in the metal layer such that the opening separates the metal layer into the plurality of metal lines.
Further, the step of forming a hollow dielectric layer between the plurality of metal lines includes:
forming a first hollow dielectric layer on one side of the substrate, wherein the first hollow dielectric layer covers at least part of the metal wire, and the first hollow dielectric layer fills the opening;
and grinding the first hollow medium layer to remove the first hollow medium layer on the metal wire, so that the first hollow medium layer remained in the opening forms the hollow medium layer.
Further, the method further comprises:
and forming a contact structure which penetrates through the interlayer dielectric layer and is connected with the metal wire.
Further, at least one air gap is formed in the hollow dielectric layer between two adjacent metal wires.
Accordingly, an embodiment of the present invention further provides a semiconductor device, including:
a substrate;
a plurality of metal lines on the substrate, the plurality of metal lines being spaced apart;
a hollow dielectric layer located between the plurality of metal lines; and the number of the first and second groups,
and the interlayer dielectric layer is positioned on the metal wire and the hollow dielectric layer, and the etching rates of the interlayer dielectric layer and the hollow dielectric layer are different.
Furthermore, the etching rate of the hollow dielectric layer is less than that of the interlayer dielectric layer.
Further, the semiconductor device further includes:
and the contact structure penetrates through the interlayer dielectric layer and is connected with the metal wire.
Further, at least one air gap is formed in the hollow dielectric layer between two adjacent metal wires.
Correspondingly, the embodiment of the invention also provides a memory, which comprises a memory array structure and a peripheral structure connected with the memory array structure;
at least one of the memory array structure and the peripheral structure includes the above semiconductor device.
The embodiment of the invention has the beneficial effects that: the method comprises the steps of firstly forming a hollow dielectric layer among a plurality of metal wires distributed at intervals, then forming an interlayer dielectric layer on the metal wires and the hollow dielectric layer, wherein the etching rates of the interlayer dielectric layer and the hollow dielectric layer are different, and when a contact hole is etched in the interlayer dielectric layer on the metal wires subsequently, even if the etching of the contact hole is deviated, the hollow dielectric layer can be used as a stop layer to prevent the contact hole from being etched into the hollow dielectric layer among the metal wires, so that the contact hole is at least partially prevented from damaging air gaps in the hollow dielectric layer among the metal wires, the capacitance among the metal wires is reduced, the working efficiency of a semiconductor device is improved, such as programming efficiency, and the programming performance of a memory is improved.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2a to fig. 2b are schematic structural diagrams corresponding to step 101 in a method for manufacturing a semiconductor device according to an embodiment of the invention;
fig. 2c to fig. 2d are schematic structural diagrams corresponding to step 102 in the method for manufacturing a semiconductor device according to the embodiment of the invention;
fig. 2e is a schematic structural diagram corresponding to step 103 in the method for manufacturing a semiconductor device according to the embodiment of the present invention;
fig. 2f is a schematic structural diagram corresponding to step 104 in the method for manufacturing a semiconductor device according to the embodiment of the present invention;
fig. 3 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a memory according to an embodiment of the present invention.
Detailed Description
Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the embodiments of the present invention, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the embodiments of the present invention and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present invention, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.
In the description of the embodiments of the present invention, it should be noted that, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. Specific meanings of the above terms in the embodiments of the present invention can be understood in specific cases by those of ordinary skill in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
As shown in fig. 1, the present embodiment provides a method for manufacturing a semiconductor device, where the method includes steps 101 to 103, and specifically includes the following steps:
In the embodiment of the invention, the semiconductor device can be applied to a memory, and the memory can comprise a memory array structure and a peripheral structure connected with the memory array structure. The substrate may be a substrate in a memory array structure or a substrate in a peripheral structure. It should be noted that the semiconductor device may also be applied to other structures, and the substrate may also be a substrate in other structures, which is not specifically limited herein.
When the base is a base in a memory array structure, the base may include a first substrate and a stack layer on the first substrate. The first substrate may be a semiconductor substrate, for example, a silicon substrate, or may be a substrate including another element semiconductor or a compound semiconductor. The stacked layers include a plurality of gate layers and interlayer insulating layers alternately stacked in a vertical direction, where the vertical direction refers to a direction perpendicular to the upper surface of the first substrate, and the number of stacked layers of the gate layers and the interlayer insulating layers is not limited, for example, 48 layers, 64 layers, 128 layers, and the like. The base may also include a memory channel structure extending longitudinally through the stacked layers and into the first substrate. The memory channel structure may include an isolation layer, a channel layer located on the periphery of the isolation layer, and a memory medium layer located on the periphery of the channel layer, which are not described in detail herein.
The metal lines may be metal interconnect lines of a back-end-of-line process in the memory array structure. Specifically, the metal line may be located on the stacked layer, and the metal line may be electrically connected to a channel layer of the memory channel structure in the stacked layer. For example, the metal line may be a bit line or the like.
When the base is a base in the peripheral structure, the base may include a second substrate and an insulating layer on the second substrate. The second substrate may be a semiconductor substrate, for example, a silicon substrate, or a substrate including another element semiconductor or a compound semiconductor, and the insulating layer may be silicon oxide, silicon nitride, or the like. The metal line may be a metal interconnection line of a back-end-of-line process in the peripheral structure. Specifically, the metal line may be on the insulating layer, and the metal line may be electrically connected to other metal lines on different layers.
The metal wires on the substrate can be multiple, and the multiple metal wires are located on the same layer and distributed at intervals. The plurality of metal lines may be formed by etching the metal layer. Specifically, the providing the substrate and the plurality of metal lines on the substrate in step 101 includes:
forming a metal layer on the substrate;
forming at least one opening in the metal layer such that the opening separates the metal layer into the plurality of metal lines.
As shown in fig. 2a, a metal layer 2 is formed on a substrate 1, and the metal layer 2 completely covers the upper surface of the substrate 1. The base 1 may include a substrate 11 and an insulating layer 12 on the substrate 11. Specifically, the metal layer 2 is deposited on the substrate 1 using a Deposition process, for example, using a Physical Vapor Deposition (PVD) process. It should be noted that, the metal layer 2 formed by the pvd process can reduce the resistance of the metal line formed subsequently by the metal layer 2. Preferably, the metal layer 2 may be metal tungsten or the like.
The metal layer may then be etched using the mask layer. Specifically, a mask layer is formed on the metal layer 2, and the mask layer may include a hard mask layer, an anti-reflection layer, and a photoresist layer sequentially on the metal layer 2. The hard mask layer may be amorphous carbon, and the anti-reflection layer may be silicon oxynitride SiON.
The photoresist layer has a hollow pattern, and the metal layer 2 is etched through the hollow pattern, that is, the metal layer 2 corresponding to the hollow pattern is removed, so as to form at least one opening 20 in the metal layer 2, as shown in fig. 2 b. The remaining metal layer 2 forms a plurality of metal lines 21 spaced apart, i.e. at least one opening 20 separates the metal layer 2 into a plurality of metal lines 21. It should be noted that the opening 20 may only penetrate through the metal layer 2, and the opening 20 may also penetrate through the metal layer 2 and extend into the insulating layer 12, so as to ensure that the plurality of metal lines 21 are completely separated by the opening 20. The metal line 21 may be metal tungsten or the like.
And 102, forming a hollow dielectric layer among the metal wires.
In the embodiment of the invention, the hollow medium layer refers to a medium layer with Air gaps (Air gaps). At least one air gap corresponds to any two adjacent metal lines, namely at least one air gap is formed in the hollow dielectric layer between any two adjacent metal lines. Capacitance effect can be generated between two adjacent metal wires, and an air gap is formed between the two adjacent metal wires, so that the dielectric constant of the capacitor can be reduced, and the working efficiency of the semiconductor device is improved.
Specifically, the forming a hollow dielectric layer between the plurality of metal lines in step 102 includes:
forming a first hollow dielectric layer on one side of the substrate, wherein the first hollow dielectric layer covers at least part of the metal wire, and the first hollow dielectric layer fills the opening;
and grinding the first hollow medium layer to remove the first hollow medium layer on the metal wire, so that the first hollow medium layer remained in the opening forms the hollow medium layer.
As shown in fig. 2c, a first hollow dielectric layer 3 is deposited on one side of the substrate 1 by a deposition process, the first hollow dielectric layer 3 covers at least a portion of the metal line 21, and the first hollow dielectric layer 3 fills the opening 20. Due to the setting of the filling parameters, at least one air gap 30 is formed in the first hollow dielectric layer 3 filled in each opening 20, that is, at least one air gap 30 is formed in each opening 20, so as to ensure that at least one air gap 30 is formed between any two adjacent metal lines 21. The first hollow dielectric layer 3 may be a low-k material, such as silicon nitride (sin), carbon-containing silicon Nitride (NDC), etc., to further reduce the k of the capacitor formed by two adjacent metal lines, thereby improving the operating efficiency of the semiconductor device, such as programming efficiency.
Then, as shown in fig. 2d, the first hollow medium layer 3 is polished by Chemical Mechanical Polishing (CMP) (the metal wire 21 may be used as a stop layer) to remove the first hollow medium layer 3 on the side of the metal wire 21 away from the substrate 1, and the first hollow medium layer 3 in the opening 20 is remained, i.e. the upper surface of the polished first hollow medium layer 3 is flush with the upper surface of the metal wire 21. The first hollow medium layer 3 remaining in the opening 20 constitutes a hollow medium layer 31, such that the hollow medium layer 31 is located between the plurality of metal lines 21, and at least one air gap 30 is formed in the hollow medium layer 31 between any two adjacent metal lines 21.
When the opening 20 penetrates only the metal layer 2, the hollow dielectric layer 31 is only located between the plurality of metal lines 21. When the opening 20 penetrates through the metal layer 2 and extends into the insulating layer 12, the hollow dielectric layer 31 is located between the metal lines 21 and extends into the insulating layer 12. The material of the hollow dielectric layer 31 may be the same as or different from that of the insulating layer 12, and is not particularly limited herein.
103, forming an interlayer dielectric layer on the metal wire and the hollow dielectric layer, wherein the etching rates of the interlayer dielectric layer and the hollow dielectric layer are different.
In the embodiment of the invention, the materials of the interlayer dielectric layer and the hollow dielectric layer can be different, so that the etching rates of the interlayer dielectric layer and the hollow dielectric layer are different. The materials of the interlayer dielectric layer and the hollow dielectric layer can be the same, but the interlayer dielectric layer and the hollow dielectric layer adopt different processes to form dielectric layers with different qualities, so that the etching rates of the interlayer dielectric layer and the hollow dielectric layer are different.
When the contact hole is formed in the interlayer dielectric layer subsequently, due to the fact that the etching rates of the interlayer dielectric layer and the hollow dielectric layer are different, even if the etching of the contact hole is deviated, the hollow dielectric layer can be used as a stop layer, the contact hole is prevented from being etched into the hollow dielectric layer between the metal wires, and further the air gap in the hollow dielectric layer is at least partially prevented from being damaged, so that the capacitance between the metal wires is reduced, and the working efficiency of the semiconductor device, such as programming efficiency, is improved.
Specifically, as shown in fig. 2e, an interlayer dielectric layer 4 is deposited on the plurality of metal lines 21 and the hollow dielectric layer 31 by a deposition process, and the interlayer dielectric layer 4 completely covers the upper surfaces of the plurality of metal lines 21 and the hollow dielectric layer 31.
Preferably, the etching rate of the hollow dielectric layer 31 is smaller than that of the interlayer dielectric layer 4. When the materials of the hollow dielectric layer 31 and the interlayer dielectric layer 4 are different, the hollow dielectric layer 31 may be silicon nitride, carbon-containing silicon nitride, or the like, and the interlayer dielectric layer 4 may be silicon dioxide, or the like, so that the etching rate of the hollow dielectric layer 31 is less than that of the interlayer dielectric layer 4. When the materials of the hollow dielectric layer 31 and the interlayer dielectric layer 4 are the same, the hollow dielectric layer 31 may be formed between the plurality of metal lines 21 by using an HDP (high density plasma) process, and the interlayer dielectric layer 4 may be formed on the plurality of metal layers 21 and the hollow dielectric layer 31 by using a TEOS (tetraethylorthosilicate) process, so that the etching rate of the hollow dielectric layer 31 is less than that of the interlayer dielectric layer 4.
Further, the method further includes step 104, where step 104 specifically is:
and forming a contact structure which penetrates through the interlayer dielectric layer and is connected with the metal wire.
As shown in fig. 2f, a contact hole 40 is etched in the interlayer dielectric layer 4, the contact hole 40 penetrating the interlayer dielectric layer 4. The number of the contact holes 40 may be plural, and the plurality of contact holes 40 correspond to the plurality of metal lines 21 one to one. The contact holes 40 may be perfectly aligned with their corresponding metal lines 21, i.e., the bottom of the contact holes 40 is completely located on their corresponding metal lines 21. Due to the error of the etching process, the contact hole 40 may not be aligned completely with its corresponding metal line 21, i.e., the bottom of the contact hole 40 is partially located on its corresponding metal line 21 and partially located on the hollow dielectric layer 31. Due to the fact that the etching rates of the hollow dielectric layer 31 and the interlayer dielectric layer 4 are different, the contact hole 40 cannot be etched into the hollow dielectric layer 31 after penetrating through the interlayer dielectric layer 4, and therefore the air gap 30 in the hollow dielectric layer 31 is at least partially prevented from being damaged.
Then, the contact hole 40 is filled with the contact structure 5, i.e., the contact structure 5 penetrates the interlayer dielectric layer 4. The number of the contact holes 40 may be plural, so that the number of the contact structures 5 may be plural, and the plurality of contact structures 5 correspond to the plurality of metal lines 21 one to one. The contact structures 5 and their corresponding metal lines 21 may be completely aligned, i.e. the bottom of the contact structures 5 is completely located on their corresponding metal lines 21, so that the contact structures 5 and their corresponding metal lines 21 are electrically connected; the contact structures 5 and their corresponding metal lines 21 may not be completely aligned, i.e. the bottom portions of the contact structures 5 are located on their corresponding metal lines 21 and the portions are located on the hollow dielectric layer 31, as long as the contact structures 5 and their corresponding metal lines 21 are electrically connected.
It should be noted that other metal lines may also be formed on the interlayer dielectric layer 4, and the other metal lines are electrically connected to the contact structure 5, so that the metal line 21 may be electrically connected to other metal lines located at different layers through the contact structure 5.
According to the manufacturing method of the semiconductor device, the hollow dielectric layer is formed among the plurality of metal wires which are distributed at intervals, then the interlayer dielectric layer is formed on the metal wires and the hollow dielectric layer, the etching rates of the interlayer dielectric layer and the hollow dielectric layer are different, when the contact holes are etched in the interlayer dielectric layer on the metal wires subsequently, even if the etching deviation of the contact holes occurs, the hollow dielectric layer can be used as a stop layer, the contact holes are prevented from being etched into the hollow dielectric layer among the metal wires, so that the air gaps in the hollow dielectric layer among the metal wires are at least partially prevented from being damaged by the contact holes, the capacitance among the metal wires is reduced, and the working efficiency of the semiconductor device, such as the programming efficiency, is improved.
Correspondingly, the embodiment of the invention also provides a semiconductor device which can be formed by the manufacturing method of the semiconductor device.
Referring to fig. 3, an embodiment of the present invention further provides a semiconductor device, including:
a substrate 1;
a plurality of metal lines 21 on the substrate 1, wherein the plurality of metal lines 21 are distributed at intervals;
a hollow dielectric layer 31 between the plurality of metal lines 21; and the number of the first and second groups,
and the interlayer dielectric layer 4 is positioned on the metal wire 21 and the hollow dielectric layer 31, and the etching rates of the interlayer dielectric layer 4 and the hollow dielectric layer 31 are different.
The semiconductor device can be applied to a memory, and the memory can comprise a memory array structure and a peripheral structure connected with the memory array structure. The substrate 1 may be a substrate in a memory array structure, or may be a substrate in a peripheral structure. When the base 1 is a base in a memory array structure, the base 1 may include a first substrate and a stack layer on the first substrate, and the metal line 21 may be a metal interconnection line, such as a bit line, in a back-end process of the memory array structure; when the base 1 is a base in the peripheral structure, the base 1 may include a second substrate and an insulating layer on the second substrate, and the metal line 21 may be a metal interconnection line of a back-end process in the peripheral structure.
The hollow dielectric layer 31 has air gaps 30 therein, and at least one air gap 30 is provided in the hollow dielectric layer 31 between any two adjacent metal lines 21. Capacitance effect is generated between two adjacent metal lines 21, and an air gap is formed between two adjacent metal lines 21, so that the dielectric constant of the capacitor can be reduced, and the working efficiency of the semiconductor device can be improved. The hollow dielectric layer 31 may be a low-k material, such as silicon nitride (sin), carbon-containing silicon Nitride (NDC), etc., to further reduce the k of the capacitor formed by two adjacent metal lines 21, thereby improving the operating efficiency of the semiconductor device, such as programming efficiency.
The materials of the interlayer dielectric layer 4 and the hollow dielectric layer 31 may be different, so that the etching rates of the interlayer dielectric layer 4 and the hollow dielectric layer 31 are different. The materials of the interlayer dielectric layer 4 and the hollow dielectric layer 31 can also be the same, but the interlayer dielectric layer 4 and the hollow dielectric layer 31 adopt different processes to form dielectric layers with different qualities, so that the etching rates of the interlayer dielectric layer 4 and the hollow dielectric layer 31 are different.
Preferably, the etching rate of the hollow dielectric layer 31 is smaller than that of the interlayer dielectric layer 4. When the materials of the hollow dielectric layer 31 and the interlayer dielectric layer 4 are different, the hollow dielectric layer 31 may be silicon nitride, carbon-containing silicon nitride, or the like, and the interlayer dielectric layer 4 may be silicon dioxide, or the like, so that the etching rate of the hollow dielectric layer 31 is less than that of the interlayer dielectric layer 4. When the materials of the hollow dielectric layer 31 and the interlayer dielectric layer 4 are the same, the hollow dielectric layer 31 may be formed between the plurality of metal lines 21 by using an HDP (high density plasma) process, and the interlayer dielectric layer 4 may be formed on the plurality of metal layers 21 and the hollow dielectric layer 31 by using a TEOS (tetraethylorthosilicate) process, so that the etching rate of the hollow dielectric layer 31 is less than that of the interlayer dielectric layer 4.
Further, the semiconductor device further includes:
and the contact structure penetrates through the interlayer dielectric layer and is connected with the metal wire.
As shown in fig. 3, the number of the contact structures 5 may be multiple, and the multiple contact structures 5 correspond to the multiple metal lines 21 one by one. The contact structures 5 and their corresponding metal lines 21 may be completely aligned, i.e. the bottom of the contact structures 5 is completely located on their corresponding metal lines 21, so that the contact structures 5 and their corresponding metal lines 21 are electrically connected; the contact structures 5 and their corresponding metal lines 21 may not be completely aligned, i.e., the bottom portions of the contact structures 5 are located on their corresponding metal lines 21 and the portions are located on the intermediate dielectric layer 31, as long as the contact structures 5 are electrically connected to their corresponding metal lines 21.
It should be noted that other metal lines may also be disposed on the interlayer dielectric layer 4, and the other metal lines are electrically connected to the contact structure 5, so that the metal line 21 may be electrically connected to the other metal lines through the contact structure 5.
According to the semiconductor device provided by the embodiment of the invention, the hollow dielectric layer is arranged among the plurality of metal wires which are distributed at intervals, the interlayer dielectric layer is arranged on the metal wires and the hollow dielectric layer, the etching rates of the interlayer dielectric layer and the hollow dielectric layer are different, and when the contact hole is etched in the interlayer dielectric layer on the metal wires subsequently, even if the etching of the contact hole has deviation, the hollow dielectric layer can be used as a stop layer to prevent the contact hole from being etched into the hollow dielectric layer between the metal wires, so that the contact hole is at least partially prevented from damaging air gaps in the hollow dielectric layer between the metal wires, the capacitance between the metal wires is reduced, and the working efficiency, such as programming efficiency, of the semiconductor device is improved.
Fig. 4 is a schematic structural diagram of a memory according to an embodiment of the present invention.
As shown in fig. 4, the memory includes a memory array structure 100, and a peripheral structure 200 connected to the memory array structure 100. Specifically, at least one of the memory array structure 100 and the peripheral structure 200 includes the semiconductor device in the above-described embodiment, and will not be described in detail herein.
The memory array structure 100 may be a non-volatile memory array structure, for example, the memory array structure 100 may be a NAND flash memory, a NOR flash memory, or the like. The peripheral structure 200 may include devices such as CMOS (complementary metal oxide semiconductor), SRAM (static random access memory), DRAM (dynamic random access memory), FPGA (field programmable gate array), CPU (central processing unit), Xpoint chip, and the like.
Specifically, the peripheral structure 200 may be located on the memory array structure 100, and the peripheral structure 200 is connected to the memory array structure 100. The memory array structure 100 and the peripheral structure 200 may also adopt other architecture forms, for example, the peripheral structure 200 is located below the memory array structure 100, i.e., a puc (peripheral under core array) architecture, or the peripheral structure 200 and the memory array structure 100 are arranged in parallel, i.e., a pnc (peripheral under core array) architecture, and the like, which is not limited herein.
The memory provided by the embodiment of the invention can at least partially prevent the contact holes from damaging air gaps in the hollow dielectric layers between the metal wires, thereby reducing the capacitance between the metal wires, improving the working efficiency of a semiconductor device, such as programming efficiency, and improving the programming performance of the memory.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (11)
1. A method for manufacturing a semiconductor device, comprising:
providing a substrate and a plurality of metal wires positioned on the substrate, wherein the metal wires are distributed at intervals;
forming a hollow dielectric layer between the plurality of metal lines;
and forming an interlayer dielectric layer on the metal wire and the hollow dielectric layer, wherein the etching rates of the interlayer dielectric layer and the hollow dielectric layer are different.
2. The method of claim 1, wherein an etching rate of the hollow dielectric layer is less than an etching rate of the interlayer dielectric layer.
3. The method of claim 1, wherein the step of providing a substrate and a plurality of metal lines on the substrate comprises:
forming a metal layer on the substrate;
forming at least one opening in the metal layer such that the opening separates the metal layer into the plurality of metal lines.
4. The method of claim 3, wherein the step of forming a hollow dielectric layer between the plurality of metal lines comprises:
forming a first hollow dielectric layer on one side of the substrate, wherein the first hollow dielectric layer covers at least part of the metal wire, and the first hollow dielectric layer fills the opening;
and grinding the first hollow medium layer to remove the first hollow medium layer on the metal wire, so that the first hollow medium layer remained in the opening forms the hollow medium layer.
5. The method of manufacturing a semiconductor device according to claim 1, further comprising:
and forming a contact structure which penetrates through the interlayer dielectric layer and is connected with the metal wire.
6. The method of claim 1, wherein at least one air gap is formed in the hollow dielectric layer between two adjacent metal lines.
7. A semiconductor device, comprising:
a substrate;
a plurality of metal lines on the substrate, the plurality of metal lines being spaced apart;
a hollow dielectric layer located between the plurality of metal lines; and the number of the first and second groups,
and the interlayer dielectric layer is positioned on the metal wire and the hollow dielectric layer, and the etching rates of the interlayer dielectric layer and the hollow dielectric layer are different.
8. The semiconductor device according to claim 7, wherein an etching rate of the hollow dielectric layer is smaller than an etching rate of the interlayer dielectric layer.
9. The semiconductor device according to claim 7, further comprising:
and the contact structure penetrates through the interlayer dielectric layer and is connected with the metal wire.
10. The semiconductor device of claim 7, wherein at least one air gap is provided in the hollow dielectric layer between two adjacent metal lines.
11. A memory comprises a memory array structure and a peripheral structure connected with the memory array structure;
at least one of the memory array structure and the peripheral structure includes the semiconductor device according to any one of claims 7 to 10.
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| CN202111650909.8A CN114284209A (en) | 2021-12-30 | 2021-12-30 | Manufacturing method of semiconductor device, semiconductor device and memory |
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| CN202111650909.8A CN114284209A (en) | 2021-12-30 | 2021-12-30 | Manufacturing method of semiconductor device, semiconductor device and memory |
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