CN117133805A - Mixed drain electrode enhanced GaN high electron mobility transistor - Google Patents
Mixed drain electrode enhanced GaN high electron mobility transistor Download PDFInfo
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- CN117133805A CN117133805A CN202311340326.4A CN202311340326A CN117133805A CN 117133805 A CN117133805 A CN 117133805A CN 202311340326 A CN202311340326 A CN 202311340326A CN 117133805 A CN117133805 A CN 117133805A
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- 239000002184 metal Substances 0.000 claims abstract description 73
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 68
- 230000004888 barrier function Effects 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 238000002161 passivation Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 8
- 230000005684 electric field Effects 0.000 abstract description 7
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 43
- 229910002601 GaN Inorganic materials 0.000 description 42
- 230000015556 catabolic process Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 6
- 239000011295 pitch Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention relates to a mixed drain electrode enhanced GaN high electron mobility transistor, and belongs to the technical field of semiconductors. The transistor comprises a metal source electrode, a metal gate electrode, a P-AlGaN region, a drain electrode field plate, a Schottky drain electrode, an ohmic drain electrode, an AlGaN barrier layer, a GaN buffer layer and a substrate layer. The p-type doped AlGaN region introduced by the invention realizes the enhancement of the device; the Schottky/ohmic contact mixed drain electrode introduced by the invention can improve the contact characteristic of a pure ohmic drain electrode, so that the contact surface of the pure ohmic drain electrode and an AlGaN barrier layer becomes smoother, and the electric field distribution of a drain end can be improved; the drain electrode field plate introduced by the invention also has the function of a metal field plate, and can disperse the electric field concentrated at the drain end, thereby further improving the withstand voltage of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a mixed drain electrode enhanced GaN high electron mobility transistor.
Background
The semiconductor industry has developed rapidly under moore's law for decades, and the first generation of semiconductor material silicon has been the most widely used semiconductor material by virtue of its many advantages, and the silicon process is also the most mature integrated process. Along with the increasing requirements of various high-power equipment on the performances of voltage resistance, frequency and the like of power electronic devices, the traditional Si and GaAs devices are still applicable by continuously improving the manufacturing process, but the cost is extremely high, and the limitation of the physical characteristics of materials such as Si, gaAs and the like cannot meet the requirements of certain application scenes. The third-generation semiconductor material gallium nitride (GaN) has the advantages of strong radiation resistance, high breakdown electric field, high electron mobility, good heat conductivity and the like, so that a semiconductor device with large bandwidth, high gain, high-frequency voltage resistance, smaller size can be obtained, and the GaN-based semiconductor material gallium nitride (GaN) becomes a research hot spot in the field of high-power electronic devices nowadays. The AlGaN/GaN HEMT device utilizes a two-dimensional electron gas (2 DEG) conducting channel naturally formed by an III-V compound AlGaN/GaN heterojunction, has good frequency, voltage resistance and conduction characteristics, and has extremely wide development space and application value in the directions of high-power devices such as 5G technology, fast charge technology, microwave detection and the like.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a hybrid drain enhanced GaN high electron mobility transistor that achieves enhancement of the device by introducing a p-doped AlGaN region; a Schottky/ohmic contact mixed drain electrode is introduced to improve the contact characteristic of the pure ohmic drain electrode, so that the contact surface of the pure ohmic drain electrode and the AlGaN barrier layer is smoother, and the electric field distribution of a drain end can be improved; the induced drain electrode field plate also has the function of a metal field plate, and can disperse the electric field concentrated at the drain end, thereby further improving the withstand voltage of the device.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a hybrid drain enhanced GaN high electron mobility transistor comprises a metal source 1, a metal gate 2, a P-AlGaN region 3, a drain field plate 4, a Schottky drain 5, an ohmic drain 6, an AlGaN barrier layer 7, a GaN buffer layer 8 and a substrate layer 9.
The metal source electrode 1 is positioned on the upper surface of the AlGaN barrier layer 7 and is positioned on the left side of the metal grid electrode 2;
the metal grid electrode 2 is positioned between the metal source electrode 1 and the drain electrode field plate 4, and the lower surface of the metal grid electrode is in contact with the P-AlGaN region 3;
the P-AlGaN region 3 is positioned between the metal source electrode 1 and the drain electrode field plate 4, the upper surface of the P-AlGaN region is in contact with the metal gate electrode 2, and the lower surface of the P-AlGaN region is in contact with the AlGaN barrier layer 7;
the drain electrode field plate 4 is positioned on the right side of the metal grid electrode 2, and the lower surface of the drain electrode field plate is in contact with the Schottky drain electrode 5 and the ohmic drain electrode 6;
the Schottky drain electrode 5 is positioned between the metal gate electrode 2 and the ohmic drain electrode 6, the right side of the Schottky drain electrode is in contact with the ohmic drain electrode 6, the upper surface of the Schottky drain electrode is in contact with the drain electrode field plate 4, and the lower surface of the Schottky drain electrode is in contact with the AlGaN barrier layer 7;
the ohmic drain electrode 6 is positioned on the right side of the Schottky drain electrode 5 and is in contact with the Schottky drain electrode, the upper surface of the ohmic drain electrode is in contact with the drain electrode field plate 4, and the lower surface of the ohmic drain electrode is in contact with the AlGaN barrier layer 7;
the AlGaN barrier layer 7 is positioned on the lower surfaces of the metal source electrode 1, the P-AlGaN region 3, the Schottky drain electrode 5 and the ohmic drain electrode 6 and the upper surface of the GaN buffer layer 8;
the GaN buffer layer 8 is positioned on the lower surface of the AlGaN barrier layer 7 and the upper surface of the Si substrate layer 9;
the substrate layer 9 is located on the lower surface of the GaN buffer layer 8.
Optionally, the P-AlGaN region 3 is doped with P-type impurity with a concentration of specifically 4×10 18 cm -3 。
Optionally, the material of the metal source electrode 1 and the ohmic drain electrode 6 is Ti, al, ni or Au.
Optionally, the material of the metal gate 2, the drain field plate 4 and the schottky drain 5 is Ni or Au.
Alternatively, the substrate layer 9 is made of sapphire or Si.
Optionally, the metal source 1, the metal gate 2, the P-AlGaN region 3, the schottky drain 4, the ohmic drain 5 and the drain field plate 6 are covered by a passivation layer.
Optionally, the width w of the drain field plate 4 3 Is 2um, thickness h 4 Is 0.09um.
Optionally, the widths and thicknesses of the schottky drain electrode (5) and the ohmic drain electrode (6) are respectively equal. Width w of the schottky drain 5 4 0.75um, thickness h 5 Is 0.11um. Width w of ohmic drain electrode 6 5 0.75um, thickness h 10 Is 0.11um.
The invention has the beneficial effects that: according to the invention, the P-AlGaN layer is introduced under the gate, so that the enhancement of the device is realized, and the Schottky/ohm mixed drain electrode is used, so that the contact characteristic of the pure ohm drain electrode can be improved, the contact surface of the pure ohm drain electrode and the AlGaN barrier layer becomes smoother, and the electric field distribution at the drain end can be improved; the drain electrode field plate introduced by the invention also has the function of a metal field plate, and can disperse the electric field concentrated at the drain end, thereby further improving the withstand voltage of the device.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and other advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the specification.
Drawings
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in the following preferred detail with reference to the accompanying drawings, in which:
fig. 1 is a schematic diagram of the structure of an improved hybrid drain enhanced GaN high electron mobility transistor provided in example 1;
FIG. 2 is a schematic diagram of the dimensions of an embodiment of the improved hybrid drain enhancement GaN HEMT shown in FIG. 1;
FIG. 3 is a schematic diagram of a conventional enhanced GaN HEMT structure;
FIG. 4 is a schematic diagram showing the structural dimensions of the enhanced GaN HEMT shown in FIG. 3;
FIG. 5 is a graph of transfer characteristics of two different devices shown in FIGS. 1 and 3;
FIG. 6 is a graph of the output characteristics of two different curves shown in FIGS. 1 and 3;
FIG. 7 is a graph of breakdown characteristics of two different devices shown in FIGS. 1 and 3;
FIG. 8 is a graph showing the effect of different drain field plate lengths on the breakdown characteristic of the improved device;
FIG. 9 is a graph showing the effect of different gate-drain spacing on the breakdown characteristic of the improved device;
reference numerals: 1-metal source, 2-metal gate, 3-P-AlGaN region, 4-drain field plate, 5-Schottky drain, 6-ohmic drain, 7-AlGaN barrier layer, 8-GaN buffer layer, 9-substrate layer, 10-metal drain.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the illustrations provided in the following embodiments merely illustrate the basic idea of the present invention by way of illustration, and the following embodiments and features in the embodiments may be combined with each other without conflict.
Wherein the drawings are for illustrative purposes only and are shown in schematic, non-physical, and not intended to limit the invention; for the purpose of better illustrating embodiments of the invention, certain elements of the drawings may be omitted, enlarged or reduced and do not represent the size of the actual product; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numbers in the drawings of embodiments of the invention correspond to the same or similar components; in the description of the present invention, it should be understood that, if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc., that indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, it is only for convenience of describing the present invention and simplifying the description, but not for indicating or suggesting that the referred device or element must have a specific azimuth, be constructed and operated in a specific azimuth, so that the terms describing the positional relationship in the drawings are merely for exemplary illustration and should not be construed as limiting the present invention, and that the specific meaning of the above terms may be understood by those of ordinary skill in the art according to the specific circumstances.
Example 1:
the present embodiment provides a hybrid drain enhanced GaN high electron mobility transistor, which includes a metal source 1, a metal gate 2, a P-AlGaN region 3, a drain field plate 4, a schottky drain 5, an ohmic drain 6, an AlGaN barrier layer 7, a GaN buffer layer 8, and a substrate layer 9, as shown in fig. 1 to 2.
The metal source 1 is located on the upper surface of the AlGaN barrier layer 7 and on the left side of the metal gate 2. Width w of metal source 1 1 1um, thickness h 1 Is 0.11um.
The metal gate 2 is located between the metal source 1 and the drain field plate 4, with its lower surface in contact with the P-AlGaN region 3. Width w of metal gate 2 2 Is 2um, thickness h 2 Is 0.11um.
The P-AlGaN region 3 is located between the metal source 1 and drain field plate 4 with its upper surface in contact with the metal gate 2 and its lower surface in contact with the AlGaN barrier layer 7. Width w of P-AlGaN region 3 2 Is 2um, thickness h 3 Is 0.05um. The doping type is uniform doping, and the doped P-type impurity concentration is 4 multiplied by 10 18 cm -3 。
The drain field plate 4 is located on the right side of the metal gate 2, and its lower surface is in contact with the schottky drain 5 and the ohmic drain 6. Width w of drain field plate 4 3 Is 2um, thickness h 4 Is 0.09um.
The schottky drain 5 is located between the metal gate 2 and the ohmic drain 6 and contacts the ohmic drain 6 on its right side, with its upper surface in contact with the drain field plate 4 and its lower surface in contact with the AlGaN barrier layer 7. Width w of schottky drain 5 4 0.75um, thickness h 5 Is 0.11um.
The ohmic drain electrode 6 is located on the right side of the schottky drain electrode 5 and is in contact with the drain field plate 4 on its upper surface and the AlGaN barrier layer 7 on its lower surface. Width w of ohmic drain electrode 6 5 0.75um, thickness h 10 Is 0.11um.
The AlGaN barrier layer 7 is located on the lower surface of the metal source 1, the P-AlGaN region 3, the schottky drain 5, the ohmic drain 6, and the upper surface of the GaN buffer layer 8. Thickness h of AlGaN barrier layer 7 6 Is 0.025um.
GaN buffer layer 8 is positioned on AlGaN barrier layer 7 small meterA face and an upper surface of the substrate layer 9. Thickness h of GaN buffer layer 8 7 Is 1.575um.
The substrate layer 9 is located on the lower surface of the GaN buffer layer 8. Thickness h of substrate layer 9 8 Is 0.4um.
The transistor device dimensions of example 1 are detailed in table 1.
Table 1 transistor device size parameter table of example 1
Comparison experiment:
performance comparison analysis was performed for the hybrid drain enhanced GaN high electron mobility transistor of example 1 with a conventional enhanced GaN high electron mobility transistor.
As shown in fig. 3 to 4, the conventional enhanced GaN high electron mobility transistor includes a metal source 1, a metal gate 2, a P-AlGaN region 3, a metal drain 10, an AlGaN barrier layer 7, a GaN buffer layer 8, and a substrate layer 9.
The metal source electrode 1 is positioned on the upper surface of the AlGaN barrier layer 7 and positioned on the left side of the metal grid electrode 2; width w of metal source 1 1 1um, height h 1 Is 0.11um.
The metal grid electrode 2 is positioned between the metal source electrode 1 and the metal drain electrode 10, and the lower surface of the metal grid electrode is in contact with the P-AlGaN region 3; width w of metal gate 2 2 Is 2um, height h 2 Is 0.11um.
The P-AlGaN region 3 is positioned between the metal source electrode 1 and the metal drain electrode 10, the upper surface of the P-AlGaN region is in contact with the metal gate electrode 2, and the lower surface of the P-AlGaN region is in contact with the AlGaN barrier layer 7; width w of P-AlGaN region 3 2 Is 2um, thickness h 3 Is 0.05um; the doping type is uniform doping, and the doped P-type impurity concentration is 4 multiplied by 10 18 cm -3 。
The metal drain electrode 10 is positioned on the right side of the metal gate electrode 2, and the lower surface of the metal drain electrode is in contact with the AlGaN barrier layer 7; metal drain electrode 10Width w 6 1.5um, thickness h 9 Is 0.11um.
The AlGaN barrier layer 7 is positioned on the lower surfaces of the metal source electrode 1, the P-AlGaN region 3 and the metal drain electrode 10 and the upper surface of the GaN buffer layer 8; thickness h of AlGaN barrier layer 7 6 Is 0.025um.
The GaN buffer layer 8 is positioned on the small surface of the AlGaN barrier layer 7 and the upper surface of the substrate layer 9; thickness h of GaN buffer layer 8 7 Is 1.575um.
The substrate layer 9 is positioned on the lower surface of the GaN buffer layer (8); thickness h of substrate layer 9 8 Is 0.4um.
The dimensions of a conventional enhanced GaN high electron mobility transistor device are detailed in table 2.
Table 2 enhanced GaN hemt device size parameter table
Fig. 5 is t=300k, v ds At =5v, the transfer characteristics of the conventional enhancement mode GaN hemt and the modified hybrid drain enhancement mode GaN hemt (example 1) have similar threshold voltage characteristics, and both devices are at V g =1v or so.
Fig. 6 is t=300k, v gs Comparison of output characteristics of conventional enhancement type GaN high electron mobility transistor, modified hybrid drain enhancement type GaN high electron mobility transistor (example 1) at=5v.
Fig. 7 is t=300k, v gs When=0v, the breakdown curves of the conventional enhancement type GaN high electron mobility transistor and the modified hybrid drain enhancement type GaN high electron mobility transistor (example 1) are compared. The withstand voltage of the traditional device is 597V, and the withstand voltage of the improved device is 952V, which is improved by about 59.5% compared with 355V.
Fig. 8 is t=300K，V gs Effect of different drain field plate lengths on the breakdown characteristic of the modified hybrid drain enhanced GaN high electron mobility transistor (example 1) at =0v. As can be seen from fig. 8, the length of the drain field plate has a great influence on the breakdown voltage of the device, and for the improved hybrid drain enhanced GaN high electron mobility transistor, the length of the field plate cannot be too long or too short, which results in too short a gate-drain pitch of the device, so that the device breaks down in advance, and the advantage of the field plate cannot be exerted if too short.
Fig. 9 is t=300k, v gs Effect of different gate-drain pitches on the breakdown profile of the modified hybrid drain-enhanced GaN high-electron-mobility transistor (example 1) at =0v. As can be seen from fig. 9, the different gate-drain pitches have different effects on the breakdown voltage of the device, and for the improved hybrid drain-enhanced GaN high electron mobility transistor, too short a gate-drain pitch can cause the device to breakdown in advance, and saturation occurs when the gate-drain pitch increases to a certain extent.
Finally, it is noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the present invention, which is intended to be covered by the claims of the present invention.
Claims (7)
1. The mixed drain enhanced GaN high electron mobility transistor comprises a metal source electrode (1), a metal gate electrode (2), a P-AlGaN region (3), an AlGaN barrier layer (7), a GaN buffer layer (8) and a substrate layer (9), and is characterized by further comprising a drain field plate (4), a Schottky drain electrode (5) and an ohmic drain electrode (6);
the metal source electrode (1) is positioned on the upper surface of the AlGaN barrier layer (7) and is positioned on the left side of the metal gate electrode (2);
the metal grid (2) is positioned between the metal source electrode (1) and the drain electrode field plate (4), and the lower surface of the metal grid is in contact with the P-AlGaN region (3);
the P-AlGaN region (3) is positioned between the metal source electrode (1) and the drain electrode field plate (4), the upper surface of the P-AlGaN region is in contact with the metal gate electrode (2), and the lower surface of the P-AlGaN region is in contact with the AlGaN barrier layer (7);
the drain electrode field plate (4) is positioned on the right side of the metal grid electrode (2), and the lower surface of the drain electrode field plate is in contact with the Schottky drain electrode (5) and the ohmic drain electrode (6);
the Schottky drain electrode (5) is positioned between the metal gate electrode (2) and the ohmic drain electrode (6), the right side of the Schottky drain electrode is contacted with the ohmic drain electrode (6), the upper surface of the Schottky drain electrode is contacted with the drain electrode field plate (4), and the lower surface of the Schottky drain electrode is contacted with the AlGaN barrier layer (7);
the ohmic drain electrode (6) is positioned on the right side of the Schottky drain electrode (5) and is in contact with the Schottky drain electrode, the upper surface of the ohmic drain electrode is in contact with the drain electrode field plate (4), and the lower surface of the ohmic drain electrode is in contact with the AlGaN barrier layer (7);
the AlGaN barrier layer (7) is positioned on the lower surfaces of the metal source electrode (1), the P-AlGaN region (3), the Schottky drain electrode (5), the ohmic drain electrode (6) and the GaN buffer layer (8);
the GaN buffer layer (8) is positioned on the lower surface of the AlGaN barrier layer (7) and the upper surface of the Si substrate layer (9);
the substrate layer (9) is positioned on the lower surface of the GaN buffer layer (8).
2. The hybrid drain enhanced GaN high electron mobility transistor of claim 1, wherein the material of the metal source (1) and ohmic drain (6) is Ti, al, ni or Au.
3. The hybrid drain enhanced GaN high electron mobility transistor of claim 1, wherein the material of the metal gate (2), drain field plate (4) and schottky drain (5) is Ni or Au.
4. The hybrid drain enhanced GaN high electron mobility transistor of claim 1, wherein the metal source (1), metal gate (2), P-AlGaN region (3), schottky drain (4), ohmic drain (5) and drain field plate (6) are covered around by a passivation layer.
5. The hybrid drain-enhanced GaN high electron mobility transistor of claim 1, 3 or 4 whichCharacterized in that the width w of the drain field plate (4) 3 Is 2um, thickness h 4 Is 0.09um.
6. The hybrid drain enhanced GaN high electron mobility transistor of claim 1, 3 or 4, wherein the schottky drain (5) and ohmic drain (6) have equal widths and thicknesses, respectively.
7. The hybrid drain enhanced GaN high electron mobility transistor of claim 6, wherein said schottky drain (5) and ohmic drain (6) have a width of 0.75um and a thickness of 0.11um.
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|---|---|---|---|---|
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| CN107078153A (en) * | 2014-10-03 | 2017-08-18 | 泰勒斯公司 | The field-effect transistor and its manufacture method of mixing drain contact with optimization |
| CN114695541A (en) * | 2022-03-31 | 2022-07-01 | 西交利物浦大学 | Gallium nitride device |
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2023
- 2023-10-16 CN CN202311340326.4A patent/CN117133805A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010278137A (en) * | 2009-05-27 | 2010-12-09 | Sharp Corp | Semiconductor device |
| US20160087625A1 (en) * | 2014-09-19 | 2016-03-24 | Kabushiki Kaisha Toshiba | Gate control device, semiconductor device, and method for controlling semiconductor device |
| CN107078153A (en) * | 2014-10-03 | 2017-08-18 | 泰勒斯公司 | The field-effect transistor and its manufacture method of mixing drain contact with optimization |
| CN114975588A (en) * | 2022-02-18 | 2022-08-30 | 中山市华南理工大学现代产业技术研究院 | HEMT device with Schottky/ohmic drain structure and preparation method thereof |
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Non-Patent Citations (1)
| Title |
|---|
| JIELONG LIU, ETAL: "High-performance AlGaN/GaN HEMTs with hybrid schottky-ohmic drain for Ka-band applications", 《 IEEE TRANSACTIONS ON ELECTRON DEVICES》, 31 August 2022 (2022-08-31), pages 4189 * |
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