CN117116886A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN117116886A
CN117116886A CN202310577277.XA CN202310577277A CN117116886A CN 117116886 A CN117116886 A CN 117116886A CN 202310577277 A CN202310577277 A CN 202310577277A CN 117116886 A CN117116886 A CN 117116886A
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film
semiconductor device
wiring
metal film
metal
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冈部翔太
伊藤望
高桥裕治
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本公开涉及一种半导体器件及其制造方法，其中半导体器件包括第一金属膜，第一金属膜形成具有键合垫的最上层布线。在第一金属膜的晶粒边界处的杂质的浓度高于在第一金属膜中的晶粒中的杂质的浓度。第一金属膜中包括的晶粒的最大颗粒尺寸小于5μm。

Description

半导体器件及其制造方法
相关申请的交叉引用
本申请要求于2022年05月23日提交的、日本专利申请号2022-083565的优先权，其内容在此通过引用并入本申请。
技术领域
本公开涉及一种半导体器件及其制造方法。
背景技术
下面列出了公开的技术。
[专利文献1]日本未审查专利申请公开号2014-187073
例如，专利文献1描述了一种半导体器件。专利文献1中公开的半导体器件包括布线和OPM(垫上冶金(Over Pad Metallurgy))膜。布线是最上层布线。布线具有键合垫。布线由铝合金制成。OPM膜被布置在键合垫上。键合线被键合到键合垫，OPM膜介于它们之间。
发明内容
然而，在专利文献1中公开的半导体器件中，键合垫与键合线之间的键合的可靠性存在改进余地。其他问题和新颖特征将从说明书的描述和附图变得明显。
本公开的半导体器件包括第一金属膜，第一金属膜形成具有键合垫的最上层布线。第一金属膜的晶粒边界处的杂质的浓度高于第一金属膜中的晶粒中的杂质的浓度。第一金属膜中包括的晶粒的最大晶粒尺寸小于5μm。
键合垫与键合线之间的键合可靠性可以得到改善。
附图说明
图1是半导体器件DEV1的截面图。
图2是示出了制造半导体器件DEV1的方法的过程图。
图3是用于说明溅射步骤S1的截面图。
图4是用于说明布线图案化步骤S2的截面图。
图5是用于说明保护膜形成步骤S3的截面图。
图6是用于说明OPM膜形成步骤S4的截面图。
图7是半导体器件DEV2的截面图。
图8是半导体器件DEV3的截面图。
图9是半导体器件DEV4的截面图。
具体实施方式
将参考附图详细描述本公开的实施例。
(第一实施例)
将描述根据第一实施例的半导体器件。根据第一实施例的半导体器件被称为半导体器件DEV1。
<半导体器件DEV1的配置>
下面将描述半导体器件DEV1的配置。
图1是半导体器件DEV1的截面图。如图1中所示，半导体器件DEV1包括层间绝缘膜ILD、布线WL(第一金属膜)、保护膜PV、OPM膜OPM1(第二金属膜)和OPM膜OPM2。顺便提及，在图1中，省略了层间绝缘膜ILD下方的结构的图示。半导体器件DEV1是功率器件。功率器件的具体示例是IGBT(绝缘栅极双极晶体管)。然而，半导体器件DEV1不限于IGBT。
层间绝缘膜ILD是最上层的层间绝缘膜。层间绝缘膜ILD例如由氧化硅(SiO2)制成。布线WL被布置在层间绝缘膜ILD上。布线WL是最上层布线。布线WL具有键合垫BP1和键合垫BP2。当半导体器件DEV1是IGBT时，键合垫BP1和键合垫BP2分别是栅极电极和发射极电极。
布线WL包括第一金属元素作为主要组分。即，布线WL中的第一金属元素的含量为99％以上。第一金属元素例如是铝(Al)。
第一金属元素可以是铜(Cu)。布线WL2可以包括第二金属元素。当第一金属元素是铝时，第二金属元素例如是硅(Si)、铜(Cu)和钯(Pd)中的至少一种。
布线WL包括杂质。这些杂质例如是氧(O)。这些杂质可以是氮(N)或碳(C)。也就是说，布线WL可以包括氧、氮和碳中的至少一种作为杂质。
布线WL是多晶的。在布线WL的晶粒边界处的杂质的浓度高于在布线WL的晶粒中的杂质的浓度。当布线WL中包括的杂质是氧时，在布线WL的晶粒中的氧的浓度优选为0.6原子％以上且0.8原子％以下，并且在布线WL的晶粒边界中的氧的浓度优选为0.9原子％以上且1.5原子％以下。
在布线WL的晶粒边界处的杂质的浓度和在布线WL的晶粒中的杂质的浓度通过使用EPMA(电子探针微分析器)来进行测量。执行该测量时的电子束的斑直径被设置为1μm以下。在三个测量点处测量在布线WL的晶粒边界处的杂质的浓度和在布线WL的晶粒中的杂质的浓度，并且计算其平均值。
布线WL中包括的晶粒的最大颗粒尺寸小于5μm。布线WL中包括的晶粒的最大颗粒尺寸优选小于4μm。布线WL中包括的晶粒的最大值通过EBSD(电子背散射电子)方法进行测量。更具体地，首先，在布线WL的截面中获取EBSD图像。该EBSD图像具有1500倍的放大倍数，并且具有50μm×50μm的尺寸。其次，EBSD图像中具有最大颗粒尺寸的晶粒被标识，并且通过将晶粒的面积除以π/4而获得的值的平方根被计算。该平方根被认为是布线WL中包括的晶粒的最大颗粒尺寸。
布线WL的硬度优选为0.8GPa以上。布线WL的硬度通过ISO14577中指定的纳米压痕硬度测试来进行测量。该纳米压痕硬度测试的测试条件是：测量温度为室温，并且压头的压入深度为布线WL的厚度的大约10％。在10个测量点处测量布线WL的硬度，并且计算其平均值。
保护膜PV被布置在层间绝缘膜ILD上以覆盖布线WL。保护膜PV例如由聚酰亚胺制成。开口OP1和开口OP2形成在保护膜PV中。开口OP1沿厚度方向贯穿保护膜PV。键合垫BP1从开口OP1暴露。开口OP2沿厚度方向贯穿保护膜PV。键合垫BP2从开口OP2暴露。
开口OP1的开口宽度被称为宽度W1。开口OP2的开口宽度被称为宽度W2。宽度W1小于宽度W2。宽度W1优选为300μm以下。宽度W1例如为90μm以上。宽度W2优选为1000μm以上。宽度W2例如为10000μm以下。
OPM膜OPM1被布置在从开口OP1暴露的键合垫BP1上。例如，OPM膜OPM1具有无电解镀镍膜OPM1a、无电解镀钯膜OPM1b和无电解镀金膜OPM1c。
无电解镀镍膜OPM1a是包括镍(Ni)的无电解镀膜(通过无电解镀形成的膜)。无电解镀镍膜OPM1a被布置在从开口OP1暴露的键合垫BP1上。
无电解镀钯膜OPM1b是包括钯的无电解镀膜。无电解镀钯膜OPM1b被布置在无电解镀镍膜OPM1a上。无电解镀金膜OPM1c是包括金(Au)的无电解镀膜。无电解镀金膜OPM1c被布置在无电解镀钯膜OPM1b上。OPM膜OPM1可以不具有无电解镀钯膜OPM1b。在该情况下，无电解镀金膜OPM1c被布置在无电解镀镍膜OPM1a上。
OPM膜OPM2被布置在从开口OP2暴露的键合垫BP2上。OPM膜OPM2具有与OPM膜OPM1相同的膜配置。即，例如，OPM膜OPM2具有无电解镀镍膜OPM2a、无电解镀钯膜OPM2b和无电解镀金膜OPM2c。无电解镀镍膜OPM2a是包括镍的无电解镀膜。
无电解镀镍膜OPM2a被布置在从开口OP2暴露的键合垫BP2上。无电解镀钯膜OPM2b是包括钯的无电解镀膜。无电解镀钯膜OPM2b被布置在无电解镀镍膜OPM2a上。无电解镀金膜OPM2c是包括金的无电解镀膜。无电解镀金膜OPM2c被布置在无电解镀钯膜OPM2b上。OPM膜OPM2可以不具有无电解镀钯膜OPM2b。在该情况下，无电解镀金膜OPM2c被布置在无电解镀镍膜OPM2a上。
无电解镀镍膜OPM1a的厚度和无电解镀镍膜OPM2a的厚度分别被称为厚度T1和厚度T2。厚度T1和厚度T2例如是布线WL中包括的晶粒的最大颗粒尺寸的0.5倍以上。
半导体器件DEV1还可以具有键合线BW、夹具(clip)CL和键合层JL。
键合线BW包括第三金属元素作为主要组分。即，键合线BW中的第三金属元素的含量为99质量％以上。第三金属元素是铝、铜、银(Ag)和金中的任一种。键合线BW的一端为球部。键合线BW在球部处被键合到OPM膜OPM1。即，键合线BW经由OPM膜OPM1被键合到键合垫BP1。
夹具CL例如由铜或铜合金制成。夹具CL通过键合层JL被键合到键合垫BP2。键合层JL例如是诸如锡(Sn)合金的焊料合金。尽管未被示出，但键合垫BP1经由键合线BW电连接到引线框架等，并且键合垫BP2经由夹具CL和接合层JL电连接到引线框架等。
<制造半导体器件DEV1的方法>
下面将描述制造半导体器件DEV1的方法。
图2是示出了制造半导体器件DEV1的方法的过程图。如图2中所示，制造半导体器件DEV1的方法包括溅射步骤S1、布线图案化步骤S2、保护膜形成步骤S3、OPM膜形成步骤S4和封装步骤S5。
在溅射步骤S1之前，形成层间绝缘膜ILD及其底下结构。通过常规的已知方法形成层间绝缘膜ILD及其底下结构，因此这里省略其描述。
图3是用于说明溅射步骤S1的截面图。如图3中所示，在溅射步骤S1中，在层间绝缘膜ILD上形成布线WL的构成材料。用于该溅射的溅射气体包括例如氩气(Ar)和氧气(O2)。顺便提及，当氮作为杂质被引入到布线WL中时，使用氮气(N2)代替氧气，并且当碳作为杂质被引入到布线WL中时，使用包括碳(一氧化碳(CO)、甲烷(CH4)等)的气体。溅射气体中的氧气的含量优选为0.025体积％以上且0.25体积％以下。
图4是用于说明布线图案化步骤S2的截面图。在布线图案化步骤S2中，如图4中所示，对溅射步骤S1中形成的布线WL的构成材料进行图案化。在布线图案化步骤S2中，首先，在形成的布线WL的构成材料上形成抗蚀剂图案。该抗蚀剂图案通过对光致抗蚀剂进行曝光和显影而形成。其次，通过使用该抗蚀剂图案作为掩模，对形成的布线WL的构成材料进行干法蚀刻。因此，形成具有键合垫BP1和键合垫BP2的布线WL。
图5是用于说明保护膜形成步骤S3的截面图。如图5中所示，在保护膜形成步骤S3中，保护膜PV的构成材料被施加到层间绝缘膜ILD上以覆盖布线WL。其次，通过对所施加的保护膜PV的构成材料进行曝光和显影，形成开口OP1和开口OP2。第三，通过加热将所施加的保护膜PV的构成材料固化，以形成保护膜PV。
图6是用于说明OPM膜形成步骤S4的截面图。如图6中所示，在OPM膜形成步骤S4中，在从开口OP1暴露的键合垫BP1和从开口OP2暴露的键合垫BP2上形成OPM膜OPM1和OPM膜OPM2。例如，通过无电解镀来形成OPM膜OPM1和OPM膜OPM2。
在封装步骤S5中，引线框架等与OPM膜OPM1通过键合线BW连接，并且引线框架等与OPM膜OPM2通过夹具CL连接。因此，形成了具有图1中所示结构的半导体器件DEV1。
<半导体器件DEV1的效果>
下面将与根据比较示例的半导体器件相比较，来描述半导体器件DEV1的效果。根据比较示例的半导体器件被称为半导体器件DEV2。
图7是半导体器件DEV2的截面图。如图7中所示，半导体器件DEV2具有层间绝缘膜ILD、布线WL、保护膜PV、OPM膜OPM1和OPM膜OPM2。在半导体器件DEV2中，布线WL具有键合垫BP1和键合垫BP2。在半导体器件DEV2中，在布线WL的晶粒边界处的氧的浓度与在布线WL的晶粒中的氧的浓度大致相同。此外，在半导体器件DEV2中，布线WL中包括的晶粒的最大颗粒尺寸为5μm以上(大约17μm)。
难以在铝的特定晶面上生长无电解镀镍膜。由于布线WL是多晶的，因此这种特定晶面可以存在于键合垫BP1的表面和键合垫BP2的表面上。即使在键合垫BP1的表面和键合垫BP2的表面上存在这种特定晶面，并且当厚度T1和厚度T2被设置为布线WL中包括的晶粒的最大颗粒尺寸的0.5倍以上时，无电解镀镍膜OPM1a和无电解镀镍膜OPM2a横向生长，使得特定晶面导致被无电解镀镍膜OPM1a和无电解镀镍膜OPM2a覆盖。
在半导体器件DEV2中，布线WL中包括的晶粒例如通过在保护膜形成步骤S3中执行的加热而粗糙化，并且布线WL中包括的晶粒的最大颗粒尺寸为大约17μm。因此，除非厚度T1和厚度T2显著增加(增厚)，否则无电解镀镍膜OPM1a和无电解镀镍膜OPM2a破裂，并且OPM膜OPM1和OPM膜OPM2由于该破裂而破裂。键合线BW经由OPM膜OPM1被键合到键合垫BP1，但键合线BW可能从OPM膜OPM1中的裂纹开始从OPM膜OPM1剥离。因此，在半导体器件DEV2中，键合线BW与键合垫BP1之间的键合可靠性存在改进余地。
顺便提及，在半导体器件DEV2中同样地，通过增加厚度T1和厚度T2，可以利用无电解镀镍膜OPM1a和无电解镀镍膜OPM2a覆盖其处无电解镀镍膜OPM1a和无电解镀镍膜OPM2a难以生长的特定晶面。然而，在该情况下，由于无电解镀镍膜OPM1a和无电解镀镍膜OPM2a的形成而引起的应力增加，半导体器件DEV2可能翘曲。此外，在该情况下，由于无电解镀镍膜OPM1a和无电解镀镍膜OPM2a的形成，制造成本增加。
在半导体器件DEV1中，在溅射步骤S1中将少量氧气添加到溅射气体。因此，布线WL的晶粒边界被轻微氧化，并且在布线WL的晶粒边界处的氧的浓度高于在布线WL的晶粒中的氧的浓度。结果，在半导体器件DEV1中，即使在保护膜形成步骤S3中执行加热，相互扩散也被氧化的晶粒边界抑制，结果，布线WL中包括的晶粒不太可能被粗糙化，并且布线WL中包括的晶粒的最大颗粒尺寸小于5μm。
为了确认通过使在布线WL的晶粒边界处的氧的浓度高于在布线WL的晶粒中的氧的浓度而抑制布线WL中包括的晶粒的粗糙化，制备了样品1和样品2。在样品1和样品2中，溅射铝以形成布线WL。如表1中所示，在样品1中，溅射气体中的氧气的含量被设置为0.05体积％。另一方面，对于样品2，溅射气体仅包括氩气而不包括氧气。在溅射铝之后，样品1和样品2在400℃下退火30分钟。
表1
在样品1中，通过溅射形成的铝膜在晶粒边界处的氧的浓度高于通过溅射形成的铝膜在晶粒中的氧的浓度。另一方面，在样品2中，通过溅射形成的铝膜在晶粒边界处的氧的浓度低于通过溅射形成的铝膜在晶粒中的氧的浓度。
在样品1中，通过溅射形成的铝膜中包括的晶粒的最大颗粒尺寸为3.56μm。另一方面，在样品2中，通过溅射形成的铝膜中包括的晶粒的最大颗粒尺寸为16.84μm。根据该比较，确认了，当在布线WL的晶粒边界处的氧的浓度高于在布线WL的晶粒中的氧的浓度时，布线WL中包括的晶粒的粗糙化被抑制。顺便提及，在样品1中，由于抑制了晶粒的粗糙化，通过溅射形成的铝膜的硬度高于样品2中的硬度。
在半导体器件DEV1中，布线WL中包括的晶粒的最大颗粒尺寸小于5μm，因此无需增加厚度T1和厚度T2就能够防止在无电解镀镍膜OPM1a(OPM膜OPM1)和无电解镀镍膜OPM2a(OPM膜OPM2)中出现裂纹，并且最终改善了键合线BW与键合垫BP1之间的键合可靠性。顺便提及，即使当布线WL中包括的杂质是氮或碳时，存在于布线WL的晶粒边界处的氮或碳也抑制了布线WL中包括的晶粒的粗糙化，从而与上文一样，可以改善键合线BW与键合垫BP1之间的键合可靠性。
随着宽度W1变小(更具体地，随着宽度W1变为300μm以下)，键合线BW与OPM膜OPM1之间的键合面积变小，并且OPM膜OPM1中存在的裂纹容易影响键合可靠性。根据半导体器件DEV1，即使宽度W1为300μm以下，也可以改善键合线BW与键合垫BP1之间的键合可靠性。
(第二实施例)
将描述根据第二实施例的半导体器件。根据第二实施例的半导体器件被称为半导体器件DEV3。这里，将主要描述半导体器件DEV3和半导体器件DEV1之间的差异，并且将不再重复冗余描述。
<半导体器件DEV3的配置>
下面将描述半导体器件DEV3的配置。
图8是半导体器件DEV3的截面图。如图8中所示，半导体器件DEV3具有层间绝缘膜ILD、布线WL、保护膜PV和键合线BW。在半导体器件DEV3中，布线WL具有键合垫BP1。在半导体器件DEV3中，开口OP1形成在保护膜PV中。关于这一点，半导体器件DEV3的配置与半导体器件DEV1的配置相同。
在半导体器件DEV3中，OPM膜OPM1未形成在从开口OP1暴露的键合垫BP1上。在半导体器件DEV3中，键合线BW被直接键合到键合垫BP1。关于这些点，半导体器件DEV3的配置不同于半导体器件DEV1的配置。顺便提及，半导体器件DEV3例如是LSI(大规模集成电路)。
<半导体器件DEV3的效果>
下面将与根据比较示例的半导体器件相比较，来描述半导体器件DEV3的效果。根据比较示例的半导体器件被称为半导体器件DEV4。
图9是半导体器件DEV4的截面图。如图9中所示，半导体器件DEV4具有层间绝缘膜ILD、布线WL、保护膜PV和键合线BW。在半导体器件DEV4中，布线WL具有键合垫BP1。在半导体器件DEV4中，开口OP1形成在保护膜PV中。在半导体器件DEV4中，OPM膜OPM1未形成在从开口OP1暴露的键合垫BP1上。在半导体器件DEV4中，键合线BW被直接键合到键合垫BP1。
然而，在半导体器件DEV4中，在布线WL的晶粒边界处的杂质的浓度不高于在布线WL的晶粒中的杂质的浓度。结果，在半导体器件DEV4中，布线WL中包括的晶粒的最大颗粒尺寸为5μm以上，并且布线WL的硬度较低。因此，在半导体器件DEV4中，接线WL由于接线键合而变形，键合线BW正下方的键合垫BP1的厚度减小，并且在键合垫BP1中可能出现裂纹。这种裂纹引起键合垫BP1与键合线BW之间的键合可靠性的降低。
另一方面，在半导体器件DEV3中，布线WL中包括的晶粒的最大颗粒尺寸小于5μm，并且布线WL的硬度较高。因此，在半导体器件DEV3中，通过抑制布线WL由于接线键合而引起的变形，可以抑制键合线BW正下方的键合垫BP1的厚度的减小，并且最终抑制键合垫BP1的裂纹的出现。因此，根据半导体器件DEV3，可以改善键合线BW与键合垫BP1之间的键合可靠性。
上文已经基于实施例具体描述了本发明人做出的发明，但本发明不限于上述实施例，并且不用说，可以在不脱离本发明的范围的情况下，进行各种修改。

Claims (17)

1.一种半导体器件，包括：
第一金属膜，形成具有键合垫的最上层布线，
其中所述第一金属膜的晶粒边界处的杂质的浓度高于所述第一金属膜的晶粒中的杂质的浓度，并且
其中所述第一金属膜中包括的所述晶粒的最大颗粒尺寸小于5μm。
2.根据权利要求1所述的半导体器件，
其中所述第一金属膜包括第一金属元素，
其中所述第一金属膜中的所述第一金属元素的含量为99质量％以上，并且
其中所述第一金属元素是铝或铜。
3.根据权利要求2所述的半导体器件，
其中所述第一金属元素是铝，
其中所述第一金属膜还包括第二金属元素，并且
其中所述第二金属元素是铜、硅和钯中的至少一种。
4.根据权利要求1所述的半导体器件，
其中所述杂质是氧、氮和碳中的至少一种。
5.根据权利要求1所述的半导体器件，
其中所述杂质是氧，
其中所述第一金属膜的所述晶粒中的氧的浓度为0.6原子％以上且0.8原子％以下，
其中所述第一金属膜的所述晶粒边界处的氧的浓度为0.9原子％以上且1.5原子％以下。
6.根据权利要求1所述的半导体器件，包括布置在所述键合垫上的第二金属膜。
7.根据权利要求6所述的半导体器件，
其中所述第二金属膜是无电解镀膜。
8.根据权利要求7所述的半导体器件，
其中所述第二金属膜包括布置在所述键合垫上的第一膜，并且
其中所述第一膜是无电解镀镍膜。
9.根据权利要求8所述的半导体器件，
其中所述第二金属膜还包括布置在所述第一膜上的第二膜，并且
其中所述第二膜是无电解镀金膜。
10.根据权利要求8所述的半导体器件，
其中所述第二金属膜还包括布置在所述第一膜上的第二膜和布置在所述第二膜上的第三膜，
其中所述第二膜是无电解镀钯膜，并且
其中所述第三膜是无电解镀金膜。
11.根据权利要求8所述的半导体器件，包括键合线，
其中所述键合线被键合到所述第二金属膜。
12.根据权利要求11所述的半导体器件，
其中所述键合线包括第三金属元素，
其中所述键合线中的所述第三金属元素的含量为99质量％以上，并且
其中所述第三金属元素是铝、铜、银和金中的任一种。
13.根据权利要求1所述的半导体器件，包括键合线，
其中所述键合线被键合到所述键合垫。
14.根据权利要求1所述的半导体器件，
其中所述第一金属膜的硬度为0.8GPa以上。
15.根据权利要求1所述的半导体器件，包括覆盖所述第一金属膜的保护膜，
其中在所述保护膜中形成开口以暴露所述键合垫，并且
其中所述开口的宽度为300μm以下。
16.一种制造半导体器件的方法，所述方法包括：
通过溅射形成第一金属膜；以及
通过对所述第一金属膜进行图案化来形成最上层布线，所述最上层布线具有键合垫，
其中在执行所述溅射时，氧气被添加到溅射气体中。
17.根据权利要求16所述的方法，
其中所述溅射气体中的所述氧气的含量为0.025体积％以上且0.25体积％以下。
CN202310577277.XA 2022-05-23 2023-05-22 半导体器件及其制造方法 Pending CN117116886A (zh)

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