CN117116179A

CN117116179A - Display panel and display device

Info

Publication number: CN117116179A
Application number: CN202310985563.XA
Authority: CN
Inventors: 胡铖; 赖青俊
Original assignee: Xiamen Tianma Display Technology Co Ltd
Current assignee: Xiamen Tianma Display Technology Co Ltd
Priority date: 2023-08-07
Filing date: 2023-08-07
Publication date: 2023-11-24

Abstract

The invention discloses a display panel and a display device, which belong to the technical field of display, wherein the display panel comprises a driving circuit, the driving circuit comprises a shift register, and an input module of the shift register is at least connected with an input signal end, a first clock signal line and a first node; the control module is at least connected with the first voltage signal line, the second voltage signal line, the first node, the second node and the third node, and the first node is directly connected with the third node or is connected with the third node through the first adjusting module; the output module comprises a first output module and a second output module, wherein the first output module is at least connected with the first voltage signal line, the third node and the output signal end, and the second output module is at least connected with the second voltage signal line, the second node and the output signal end. The display device comprises the display panel. The driving circuit can effectively output control signals, and well achieves the driving control effect on the pixel units in the display area.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and more particularly, to a display panel and a display device.

Background

Along with the continuous progress of science and technology, more and more electronic devices with display functions are widely applied to daily life and work of people, bring great convenience to daily life and work of people, and become an indispensable important tool for people at present. The display panel is a main component of the electronic device to realize a display function.

Currently, a display panel on the market generally includes a display area and a frame area, where the display area is generally provided with a plurality of pixel units, and each pixel unit includes a pixel circuit. The frame region includes a peripheral driving circuit, such as a gate driving circuit, for providing control signals to the pixel units of the display region. Each pixel circuit is respectively and electrically connected with a peripheral driving circuit of the frame area, and a control signal is provided for the pixel circuit through the peripheral driving circuit so as to control the pixel circuit to provide driving current for the light-emitting element, so that the pixel units in the display area emit light orderly. The output of the gate driving circuit directly affects the display effect of the pixel unit.

Therefore, the design of the peripheral driving circuit in the frame area has been a big research focus in the display field.

Disclosure of Invention

In view of this, the present invention provides a display panel and a display device, which effectively output control signals through a peripheral driving circuit disposed in a frame region, so as to better achieve a driving control effect on pixel units in the display region.

The invention discloses a display panel, comprising: a driving circuit including a shift register, the shift register including: the input module is at least connected with the input signal end, the first clock signal line and the first node; the control module is at least connected with the first voltage signal line, the second voltage signal line, the first node, the second node and the third node, and the first node is directly connected with the third node or is connected with the third node through the first adjusting module; the output module comprises a first output module and a second output module, wherein the first output module is at least connected with the first voltage signal line, the third node and the output signal end, and the second output module is at least connected with the second voltage signal line, the second node and the output signal end.

Based on the same inventive concept, the invention also discloses a display device, which comprises the display panel.

Compared with the prior art, the display panel and the display device provided by the invention have the advantages that at least the following effects are realized:

the display panel provided by the invention can comprise a display area and a non-display area, wherein the non-display area of the display panel comprises a driving circuit, and the driving circuit is used for being respectively and electrically connected with the pixel circuits of all pixel units and providing control signals for the pixel circuits so that the pixel units in the display area can emit light orderly, and the display function of the display panel is realized. The driving circuit comprises a shift register, and the shift register at least comprises an input module, a control module and an output module so as to realize a shift control function of the driving circuit. The input module transmits an initial shift signal, namely an input signal, to each level shift register, and then the first output module and the second output module are conducted in a time-sharing mode under the control of the control module, so that the output signals of the output signal ends of each level shift register of the driving circuit respectively comprise a low-level signal and a high-level signal, the output signals of the output signal ends are further transmitted to pixel circuits of pixel units of the display area as control signals, driving control of the pixel circuits is achieved, and the luminous display effect of each pixel unit in the display panel can be further guaranteed. In the invention, the first node and the third node of the shift register can be directly connected, or can be connected through the first adjusting module, so that when the signal of the third node controls the first output module to be conducted, the potential of the third node is not influenced by the potential of the first node, the first output module is ensured to be completely conducted under the control of the signal of the third node as far as possible, the conducting effect of the first output module can be stabilized, and the first output module is ensured to stably transmit the output signal to the output signal end.

Of course, it is not necessary for any one product to practice the invention to achieve all of the technical effects described above at the same time.

Other features of the present invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a module connection of the shift register of FIG. 1;

FIG. 3 is a schematic diagram of another module connection of the shift register of FIG. 1;

FIG. 4 is a schematic diagram of another module connection of the shift register of FIG. 1;

FIG. 5 is a schematic diagram of another module connection of the shift register of FIG. 1;

FIG. 6 is a schematic diagram of a circuit connection structure of the shift register of FIG. 4;

FIG. 7 is a schematic diagram of a circuit connection structure of the shift register of FIG. 5;

FIG. 8 is a schematic diagram of another circuit connection structure of the shift register of FIG. 5;

FIG. 9 is a schematic diagram of another circuit connection structure of the shift register of FIG. 5;

FIG. 10 is a timing diagram of the shift register circuit of FIG. 8;

FIG. 11 is a diagram of the on state of the transistor of the circuit structure of FIG. 8 during a first period of time;

fig. 12 is a diagram of the on state of the transistor of the circuit structure of fig. 8 during a second period of time;

fig. 13 is a diagram of the on state of the transistor of the circuit structure of fig. 8 during a third period of time;

fig. 14 is a conductive state diagram of the transistor of the circuit structure of fig. 8 for a fourth period of time;

FIG. 15 is a timing waveform diagram of a third node and an output signal without a first capacitor therebetween in the prior art;

FIG. 16 is a schematic diagram of another circuit connection structure of the shift register of FIG. 4;

FIG. 17 is a schematic diagram of another circuit connection structure of the shift register of FIG. 4;

fig. 18 is a diagram of the on state of the transistor of the circuit structure of fig. 16 during a first period of time;

fig. 19 is a conductive state diagram of the transistor of the circuit structure of fig. 16 for a second period of time;

fig. 20 is a diagram of the on state of the transistor of the circuit structure of fig. 16 during a third period of time;

fig. 21 is a conductive state diagram of the transistor of the circuit structure of fig. 16 for a fourth period of time;

fig. 22 is a schematic view of a partial cross-sectional structure of the first transistor and the second transistor in fig. 8 and 16 fabricated on a substrate base plate;

Fig. 23 is a schematic view of another partial cross-sectional structure of the first transistor and the second transistor in fig. 8 and 16 fabricated on a substrate base plate;

fig. 24 is a schematic view of a partial planar structure of the first transistor and the second transistor in fig. 8 and 16 when they are formed on a substrate;

fig. 25 is a schematic view of another partial planar structure of the first transistor and the second transistor in fig. 8 and 16 when they are formed on a substrate;

fig. 26 is a schematic plan view of another display panel according to an embodiment of the present invention;

fig. 27 is a schematic view of a partial cross-sectional structure of the first transistor and the second transistor in fig. 26, 8, and 16 fabricated on a substrate base plate;

fig. 28 is a schematic view of another partial cross-sectional structure of the first transistor and the second transistor of fig. 26, 8, and 16 fabricated on a substrate base plate;

fig. 29 is a schematic view of another partial cross-sectional structure of the first transistor and the second transistor in fig. 26, 8, and 16 fabricated on a substrate base plate;

fig. 30 is a schematic view of another planar structure of a display panel according to an embodiment of the present invention;

fig. 31 is a schematic view of another plane structure of a display panel according to an embodiment of the present invention;

FIG. 32 is a schematic diagram of an electrical connection structure of the pixel cell of FIG. 31;

FIG. 33 is a schematic diagram of another module connection of the shift register of FIG. 1;

FIG. 34 is a schematic diagram of a circuit connection structure of the shift register of FIG. 33;

FIG. 35 is a schematic diagram of another module connection of the shift register of FIG. 1;

FIG. 36 is a schematic diagram of a circuit connection structure of the shift register of FIG. 35;

FIG. 37 is a timing diagram of the shift register circuit of FIG. 36;

FIG. 38 is a diagram of the on state of the transistor of the circuit structure of FIG. 36 during a first period of time;

fig. 39 is a conductive state diagram of the transistor of the circuit structure of fig. 36 for a second period of time;

fig. 40 is a diagram of the on state of the transistor of the circuit structure of fig. 36 during a third period of time;

fig. 41 is a diagram of the on state of the transistor of the circuit structure of fig. 36 during a fourth period of time;

fig. 42 is a schematic plan view of a display device according to an embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.

The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Accordingly, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims (the claims) and their equivalents. The embodiments provided by the embodiments of the present invention may be combined with each other without contradiction.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

Referring to fig. 1, fig. 2 and fig. 3 in combination, fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention, fig. 2 is a schematic module connection diagram of the shift register in fig. 1, and fig. 3 is a schematic module connection diagram of the shift register in fig. 1, where the display panel 000 provided in this embodiment includes:

A driving circuit 00, the driving circuit 00 including a shift register 01, the shift register 01 including:

the input module 10, the input module 10 is connected to at least the input signal terminal STV, the first clock signal line CK and the first node N1;

the control module 20, the control module 20 is connected to at least the first voltage signal line VGL, the second voltage signal line VGH, the first node N1, the second node N2 and the third node N3, and the first node N1 is directly connected to the third node N3 or connected through the first adjustment module 301;

the output module 40, the output module 40 includes a first output module 401 and a second output module 402, the first output module 401 is at least connected to the first voltage signal line VGL, the third node N3 and the output signal terminal OUT, and the second output module 402 is at least connected to the second voltage signal line VGH, the second node N2 and the output signal terminal OUT.

Specifically, the display panel 000 provided in this embodiment may include a display area AA and a non-display area NA (i.e., a frame area), where the non-display area NA of the display panel 000 includes a driving circuit 00, the driving circuit 00 may be a gate driving circuit, the display area AA may be provided with a plurality of pixel units P, each pixel unit P may include a pixel circuit P1 and a light emitting element P2 that are electrically connected, the driving circuit 00 is electrically connected to the pixel circuit P1 of each pixel unit P, and a control signal (e.g., a scan control signal or a light emitting control signal) is provided to the pixel circuit P1 through the driving circuit 00 so as to control the pixel circuit P1 to provide a driving current for the light emitting element P2, so that the pixel units P in the display area AA emit light in order, thereby realizing a display function of the display panel 000. It is to be understood that the Light Emitting element P2 in this embodiment may be an Organic Light-Emitting Diode (OLED), a Micro LED or a Micro LED, and may be selectively set according to practical situations in specific implementation, which is not limited in this embodiment. In the drawings of the present embodiment, the pixel circuit P1 is illustrated in a block diagram, and in the specific implementation, the electrical connection structure of the pixel circuit P1 can be understood with reference to the structure in the related art, which is not described herein.

The driving circuit 00 of the present embodiment includes a shift register 01, alternatively, the driving circuit 00 may include a plurality of shift registers 01 cascaded, where the first shift register 01 is connected to the input signal terminal STV, the second and subsequent shift registers 01 may be understood as input signal terminals IN, and the second and subsequent shift registers 01 may have their input signal terminals IN connected to the output signal terminal OUT of the previous shift register, so as to implement the shift control function of the driving circuit 00.

It can be understood that, in fig. 1 of the present embodiment, the driving circuit 00 is located at one side of the display area AA (in fig. 1, the driving circuit 00 is located at the left side of the display area AA as an example), the control signal is provided to the pixel units P of the display area AA through a plurality of cascaded shift registers 01, and among the plurality of cascaded shift registers 01 included in the driving circuit 00, the first stage shift register may be electrically connected to the pixel circuits P1 of the pixel units P of the first row, the second stage shift register may be electrically connected to the pixel circuits P1 of the pixel units P of the second row, and so on, the last stage shift register may be electrically connected to the pixel circuits P1 of the pixel units P of the last row. In other alternative embodiments, the driving circuits 00 may also be located on different sides of the display area AA (not shown in the drawings), that is, by disposing the driving circuits 00 on both sides of the display area AA, a dual-sided driving effect is achieved for the pixel units P of the display area AA. When the driving circuit 00 is respectively located at two sides of the display area AA, the first stage shift registers at two sides of the display area AA may be electrically connected to the pixel circuits P1 of the first row of pixel units P, the second stage shift registers at two sides of the display area AA may be electrically connected to the pixel circuits P1 of the second row of pixel units P, and so on, the last stage shift registers at two sides of the display area AA may be electrically connected to the pixel circuits P1 of the last row of pixel units P. Or when the driving circuit 00 is respectively located at two sides of the display area AA, the first-stage shift register at one side of the display area AA is electrically connected with the pixel circuit P1 of the first-row pixel unit P, the first-stage shift register at the other side of the display area AA is electrically connected with the pixel circuit P1 of the second-row pixel unit P, the second-stage shift register at one side of the display area AA is electrically connected with the pixel circuit P1 of the third-row pixel unit P, the second-stage shift register at the other side of the display area AA is electrically connected with the pixel circuit P1 of the fourth-row pixel unit P, and the like, so that the driving effect on the pixel units P of the display area AA is realized by the driving circuits at different sides of the display area AA in a left-right alternating mode. The present embodiment is not described herein, and can be specifically understood by referring to the arrangement manner of the gate driving circuit in the related art.

When the driving circuit 00 of the present embodiment is configured to include a plurality of cascaded shift registers 01, the shift registers 01 at least include an input module 10, a control module 20 and an output module 30, and the module connection structure may be: the input module 10 is connected to at least the input signal terminal STV, the first clock signal line CK and the first node N1, and optionally, the input module 10 receives at least the input signal provided by the input signal terminal STV and the first clock signal provided by the first clock signal line CK to control the signal of the first node N1; the control end of the input module 10 is connected to the first clock signal line CK, the first end and the second end of the input module 10 are respectively connected to the input signal end STV and the first node N1, and the input module 10 can be turned on or turned off under the control of the first clock signal provided by the first clock signal line CK, so that the input signal provided by the input signal end STV of the first end of the input module 10 is transmitted to the second end of the input module 10 through the control of the first clock signal provided by the first clock signal line CK, and the potential signal of the first node N1 is controlled. It can be understood that the input module 10 of the first stage shift register 01 is at least connected to the input signal terminal STV, the input modules 10 of the other stages shift register 01 are at least connected to the input signal terminal IN, and the input signal terminal IN of the other stages shift register 01 is connected to the output signal terminal OUT of the previous stage shift register, so as to realize the shift control function of the driving circuit 00.

The control module 20 is connected to at least the first voltage signal line VGL, the second voltage signal line VGH, the first node N1, the second node N2 and the third node N3, and optionally, the control module 20 receives at least the first voltage signal provided by the first voltage signal line VGL, the second voltage signal provided by the second voltage signal line VGH, the signals of the first node N1 and the third node N3, and controls the signal of the second node N2; as shown in fig. 2, the first node N1 and the third node N3 may be directly connected, the control end of the control module 20 may be connected to the first node N1 (i.e., the third node N3), two first ends of the control module 20 may be respectively connected to the first voltage signal line VGL and the second voltage signal line VGH, and the second end of the control module 20 may be connected to the second node N2, where the control module 20 may be turned on or off under the control of the signal of the first node N1 (i.e., the third node N3), so that when the control module 20 is turned on, the first voltage signal provided by the first voltage signal line VGL and the second voltage signal provided by the second voltage signal line VGH connected to the first end of the control module 20 are transmitted to the second end of the control module 20 in a time-sharing manner to control the potential signal of the second node N2.

Alternatively, as shown in fig. 3, the first node N1 and the third node N3 may be connected through the first adjusting module 301, where the first adjusting module 301 may be a normally-on module, that is, two ends of the first adjusting module 301 remain on, and two control ends of the control module 20 may be connected to the first node N1 and the third node N3 respectively. The two first ends of the control module 20 may be connected to the first voltage signal line VGL and the second voltage signal line VGH, respectively, and the second end of the control module 20 may be connected to the second node N2, where the control module 20 may be turned on or off under the signal control of the first node N1, so as to transmit the second voltage signal provided by the second voltage signal line VGH connected to the first end of the control module 20 to the second end of the control module 20 when the control module 20 is turned on, and control the potential signal of the second node N2; the control module 20 may be turned on or off under the control of the signal of the third node N3, so that when the control module 20 is turned on, a first voltage signal provided by the first voltage signal line VGL connected to another first end of the control module 20 is transmitted to the second end of the control module 20 to control the potential signal of the second node N2. The potential signal of the second node N2 may be the first voltage signal or the second voltage signal.

The output module 40 includes a first output module 401 and a second output module 402, where the first output module 401 is at least connected to the first voltage signal line VGL, the third node N3, and the output signal terminal OUT, and optionally, the first output module 401 receives at least the first voltage signal provided by the first voltage signal line VGL and the signal of the third node N3, and controls the output signal of the output signal terminal OUT, and the first output module 401 may be turned on or off under the signal control of the third node N3 to control the potential signal of the output signal terminal OUT to be the first voltage signal through the first voltage signal provided by the first voltage signal line VGL. The second output module 402 is at least connected to the second voltage signal line VGH, the second node N2 and the output signal terminal OUT, and optionally, the second output module 402 receives at least the second voltage signal provided by the second voltage signal line VGH and the signal of the second node N2, and controls the output signal of the output signal terminal OUT. The second output module 402 may be turned on or off under the signal control of the second node N2 to control the potential signal of the output signal terminal OUT to be the second voltage signal through the second voltage signal line VGH.

In this embodiment, the first voltage signal provided by the first voltage signal line VGL and the second voltage signal provided by the second voltage signal line VGH may be different potential signals, and optionally, the first voltage signal provided by the first voltage signal line VGL may be a low level signal, and the second voltage signal provided by the second voltage signal line VGH may be a high level signal. The first output module 401 may be turned on or off under the signal control of the third node N3 to control the potential signal of the output signal terminal OUT to be a first voltage signal of a low level through the first voltage signal line VGL when the first output module 401 is turned on, and the second output module 402 may be turned on or off under the signal control of the second node N2 to control the potential signal of the output signal terminal OUT to be a second voltage signal of a high level through the second voltage signal line VGH when the second output module 402 is turned on.

The input module 10 of this embodiment transmits a start shift signal, i.e. an input signal, to each stage of shift register 01, and then, under the control of the control module 20, the first output module 401 and the second output module 402 are turned on in a time-sharing manner, so that the output signal of the output signal terminal OUT of each stage of shift register 01 of the driving circuit 00 includes a low-level signal and a high-level signal, respectively, and further, the output signal of the output signal terminal OUT is transmitted as a control signal to the pixel circuit P1 of the pixel unit P of the display area AA, so as to realize the driving control of the pixel circuit P1, and further, the light emitting display effect of each pixel unit P in the display panel 000 can be ensured.

Optionally, as shown in fig. 3, a control end of the first adjusting module 301 in this embodiment may be connected to the first voltage signal line VGL, where the first end and the second end of the first adjusting module 301 are respectively connected to the first node N1 and the third node N3, the first voltage signal provided by the first voltage signal line VGL may control the first end and the second end of the first adjusting module 301 to keep on, and the first node N1 and the third node N3 are connected through the first adjusting module 301, so that when the signal of the third node N3 controls the first output module 401 to be on, the potential of the third node N3 is not affected by the potential of the first node N1, so that the first output module 401 is ensured to be completely on under the control of the signal of the third node N3 as much as possible, and further the on effect of the first output module 401 may be stabilized, and the first output module 401 is ensured to transmit the output signal to the output signal terminal OUT.

It should be understood that, in the drawings of the present embodiment, only the block diagrams are used to illustrate the structures of the respective modules of the shift register 01 in the driving circuit 00, and in specific implementation, the electrical connection structures such as transistors and capacitors may be included in the respective modules of the shift register 01 according to actual requirements, and the present embodiment is not limited herein, and may be specifically understood with reference to the description of the following embodiments.

It should be noted that, in the drawings of the present embodiment, the structure of the display panel 000 is only illustrated as an example, and in the specific implementation, the structure of the display panel 000 includes, but is not limited to, but may also include other structures capable of realizing the display function, and the present embodiment is not described herein in detail.

In some alternative embodiments, please refer to fig. 1-3 and fig. 4 in combination, fig. 4 is another schematic block diagram of the shift register of fig. 1, in which the driving circuit 00 of the display panel 000 includes a plurality of shift registers 01 in cascade connection, and the control block 20 of each shift register 01 includes a first control block 201 and a second control block 202;

the first control module 201 is connected to at least the first voltage signal line VGL, the second node N2, and the third node N3;

The second control module 202 is connected to at least the second voltage signal line VGH, the first node N1 and the second node N2.

The present embodiment illustrates that the control module 20 includes a first control module 201 and a second control module 202, wherein a first end of the first control module 201 may be one of two first ends of the control module 20, a first end of the second control module 202 may be the other of two first ends of the control module 20, the first control module 201 is connected to at least a first voltage signal line VGL, a second node N2 and a third node N3, and optionally, the first control module 201 receives at least a first voltage signal provided by the first voltage signal line VGL and a signal of the third node N3, and controls a signal of the second node N2; the control end of the first control module 201 is connected to the third node N3, the first end of the first control module 201 is connected to the first voltage signal line VGL, the second end of the first control module 201 is connected to the second node N2, under the signal control of the third node N3, the first end and the second end of the first control module 201 are conducted, the first voltage signal provided by the first voltage signal line VGL can be transmitted to the second node N2, and the potential of the second node N2 is controlled to be the first voltage signal. The second control module 202 is at least connected to the second voltage signal line VGH, the first node N1 and the second node N2, and optionally, the second control module 202 receives at least a second voltage signal provided by the second voltage signal line VGH and a signal of the first node N1, and controls a signal of the second node N2, a control end of the second control module 202 is connected to the first node N1, a first end of the second control module 202 is connected to the second voltage signal line VGH, a second end of the second control module 202 is connected to the second node N2, and under the signal control of the first node N1, the first end and the second end of the second control module 202 are turned on, and the second voltage signal provided by the second voltage signal line VGH can be transmitted to the second node N2, so as to control a potential of the second node N2 to be the second voltage signal.

It can be appreciated that the control terminal of the first control module 201 in this embodiment is connected to the third node N3, so that whether the first terminal of the first control module 201 is conductive with the second terminal (i.e. whether the first voltage signal provided by the first voltage signal line VGL is transmitted to the second node N2) is controlled by the signal of the third node N3. The control terminal of the second control module 202 is connected to the first node N1, so that whether the first terminal and the second terminal of the second control module 202 are conductive (i.e. whether the second voltage signal provided by the second voltage signal line VGH is transmitted to the second node N2) is controlled by the signal of the first node N1.

Optionally, as shown in fig. 4, in this embodiment, when the signal of the third node N3 controls the first control module 201 to be turned on, the signal of the first node N1 controls the second control module 202 to be turned off; or, when the signal of the third node N3 controls the first control module 201 to be turned off, the signal of the first node N1 controls the second control module 202 to be turned on. That is, when the signal of the third node N3 controls the first end and the second end of the first control module 201 to be turned on, and the first voltage signal provided by the first voltage signal line VGL may be transmitted to the second node N2, the signal of the first node N1 controls the second control module 202 to be turned off, the first end and the second end of the second control module 202 are not turned on, the second voltage signal provided by the second voltage signal line VGH may not be transmitted to the second node N2, at this time, the signal of the third node N3 controls the first end and the second end of the first output module 401 to be not turned on, the first voltage signal provided by the first voltage signal line VGL may not be transmitted to the output signal end OUT, so that the first end and the second end of the first control module 201 may be controlled by the signal of the third node N3, the first voltage signal of the low level signal provided by the first voltage signal line VGL may be transmitted to the second node N2, the first end and the second end of the second output module 402 may be turned on, and the high level second voltage signal provided by the second voltage signal line VGH may be transmitted to the second end OUT of the second output signal register 01. When the signal of the third node N3 controls the first end and the second end of the first control module 201 to be turned off and not turned on, the first voltage signal provided by the first voltage signal line VGL cannot be transmitted to the second node N2, the signal of the first node N1 controls the conduction between the first end and the second end of the second control module 202, the second voltage signal provided by the second voltage signal line VGH can be transmitted to the second node N2, so that the first end and the second end of the second control module 202 can be controlled to be turned on by the signal of the first node N1, the second voltage signal of the high level signal provided by the second voltage signal line VGH can be transmitted to the second node N2, so that the first end and the second end of the second output module 402 cannot be turned on, the signal of the high level provided by the second voltage signal line VGH cannot be transmitted to the output signal end OUT, and when the signal of the third node N3 controls the first control module 201 to be turned off, and when the first end and the second end of the first control module 201 are not turned on, the signal of the third node N3 can control the first end and the first end of the second control module 202 to be turned on, and the second end of the first node N3 can be turned off, and the signal of the first output module 401 can be turned on, and the first end of the first output signal can be turned off, and the high level signal can be output by the first end of the first signal output from the first end of the first output module can be turned off, and high signal and high level 01 can be turned off.

In this embodiment, by the arrangement that the first control module 201 and the second control module 202 are not turned on simultaneously, when the first control module 201 is turned on and the second control module 202 is turned off, the output signal of the output signal terminal OUT is a high-level second voltage signal, and when the first control module 201 is turned off and the second control module 202 is turned on, the output signal of the output signal terminal OUT is a low-level first voltage signal, so that the output signal of the output signal terminal OUT of each stage of shift register 01 of the driving circuit 00 respectively includes a low-level signal and a high-level signal by the first control module 201 and the second control module 202 with simple structures, and the output signal of the output signal terminal OUT is further transmitted to the pixel circuit P1 of the pixel unit P of the display area AA as a control signal, so as to realize driving control of the pixel circuit P1, and further ensure the light emitting display effect of each pixel unit P in the display panel 000.

It should be understood that, in fig. 4 of the present embodiment, the first node N1 and the third node N3 are connected by the first adjusting module 301 as an example, and in the implementation, when the first node N1 and the third node N3 are directly connected (as shown in fig. 5, fig. 5 is another schematic diagram of module connection of the shift register in fig. 1), the control module 20 may also be a structure including the first control module 201 and the second control module 202, which only needs to satisfy that the first control module 201 and the second control module 202 in the present embodiment are not turned on at the same time.

Alternatively, as shown in fig. 1, fig. 4, fig. 5, fig. 6, and fig. 7, fig. 6 is a schematic circuit connection structure of the shift register in fig. 4, fig. 7 is a schematic circuit connection structure of the shift register in fig. 5 (the first node N1 and the third node N3 in fig. 6 are connected through the first adjustment module 301, and the first node N1 and the third node N3 in fig. 7 are directly connected), in this embodiment, the first control module 201 includes a first transistor M1, and the second control module 202 includes a second transistor M2;

a first terminal of the first transistor M1 (may be a drain of the first transistor M1) is connected to the first voltage signal line VGL, a second terminal of the first transistor M1 (may be a source of the first transistor M1) is connected to the second node N2, and a control terminal of the first transistor M1 (may be a gate of the first transistor M1) is connected to the third node N3; or,

a first terminal of the second transistor M2 (may be a source of the second transistor M2) is connected to the second voltage signal line VGH, a second terminal of the second transistor M2 (may be a drain of the second transistor M2) is connected to the second node N2, and a control terminal of the second transistor M2 (may be a gate of the second transistor M2) is connected to the first node N1; or,

a first terminal of the first transistor M1 (may be a drain of the first transistor M1) is connected to the first voltage signal line VGL, a second terminal of the first transistor M1 (may be a source of the first transistor M1) is connected to the second node N2, and a control terminal of the first transistor M1 (may be a gate of the first transistor M1) is connected to the third node N3; and the first end (may be the source of the second transistor M2) of the second transistor M2 is connected to the second voltage signal line VGH, the second end (may be the drain of the second transistor M2) of the second transistor M2 is connected to the second node N2, and the control end (may be the gate of the second transistor M2) of the second transistor M2 is connected to the first node N1.

The embodiment illustrates that the control module 20 includes only two transistors, the first control module 201 includes the first transistor M1, and the second control module 202 includes the second transistor M2, so that the number of transistors included in the control module 20 in the circuit of the shift register 01 is greatly reduced, and further when the driving circuit 00 including the plurality of cascaded shift registers 01 of the embodiment is manufactured in the non-display area NA of the display panel 000, the number of transistors included in the control module 20 is greatly reduced, so that the total number of transistors included in the driving circuit 00 is greatly reduced, and further the space occupied by the driving circuit 00 in the non-display area NA is greatly reduced, which is beneficial to further reducing the frame width and realizing the narrower frame effect of the display panel 000.

When the control module 20 in this embodiment works, the signal of the third node N3 controls the first transistor M1 to be turned on, and the signal of the first node N1 controls the second transistor M2 to be turned off; or, when the signal of the third node N3 controls the first transistor M1 to be turned off, the signal of the first node N1 controls the second transistor M2 to be turned on, so that the first transistor M1 and the second transistor M2 are not turned on at the same time, but turned on in a time-sharing manner, when the output signal terminal OUT needs to output the second voltage signal with high potential, the first transistor M1 may be set to be turned on, the second transistor M2 is turned off, at this time, the first voltage signal is transmitted to the second node N2 due to the conduction of the first transistor M1, the signal of the second node N2 controls the second output module 420 to be turned on, and the second voltage signal is transmitted to the output signal terminal OUT through the second output module 420. When the output signal terminal OUT needs to output the low-potential first voltage signal, the second transistor M2 may be set to be turned on, the first transistor M1 may be turned off, at this time, the second voltage signal is transmitted to the second node N2 through the on of the second transistor M2, the signal of the second node N2 controls the second output module 420 to be turned off, the signal of the third node N3 controls the first transistor M1 to be turned off, but the signal of the third node N3 may control the first output module 401 to be turned on, and the first voltage signal is transmitted to the output signal terminal OUT through the first output module 401.

The circuit structure of the two transistors included in the control module 20 of the embodiment can realize that the output signals of the output signal terminals OUT of the shift registers 01 of each stage of the driving circuit 00 respectively include a low-level signal and a high-level signal, and further transmit the output signals of the output signal terminals OUT as control signals to the pixel circuits P1 of the pixel units P of the display area AA, so that the number of transistors of the control module 20 can be greatly reduced while driving control of the pixel circuits P1 is realized, and a narrower frame effect of the display panel 000 is ensured.

Alternatively, as shown in fig. 1, 5, 7, 8 and 9, fig. 8 is a schematic diagram of another circuit connection structure of the shift register in fig. 5, and fig. 9 is a schematic diagram of another circuit connection structure of the shift register in fig. 5, in this embodiment, the first control module 201 includes a first transistor M1, the second control module 202 includes a second transistor M2, the first output module 401 includes a third transistor M3, and the second output module 402 includes a fourth transistor M4; the input module 10 may include a fifth transistor M5, and the first node N1 and the third node N3 may be directly connected.

The first transistor M1 and the second transistor M2 in the present embodiment are different in channel region type, i.e., the first transistor M1 is an N-type channel transistor, and the second transistor M2 is a P-type channel transistor (as shown in fig. 8); alternatively, the first transistor M1 is a P-channel transistor, and the second transistor M2 is an N-channel transistor (as shown in fig. 9). At this time, other transistors in the shift register 01, such as the third transistor M3, the fourth transistor M4, and the fifth transistor M5, may be of the same type as the second transistor M2.

In the circuit structure of the shift register 01 provided in this embodiment, the first end (may be the drain of the first transistor M1) of the first transistor M1 is connected to the first voltage signal line VGL, the second end (may be the source of the first transistor M1) of the first transistor M1 is connected to the second node N2, and the control end (may be the gate of the first transistor M1) of the first transistor M1 is connected to the third node N3. The first terminal of the second transistor M2 (may be the source of the second transistor M2) is connected to the second voltage signal line VGH, the second terminal of the second transistor M2 (may be the drain of the second transistor M2) is connected to the second node N2, and the control terminal of the second transistor M2 is connected to the first node N1. The first terminal (may be the drain of the third transistor M3) of the third transistor M3 is connected to the first voltage signal line VGL, the second terminal (may be the source of the third transistor M3) of the third transistor M3 is connected to the output signal terminal OUT, and the control terminal (may be the gate of the third transistor M3) of the third transistor M3 is connected to the third node N3. The first end of the fourth transistor M4 is connected to the second voltage signal line VGH (may be the source of the fourth transistor M4), the second end of the fourth transistor M4 (may be the drain of the fourth transistor M4) is connected to the output signal terminal OUT, and the control end of the fourth transistor M4 (may be the gate of the fourth transistor M4) is connected to the second node N2. The first terminal (may be the source of the fifth transistor M5) of the fifth transistor M5 is connected to the input signal terminal STV, the second terminal (may be the drain of the fifth transistor M5) of the fifth transistor M5 is connected to the first node N1, and the control terminal (may be the gate of the fifth transistor M5) of the fifth transistor M5 is connected to the first clock signal line CK.

Further optionally, the first output module 401 includes a first latch module 4011, and the first latch module 4011 is connected between the third node N3 and the output signal terminal OUT; the first latch module 4011 comprises a first capacitor C1, a first polar plate of the first capacitor C1 is connected to the third node N3, and a second polar plate of the first capacitor C1 is connected to the output signal terminal OUT; and/or, the second output module 402 includes a second latch module 4021, the second latch module 4021 is connected between the second node N2 and the second voltage signal line VGH; the second latch module 4021 includes a second capacitor C2, a first plate of the second capacitor C2 is connected to the second node N2, and a second plate of the second capacitor C2 is connected to the second voltage signal line VGH. The first latch module 4011 including the first capacitor C1 and the second latch module 4021 including the second capacitor C2 of the present embodiment can function as a latch voltage, a stabilizing potential.

Alternatively, please refer to fig. 8 and 10 in combination, fig. 10 is a timing diagram of the shift register circuit in fig. 8, taking the circuit structure of the shift register 01 shown in fig. 8 as an example, the shift register 01 works:

in the first period t1, as shown in fig. 10 and 11, fig. 11 is a conducting state diagram of the transistor in the circuit structure in fig. 8 in the first period (the "x" is shown on the transistor in the diagram to indicate that the transistor is not conducting, and any sign is not shown to indicate that the transistor is conducting), the input signal of the input signal terminal STV is at a low level, the first clock signal provided by the first clock signal line CK is at a low level, the fifth transistor M5 is conducting, the first node N1 and the third node N3 are both low level signals, the second transistor M2 is conducting, the third transistor M3 is conducting, the first transistor M1 is off, the high level second voltage signal transmitted by the second voltage signal line VGH is transmitted to the second node N2, the fourth transistor M4 is off, and the low level first voltage signal transmitted by the first voltage signal line VGL is transmitted to the output signal terminal OUT, so that the output signal of the output signal terminal OUT is at a low level signal.

In the second period t2, as shown in fig. 10 and 12, fig. 12 is a diagram of the on state of the transistor in the circuit structure in fig. 8 in the second period (the "x" in the diagram indicates that the transistor is not on, and no sign indicates that the transistor is on), the input signal of the input signal terminal STV is at a high level, the first clock signal provided by the first clock signal line CK is at a high level, the fifth transistor M5 is turned off, the first node N1 and the third node N3 remain at a low level due to the latch voltage of the first capacitor C1, the second transistor M2 remains on, the third transistor M3 remains on, the first transistor M1 remains off, the high-level second voltage signal transmitted by the second voltage signal line VGH is transmitted to the second node N2, the fourth transistor M4 remains off, the low-level first voltage signal transmitted by the first voltage signal line l is transmitted to the output signal terminal OUT, and the output signal of the output signal terminal OUT remains at a low level signal. The second capacitor C2 can stabilize the potential of the second node N2 to be a high level signal, so as to ensure that the fourth transistor M4 is continuously turned off, and avoid the influence of the transmission of the high level second voltage signal to the output signal terminal OUT on the output low level signal.

In the third period t3, as shown in fig. 10 and 13, fig. 13 is a conducting state diagram of the transistor in the circuit structure in fig. 8 in the third period (in the drawing, the "x" indicates that the transistor is not conducting, and no sign indicates that the transistor is conducting), the input signal of the input signal terminal STV is at a high level, the first clock signal provided by the first clock signal line CK is at a low level, the fifth transistor M5 is conducting, the first node N1 and the third node N3 are both high level signals, the second transistor M2 is turned off, the third transistor M3 is turned off, the first transistor M1 is turned on, the low level first voltage signal transmitted by the first voltage signal line VGL is transmitted to the second node N2, the fourth transistor M4 is turned on, and the high level second voltage signal transmitted by the second voltage signal line VGH is transmitted to the output signal terminal OUT, so that the output signal of the output signal terminal OUT is a high level signal.

In the fourth period t4, as shown in fig. 10 and 14, fig. 14 is a diagram of the circuit structure in fig. 8 in the on state of the transistor in the fourth period (the "x" in the diagram indicates that the transistor is not on, and any sign indicates that the transistor is on), the input signal of the input signal terminal STV is at a high level, the first clock signal provided by the first clock signal line CK is at a high level, the fifth transistor M5 is turned off, the first node N1 and the third node N3 remain at a high level due to the latch voltage of the first capacitor C1, the second transistor M2 remains turned off, the third transistor M3 remains turned on, the first transistor M1 remains turned on, the first voltage signal at a low level transmitted by the first voltage signal line VGL is transmitted to the second node N2, the fourth transistor M4 is turned on, the second voltage signal at a high level transmitted by the second voltage signal line h is transmitted to the output signal terminal OUT, and the output signal of the output signal terminal OUT remains at a high level.

In the fifth period t5, as shown in fig. 10 and 11, referring to fig. 11, in the on-state diagram of the transistor in the fifth period in the circuit structure of fig. 8, the input signal of the input signal line STV is at a low level, the first clock signal provided by the first clock signal line CK is at a low level, the fifth transistor M5 is turned on, the input signal of the input signal line STV is written into the first node N1, the first node N1 and the third node N3 are both low level signals, the second transistor M2 is turned on, the third transistor M3 is turned on, the first transistor M1 is turned off, the high level second voltage signal transmitted by the second voltage signal line VGH is transmitted to the second node N2, the fourth transistor M4 is turned off, and the low level first voltage signal transmitted by the first voltage signal line VGL is transmitted to the output signal terminal OUT, so that the output signal of the output signal terminal OUT is a low level signal.

In the prior art, if the first capacitor C1 is not provided between the third node N3 and the output signal terminal OUT, when the input signal of the input signal terminal STV jumps from high level to low level and the first clock signal provided by the first clock signal line CK is low level, the third node N3 is written low to V _VGL ++ vth|, where Vth is the threshold voltage of the third transistor M3, V _VGL The third transistor M3 is turned on for the voltage of the low-level first voltage signal transmitted by the first voltage signal line VGL, and the output signal terminal OUT is written low when it is written low to V _N3 +|Vth| (i.e. V _VGL +2|vth|), the operating state of the third transistor M3 changes from the saturation region to the off region (the condition that the P-type transistor enters the off region is Vg-Vs > Vth, when the potential of the output signal terminal OUT, i.e., the source potential Vs of the third transistor M3 is written low to V _VGL +2|Vth|, where Vg-Vs > Vth of the gate potential of the third transistor M3, the third transistor M3 enters the off-region), so the potential of the output signal terminal OUT cannot be written low continuously, and the potential of the output signal terminal OUT is likely to be maintained at V _VGL +2|Vth|The waveform tail, i.e., the step, of the output signal terminal OUT is caused, and the output signal of the shift register 01 is further unstable. As illustrated in fig. 15 for a fifth period t5' (fig. 15 is a timing waveform diagram of the prior art in which the first capacitor is not provided between the third node N3 and the output signal terminal OUT), if the first capacitor C1 is not provided between the third node N3 and the output signal terminal OUT, when the input signal of the input signal terminal STV jumps from the high level to the low level and the first clock signal provided by the first clock signal line CK is the low level, there is a tail in the waveform of the output signal terminal OUT.

In order to solve the problem, the circuit structure of the present embodiment sets the first capacitor C1 between the third node N3 and the output signal terminal OUT, when the input signal of the input signal terminal STV jumps from high level to low level and the first clock signal provided by the first clock signal line CK is low level, the potential of the output signal terminal OUT is pulled down, and due to the coupling effect of the first capacitor C1, the potential of the output signal terminal OUT becomes low, the first capacitor C1 can couple the third node N3 to negative potential, so that the potential of the third node N3 is coupled to be lower than V _VGL - |vth| such that, as the potential of the output signal terminal OUT is pulled down, the third transistor M3 cannot meet the condition of entering the cut-off region, so as to ensure the on stability of the third transistor M3, then in the fifth period t5, the first voltage signal of the first voltage signal line VGL is directly transmitted to the output signal terminal OUT through the third transistor M3, the potential of the output signal terminal OUT can be directly pulled down to the first voltage signal of the low level, so as to avoid the problem of waveform tailing of the output signal terminal OUT when the input signal of the input signal terminal STV is jumped from the high level to the low level, and the first clock signal provided by the first clock signal line CK is of the low level (such that the waveform of the output signal terminal OUT is directly pulled down in the fifth period t5 shown in fig. 10, so that the output signal of the shift register 01 is more stable, so as to further facilitate ensuring the display effect of the display panel 000.

The circuit structure of the shift register 01 provided in this embodiment not only can ensure the shift register function of the shift register 01, but also can simplify the circuit while providing control signals for the pixel circuit P1 of the display area AA, so that the number of transistors in the driving circuit 00 is reduced as much as possible, which is more beneficial to the design of a narrow frame, and the design of the first capacitor C1 of the first latch module is beneficial to the further guarantee of the display effect of the display panel 000, so that the output signal of the shift register 01 is more stable, the tailing problem of the output signal is improved, and further the display effect of the display panel 000 is beneficial to further guarantee.

Alternatively, as shown in fig. 1, 4, 6 and 16 and 17, fig. 16 is a schematic diagram of another circuit connection structure of the shift register in fig. 4, and fig. 17 is a schematic diagram of another circuit connection structure of the shift register in fig. 4, in this embodiment, the first control module 201 includes a first transistor M1, the second control module 202 includes a second transistor M2, the first output module 401 includes a third transistor M3, and the second output module 402 includes a fourth transistor M4; the input module 10 may include a fifth transistor M5, and the first node N1 and the third node N3 may be connected through the first adjustment module 301. The first adjustment module 301 may include a seventh transistor M7. The first node N1 and the third node N3 are connected through a first adjusting module 301, and the first adjusting module 301 is connected to at least the first node N1, the third node N3, and the first voltage signal line VGL. The first adjusting module 301 receives at least the signal of the first node N1 and the first voltage signal provided by the first voltage signal line VGL, and controls the signal of the third node N3.

The first transistor M1 and the second transistor M2 in the present embodiment are different in channel region type, i.e., the first transistor M1 is an N-type channel transistor, and the second transistor M2 is a P-type channel transistor (as shown in fig. 16); alternatively, the first transistor M1 is a P-channel transistor, and the second transistor M2 is an N-channel transistor (as shown in fig. 17). At this time, other transistors in the shift register 01, such as the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the seventh transistor M7, may be of the same type as the second transistor M2.

In the circuit structure of the shift register 01 provided in this embodiment, the first end (may be the source of the seventh transistor M7) of the seventh transistor M7 is connected to the first node N1, the second end (may be the drain of the seventh transistor M7) of the seventh transistor M7 is connected to the third node N3, and the control end (may be the gate of the seventh transistor M7) of the seventh transistor M7 is connected to the first voltage signal line VGL. The seventh transistor M7 receives at least the signal of the first node N1 and the first voltage signal supplied from the first voltage signal line VGL, and controls the signal of the third node N3.

Alternatively, please refer to fig. 16 and fig. 10 in combination, the timing diagram of the shift register circuit in fig. 16 may refer to fig. 10, taking the circuit structure of the shift register 01 shown in fig. 16 as an example, and the shift register 01 works when:

As shown in fig. 10, 16 and 18, in the first period t1, fig. 18 is a conductive state diagram of the transistor in the first period (the schematic "x" on the transistor in the drawing indicates that the transistor is not conductive, and any sign indicates that the transistor is conductive), and the seventh transistor M7 remains conductive under the first voltage signal supplied from the first voltage signal line VGL in the circuit configuration in fig. 16. The input signal of the input signal terminal STV is at a low level, the first clock signal provided by the first clock signal line CK is at a low level, the fifth transistor M5 is turned on, the first node N1 and the third node N3 are both at a low level, the second transistor M2 is turned on, the third transistor M3 is turned on, the first transistor M1 is turned off, the second voltage signal at a high level transmitted by the second voltage signal line VGH is transmitted to the second node N2, the fourth transistor M4 is turned off, the first voltage signal at a low level transmitted by the first voltage signal line VGL is transmitted to the output signal terminal OUT, and the output signal of the output signal terminal OUT is at a low level.

As shown in fig. 10, 16 and 19, in the second period t2, fig. 19 is a conductive state diagram of the transistor in the circuit structure in fig. 16 in the second period (the schematic "x" on the transistor in the drawing indicates that the transistor is not conductive, and any sign indicates that the transistor is conductive), and the seventh transistor M7 remains conductive under the first voltage signal supplied from the first voltage signal line VGL. The input signal of the input signal terminal STV is at a high level, the first clock signal provided by the first clock signal line CK is at a high level, the fifth transistor M5 is turned off, the third node N3 remains at a low level due to the latch voltage of the first capacitor C1, the first node N1 remains at a low level due to the turn-on of the seventh transistor M7, the second transistor M2 remains on, the third transistor M3 remains on, the first transistor M1 remains off, the high-level second voltage signal transmitted by the second voltage signal line VGH is transmitted to the second node N2, the fourth transistor M4 remains off, and the low-level first voltage signal transmitted by the first voltage signal line VGL is transmitted to the output signal terminal OUT, so that the output signal of the output signal terminal OUT remains at a low level signal. The second capacitor C2 stabilizes the potential of the second node N2 to be a high-level signal, so as to ensure that the fourth transistor M4 is continuously turned off, and avoid the influence of the transmission of the high-level second voltage signal to the output signal terminal OUT on the output low-level signal. In addition, the seventh transistor M7 is set in this embodiment, the potential of the third node N3 may be as low as possible, and since the potential of the first node N1 may reach the first voltage signal as low as possible, but in order to ensure complete turn-on of the third transistor M3, the potential of the third node N3 needs to be pulled down to be much lower than the value of the first voltage signal at the drain of the third transistor M3, so the seventh transistor M7 of the first adjusting module 301 is set in this embodiment, so that the low potential of the third node N3 is not affected by the potential of the first node N1, the low potential of the third node N3 may be pulled down as low as possible, and further, the turn-on effect of the third transistor M3 is ensured, so that the third transistor M3 is fully turned on, and the output signal of the output signal terminal OUT remains the first voltage signal of the low level signal.

As shown in fig. 10, 16 and 20, in the third period t3, fig. 20 is a conductive state diagram of the transistor in the third period (the schematic "x" on the transistor in the drawing indicates that the transistor is not conductive, and any sign indicates that the transistor is conductive), and the seventh transistor M7 remains conductive under the first voltage signal supplied from the first voltage signal line VGL in the circuit configuration in fig. 16. The input signal of the input signal terminal STV is at a high level, the first clock signal provided by the first clock signal line CK is at a low level, the fifth transistor M5 is turned on, the first node N1 and the third node N3 are both at a high level, the second transistor M2 is turned off, the third transistor M3 is turned off, the first transistor M1 is turned on, the first voltage signal at a low level transmitted by the first voltage signal line VGL is transmitted to the second node N2, the fourth transistor M4 is turned on, the second voltage signal at a high level transmitted by the second voltage signal line VGH is transmitted to the output signal terminal OUT, and the output signal of the output signal terminal OUT is made to be at a high level.

As shown in fig. 10, 16 and 21, in the fourth period t4, fig. 21 is a conductive state diagram of the transistor in the fourth period (in the drawing, the "x" is indicated by the "no sign indicating that the transistor is conductive on the transistor), and the seventh transistor M7 is kept conductive under the first voltage signal supplied from the first voltage signal line VGL in the circuit configuration in fig. 16. The input signal of the input signal terminal STV is at a high level, the first clock signal provided by the first clock signal line CK is at a high level, the fifth transistor M5 is turned off, the first node N1 and the third node N3 remain at a high level signal due to the latch voltage of the first capacitor C1, the second transistor M2 remains turned off, the third transistor M3 remains turned off, the first transistor M1 remains turned on, the first voltage signal at a low level transmitted by the first voltage signal line VGL is transmitted to the second node N2, the fourth transistor M4 is turned on, the second voltage signal at a high level transmitted by the second voltage signal line VGH is transmitted to the output signal terminal OUT, and the output signal of the output signal terminal OUT remains at a high level signal.

In the fifth period t5, as shown in fig. 10 and 18, referring to fig. 18, the on-state diagram of the transistor in the circuit structure in fig. 16 in the fifth period may refer to fig. 18, and the seventh transistor M7 may remain on under the first voltage signal provided by the first voltage signal line VGL. The input signal of the input signal terminal STV is at a low level, the first clock signal provided by the first clock signal line CK is at a low level, the fifth transistor M5 is turned on, the input signal of the input signal terminal STV is written into the third node N3, the first node N1 and the third node N3 are both low level signals, the second transistor M2 is turned on, the third transistor M3 is turned on, the first transistor M1 is turned off, the second voltage signal at a high level transmitted by the second voltage signal line VGH is transmitted to the second node N2, the fourth transistor M4 is turned off, the first voltage signal at a low level transmitted by the first voltage signal line VGL is transmitted to the output signal terminal OUT, and the output signal of the output signal terminal OUT is a low level signal.

The circuit structure of this embodiment sets the first capacitor C1 between the third node N3 and the output signal terminal OUT, when the input signal of the input signal terminal STV jumps from high level to low level and the first clock signal provided by the first clock signal line CK is low level, the potential of the output signal terminal OUT is pulled down, and due to the coupling effect of the first capacitor C1, the potential of the output signal terminal OUT becomes low, and the first capacitor C1 can couple the third node N3 to negative potential direction, so that the potential of the third node N3 is lower than V _VGL In the fifth period t5, the first voltage signal of the first voltage signal line VGL is directly and stably transmitted to the output signal terminal OUT through the third transistor M3, the potential of the output signal terminal OUT is directly pulled down to the first voltage signal of the low level, so that the jump of the input signal terminal STV from the high level to the low level can be avoided, and when the first clock signal provided by the first clock signal line CK is of the low level, the problem of waveform tailing of the output signal terminal OUT is solved (as in the fifth period t5 shown in fig. 10, the waveform of the output signal terminal OUT is directly pulled down, and the problem of tailing does not exist), so that the output signal of the shift register 01 is more stable, thereby being beneficial to further ensuring the display effect of the display panel 000.

The circuit structure of the shift register 01 provided in this embodiment not only can ensure the shift register function of the shift register 01, but also can simplify the circuit while providing control signals for the pixel circuits of the display area AA, so that the number of transistors in the driving circuit 00 is reduced as much as possible, which is more beneficial to the design of a narrow frame, and the design of the first capacitor C1 of the first latch module is also beneficial to further ensuring the display effect of the display panel 000, so that the output signals of the shift register 01 are more stable.

Alternatively, in order to make the first transistor M1 and the second transistor M2 not be turned on at the same time in the present embodiment, when the output signal terminal OUT needs to output the second voltage signal with a high potential, the first transistor M1 may be set to be turned on and the second transistor M2 may be set to be turned off. When the output signal terminal OUT needs to output a low-potential first voltage signal, the second transistor M2 may be set on, the first transistor M1 is set off, and the control module 20 includes circuit structures of the first transistor M1 and the second transistor M2 with different types, so that the output signal of the output signal terminal OUT of each stage of the shift register 01 of the driving circuit 00 may include a low-level signal and a high-level signal, and further, the output signal of the output signal terminal OUT is transmitted as a control signal to the pixel circuit P1 of the pixel unit P of the display area AA, so that the driving control of the pixel circuit P1 is realized, and meanwhile, the number of transistors of the control module 20 may be greatly reduced, so as to ensure a narrower frame effect of the display panel 000.

In this embodiment, the types of the first transistor M1 and the second transistor M2 are set to be different, and besides the first transistor M1 and the second transistor M2 are respectively N-type and P-type transistors, the active layer of the first transistor M1 may also be selected to include silicon, and the active layer of the second transistor M2 may include an oxide semiconductor; alternatively, the active layer of the first transistor M1 includes an oxide semiconductor, and the active layer of the second transistor M2 includes silicon, that is, a material of the active layer of the first transistor M1 and a material of the active layer of the second transistor M2 are provided differently.

The active layer of one of the first transistor M1 and the second transistor M2 includes silicon, and the active layer of the other one includes an oxide semiconductor, i.e., one of the first transistor M1 and the second transistor M2 is a silicon transistor, and the silicon may be polysilicon deposited by a low temperature method, i.e., LTPS (Low Temperature Poly-silicon) or low temperature polysilicon, and the other one of the first transistor M1 and the second transistor M2 is an oxide semiconductor transistor, an oxide semiconductor material such as amorphous indium gallium zinc oxide, i.e., IGZO (Indium Gallium Zinc Oxide). Since the types of other transistors in the circuit structure of the shift register 01 are the same as the types of the second transistor M2, the first transistor M1 may be an N-type IGZO transistor, and the second transistor M2 and the other transistors in the circuit structure are P-type LTPS transistors, so that most of the transistors in the circuit structure may be silicon transistors easy to manufacture, which is beneficial to improving the processing efficiency. And most of transistors in the circuit structure are all arranged to be silicon transistors which are easy to manufacture, and as the silicon transistors have higher carrier migration rate compared with the oxide semiconductor transistors and are not sensitive to the oxide semiconductor transistors such as hydrogen elements, water oxygen and the like in the external environment, the signal transmission stability of the whole circuit structure can be well ensured. The embodiment utilizes the characteristics and advantages of the silicon transistor and the oxide semiconductor transistor, ensures the stability and normal operation of the transistor, and is also beneficial to improving the display quality of the display panel 000, so that the display effect is more superior and the product has more competitive advantage.

In some alternative embodiments, please refer to fig. 1, 8, 16 and 22 in combination, fig. 22 is a schematic view of a partial cross-section of the first transistor and the second transistor in fig. 8 and 16 formed on a substrate, in which the display panel 000 includes a substrate 001, and the driving circuit 00 is formed on the substrate 001;

the first transistor M1 includes a first gate electrode M1G1, a first active layer M1N, a first source electrode M1S, and a second drain electrode M1D;

the second transistor M2 includes a second gate electrode M2G1, a second active layer M2P, a second source electrode M2S, and a second drain electrode M2D;

the first active layer M1N includes silicon, and the second active layer M2P includes an oxide semiconductor (i.e., the first transistor M1 may be an N-type silicon transistor, and the second transistor M2 may be a P-type oxide semiconductor transistor); alternatively, the first active layer M1N may include an oxide semiconductor, and the second active layer M2P may include silicon (i.e., the first transistor M1 may be an N-type oxide semiconductor transistor, and the second transistor M2 may be a P-type silicon transistor). In fig. 22 of the present embodiment, an oxide semiconductor transistor in which the first transistor M1 may be an N-type transistor and a silicon transistor in which the second transistor M2 may be a P-type transistor are exemplified. When the materials of the first active layer M1N and the second active layer M2P are different, the first active layer M1N and the second active layer M2P are located at different film layers. The first active layer M1N may be located at a side of the second active layer M2P remote from the substrate 001.

Alternatively, referring to fig. 1, 8, 16 and 23 in combination, fig. 23 is a schematic view showing another partial cross-sectional structure of the first transistor and the second transistor in fig. 8 and 16 formed on a substrate, in which the display panel 000 includes a substrate 001 and the driving circuit 00 is formed on the substrate 001;

the first transistor M1 further includes a third gate M1G2, the first gate M1G1 and the third gate M1G2 are respectively located at two sides of the first active layer M1N, and the first active layer M1N includes an oxide semiconductor; or,

the second transistor M2 further includes a fourth gate M2G2, the second gate M2G1 and the fourth gate M2G2 are respectively located at two sides of the second active layer M2P, and the second active layer M2P includes an oxide semiconductor.

In the driving circuit 00 of the display panel 000, at least one of the first transistor M1 and the second transistor M2 included in the control module 20 is an N-type transistor, and the other is a P-type transistor, but the first active layer M1N of the first transistor M1 includes an oxide semiconductor, and the second active layer M2P of the second transistor M2 includes an oxide semiconductor, i.e., the first transistor M1 and the second transistor M2 are both oxide semiconductor transistors. At this time, the first transistor M1 and the second transistor M2 may be dual-gate transistors, where the first transistor M1 further includes a third gate M1G2, and the first gate M1G1 and the third gate M1G2 are respectively located at two sides of the first active layer M1N along a direction Z perpendicular to a plane where the substrate 001 is located; the second transistor M2 further includes a fourth gate M2G2, and the second gate M2G1 and the fourth gate M2G2 are respectively located at two sides of the second active layer M2P along a direction Z perpendicular to the plane of the substrate 001.

In this embodiment, the first transistor M1 and the second transistor M2 are oxide semiconductor transistors with dual gate structures, the active layer of the oxide semiconductor may be indium gallium zinc oxide, the induced charges generated by the electric potentials of the two gates of the oxide semiconductor transistors with dual gate structures may extend to the active layer of the indium gallium zinc oxide of the oxide semiconductor transistors with dual gate structures, and the whole area of the active layer of the indium gallium zinc oxide in the thickness direction thereof (because the two gates of the dual gate transistors overlap on the upper and lower surfaces of the active portions of the two gates of the dual gate transistors), the carrier concentration in the first transistor M1 and the second transistor M2 with dual gate structures may be increased, thereby effectively improving the carrier mobility of the first transistor M1 and the second transistor M2, and being beneficial to improving the driving capability of the first transistor M1 and the second transistor M2. The first transistor M1 includes a first gate electrode M1G1 and a third gate electrode M1G2, and optionally, the third gate electrode M1G2 may be located at a side of the first active layer M1N close to the substrate 001. The second transistor M2 includes a second gate electrode M2G1 and a fourth gate electrode M2G2, and optionally, the fourth gate electrode M2G2 may be located at a side of the second active layer M2P close to the substrate 001. The first grid electrode M1G1 of the first transistor M1 is a main grid electrode of the first transistor M1, the third grid electrode M1G2 is an auxiliary grid electrode of the first transistor M1, the first grid electrode M1G1 of the first transistor M1 can be connected with a third node N3, the on and off of the first transistor M1 are controlled through signals of the third node N3, the third grid electrode M1G2 of the first transistor M1 can be connected with a fixed potential, the effect of improving the stability of the oxide semiconductor transistor is achieved, and the effect of protecting the first active layer M1N is achieved. Similarly, the second gate M2G1 of the second transistor M2 is a main gate of the second transistor M2, the fourth gate M2G2 is an auxiliary gate of the second transistor M2, the second gate M2G1 of the second transistor M2 may be connected to the first node N1, the second transistor M2 is controlled to be turned on and off by a signal of the first node N1, the fourth gate M2G2 of the second transistor M2 may be connected to a fixed potential, so as to play a role in improving stability of the oxide semiconductor transistor, and also play a role in protecting the second active layer M2P.

It should be understood that, in this embodiment, only the materials and structures of the first transistor M1 and the second transistor M2 included in the control module 20 are described, and in other alternative embodiments, the transistors included in the driving circuit 00 other than the first transistor M1 and the second transistor M2 may also refer to the above structures and material arrangements, which are not described herein, and only the driving control of the pixel circuit of the display area AA by implementing the circuit structure output control signal of the shift register 01 need be satisfied.

In some alternative embodiments, please refer to fig. 1, 8, 16 and 24 in combination, fig. 24 is a schematic view of a partial planar structure of the first transistor and the second transistor in fig. 8 and 16 when they are fabricated on the substrate (it is understood that, for clarity of illustration of the structure of the present embodiment, transparency filling is performed in fig. 24), in this embodiment, the multi-stage shift register 01 of the driving circuit 00 located in the non-display area NA extends along the first direction Y; the first transistor M1 and the second transistor M2 are arranged along the second direction X, and the first direction Y intersects the second direction X. Alternatively, the first direction Y and the second direction X are illustrated as being perpendicular to each other in the drawing of the present embodiment. The second direction X of the present embodiment can be understood as an extending direction of one of the scan control lines or the light emission control lines electrically connected to the pixel circuits P1 in the display area AA.

When the circuit structure of the shift register 01 of the embodiment includes the first transistor M1 and the second transistor M2 with different types, the first transistor M1 and the second transistor M2 may be arranged along the second direction X, which is different from the arrangement direction of the multi-stage shift register 01, so that the space occupied by the circuit structure of each shift register 01 in the first direction Y may be reduced.

Alternatively, please refer to fig. 1, 8, 16 and 25 in combination, fig. 25 is another partial plan view schematic diagram of the first transistor and the second transistor in fig. 8 and 16 when they are formed on the substrate (it will be understood that, for clarity of illustration of the structure of the present embodiment, transparency filling is performed in fig. 25), in this embodiment, the multi-stage shift register 01 of the driving circuit 00 located in the non-display area NA extends along the first direction Y;

the first transistor M1 and the second transistor M2 are arranged along the first direction Y.

The embodiment explains that when the driving circuit 00 is disposed in the non-display area NA of the display panel 000, and the circuit structure of the shift register 01 in the driving circuit 00 includes the first transistor M1 and the second transistor M2 with different types, no matter whether the materials of the first active layer M1N of the first transistor M1 and the second active layer M2P of the second transistor M2 are the same, the circuit structure of the same shift register 01 may be disposed, and the first transistor M1 and the second transistor M2 may be disposed along the arrangement direction of the multi-stage shift register 01, that is, the first direction Y, so that the space occupied by the circuit structure of the shift register 01 in the second direction X when fabricated on the substrate 001 may be reduced as much as possible, which is further beneficial for reducing the width of the non-display area NA in the second direction X and realizing a narrower frame design.

In some alternative embodiments, please refer to fig. 8, 16, 26 and 27, fig. 26 is another schematic plan view of a display panel according to an embodiment of the present invention, a circuit structure of a shift register in fig. 26 may be shown with reference to fig. 8 and 16, fig. 27 is a schematic partial cross-sectional view of a first transistor and a second transistor in fig. 26, 8 and 16 formed on a substrate, the display panel 000 according to the embodiment includes a substrate 001, and a driving circuit 00 is formed on the substrate 001;

the display panel 000 further includes an initial input signal line L _STV And/or power signal line L _V Initial input signal line L _STV For providing the driving circuit 00 with an initial input signal, i.e. an initial input signal line L _STV Can be connected with an input signal end STV of the first stage shift register 01 and/or a power supply signal line L _V For supplying a power signal to the light emitting element P2 of the display panel 000;

initial input signal line L _STV A first clock signal line CK, a first voltage signal line VGL, a second voltage signal line VGH, and a power signal line L _V At least one of the signal lines is a preset signal line LY, and the preset signal line LY is located at one side of the film layer where the transistor of the driving circuit 00 is located, which is away from the substrate 001. As shown in fig. 27, in the driving circuit 00, the second source M2S of the second transistor M2 is connected to the second voltage signal line VGH, where the second voltage signal line VGH may be used as a preset signal line LY, and the preset signal line LY (the second voltage signal line VGH) is located on a side of the film layer where the transistor of the driving circuit 00 is located, which is away from the substrate 001.

The present embodiment illustrates that the film structure of the display panel 000 may include a substrate 001, and the substrate 001 may be used as a carrier substrate for fabricating other structures of the display panel 000. At least the transistor array layer 002 may be included on the substrate 001, and the transistor array layer 002 may be used to fabricate a transistor or the like in the driving circuit 00.

The display panel 000 of the present embodiment is further provided with an initial input signal line L _STV And/or power signal line L _V Wherein an initial input signal line L _STV For providing the driving circuit 00 with an initial input signal, i.e. an initial input signal line L _STV Can be connected to the input signal terminal STV of the first stage shift register 01 to provide the start shift signal to the driving circuit 00. Power supply signal line L _V It can be understood that the power bus of the non-display area NA of the display panel 000 is used to supply the power signal to the light emitting element P2 of the pixel unit P of the display area AA of the display panel 000.

The present embodiment sets the initial input signal line L to which the driving circuit 00 is connected _STV A power signal line L electrically connected to the light emitting element P2 in the pixel unit P, a first clock signal line CK, a first voltage signal line VGL, and a second voltage signal line VGH _V At least one of the signal lines located in the non-display area NA is named as a preset signal line LY, and along the direction Z perpendicular to the plane where the substrate base plate 001 is located, the preset signal line LY is located on one side of the film layer where the transistors of the driving circuit 00 are located (i.e. the transistor array layer 002) away from the substrate base plate 001, so that the film layer where the preset signal line LY is located is another conductive film layer except the transistor array layer 002, the preset signal line LY of the non-display area NA is prevented from being made of the film layer of the transistor array layer 002, and further the preset signal line LY of the non-display area NA can be prevented from occupying the width of the non-display area NA in the second direction X, which is beneficial to further reducing the frame.

It is to be understood that the film layer where the transistor array layer 002 is located, i.e., the structure of the transistors in the driving circuit 00 is not particularly limited in this embodiment, the transistor array layer 002 may include a plurality of conductive layers, a plurality of insulating layers, an active layer, and the like, and is used for manufacturing the gate, source and drain, active portion, and the like of the transistors.

Alternatively, please refer to fig. 8, 16, 26 and 28, fig. 28 is the first transistor and the second transistor of fig. 26, 8 and 16Another schematic partial cross-sectional structure of the transistor fabricated on the substrate is shown, in which the predetermined signal line LY overlaps at least one of the first transistor M1 and the second transistor M2 in the direction Z perpendicular to the plane of the substrate 001. Further alternatively, the N-channel transistor in the first transistor M1 and the second transistor M2 is a preset transistor TY; the predetermined signal line LY overlaps with the predetermined transistor TY of the N-channel transistor in a direction perpendicular to the plane of the substrate 001. As shown in fig. 28, the first transistor M1 is an N-channel transistor, and the predetermined signal line LY overlaps the predetermined transistor TY of the N-channel transistor in a direction perpendicular to the plane of the substrate 001. The preset signal line LY may be the initial input signal line L to which the driving circuit 00 is connected _STV A power signal line L electrically connected to the light emitting element P2 in the pixel unit P, a first clock signal line CK, a first voltage signal line VGL, and a second voltage signal line VGH _V At least one of the signal lines located in the non-display area NA is not limited to this embodiment.

The present embodiment explains that when the control module 20 includes the first transistor M1 and the second transistor M2 of different types in the driving circuit 00, at least one of the first transistor M1 and the second transistor M2 is an N-type oxide semiconductor transistor, that is, an active layer of at least one of the first transistor M1 and the second transistor M2 is an oxide semiconductor. Since the N-type oxide semiconductor transistor is sensitive to hydrogen, water and oxygen in the external environment, the present embodiment is disposed in the direction Z perpendicular to the plane of the substrate 001, and the preset signal line LY overlaps at least one of the first transistor M1 and the second transistor M2, so that the preset signal line LY has a shielding effect on the N-type oxide semiconductor transistor of at least one of the first transistor M1 and the second transistor M2, not only can reduce the frame, but also has a protection effect on the preset transistor TY of the N-type channel transistor.

Alternatively, referring to fig. 8, 16, 26 and 29, fig. 29 is a schematic view of another partial cross-sectional structure of the first transistor and the second transistor in fig. 26, 8 and 16 formed on the substrate, in which in the embodiment, the multi-stage shift register 01 of the driving circuit 00 is arranged along the first direction Y;

the width of the preset signal line LY along the second direction X is W1, the width of the preset transistor TY along the second direction X is W2, the first direction Y intersects with the second direction X, and the first direction Y and the second direction X are perpendicular to each other in the figure for illustration in this embodiment; the width W1 of the preset signal line LY along the second direction X is greater than the width W2 of the preset transistor TY along the second direction X, so that the width W1 of the preset signal line LY along the second direction X is as wide as possible, which is beneficial to reducing the resistance of the preset signal line LY, and meanwhile, the shielding protection effect of the preset signal line LY on the preset transistor TY can be improved.

Further alternatively, referring to fig. 8, 16, 29 and 30, fig. 30 is a schematic plan view of another display panel according to an embodiment of the present invention, in this embodiment, the preset signal line LY may be a trace with a non-identical width in the second direction X, for example, the width of the preset signal line LY in the second direction X may be as wide as possible in a space-allowed range, and the width of the preset signal line LY in the second direction X may be reduced in a space-limited region to avoid other conductive structures. In this embodiment, the preset signal line LY is disposed to cover the preset transistor TY completely at least in the second direction X, so that the width W1 of the preset signal line LY is as wide as possible at least in the area where the preset transistor TY is located, so as to cover the preset transistor TY completely, and ensure the protection effect of the preset transistor TY of the N-channel transistor, and meanwhile, the resistance of the preset signal line LY itself can be reduced by the preset signal line LY that is widened as much as possible, which is beneficial to the stability of signal transmission.

In some alternative embodiments, please refer to fig. 8, 16, 31 and 32, fig. 31 is another schematic plan view of the display panel according to the embodiment of the present invention, fig. 32 is a schematic electrical connection structure of the pixel unit in fig. 31, it should be understood that the connection structure of the pixel circuit P1 of the pixel unit P in fig. 32 is merely an example, and the electrical connection structure of the pixel circuit P1 includes but is not limited to the example. The pixel unit P of the display panel 000 includes: the pixel circuit P1, the pixel circuit P1 includes a driving module P11, a reset module P12, a light emitting control module P13, and a compensation module P14, and optionally, the pixel circuit P1 may further include an anode initialization module P16 and a data writing module P17, and in other alternative embodiments, the pixel circuit P1 may further include a bias module (not illustrated). The reset module P12 is connected to the control end of the driving module P11, and is configured to provide a reset signal REF for the driving module P11; the light emission control module P13 may include a first light emission control module P131 and a second light emission control module P132, the first light emission control module P131 being connected between the first power signal line PVDD and the first end of the driving module P11, the second light emission control module P132 being connected between the second end of the driving module P11 and the light emitting element P2 of the display panel 000; the compensation module P14 is connected between the second end of the driving module P11 and the control end of the driving module P11; the transistors included in the reset module P12 and the compensation module P14 may be N-type oxide semiconductor transistors, and the transistors of the other modules may be P-type silicon transistors, which are not described in detail for the working principle of the pixel circuit P1 in this embodiment, and may be specifically understood with reference to the working principle of the display panel 000 in the related art.

The pixel circuit P1 includes a preset module PY, where the preset module is at least one of the reset module P12, the light-emitting control module P13, and the compensation module P14, i.e., the driving circuit 00 of the non-display area NA is configured to provide a control signal for the preset module PY, and when the preset module is at least one of the reset module P12, the light-emitting control module P13, and the compensation module P14, the driving circuit 00 is configured to provide a SCAN control signal (e.g., the SCAN control signal SCAN1 connected to the control terminal of the reset module P12 in fig. 32, the SCAN control signal SCAN2 connected to the control terminal of the compensation module P14) for the preset module PY (e.g., the light-emitting control signal EM connected to the control terminal of the light-emitting control module P13 in fig. 32), and when the preset module is at least one of the reset module P12, the light-emitting control module P13, and the compensation module P14, the driving circuit 00 is configured to provide a SCAN control signal (e.g., the SCAN control signal SCAN2 connected to the control terminal of the reset module P12, the SCAN control signal SCAN2 connected to the control terminal of the control module PY in the pixel circuit P1, and the pixel circuit P1 controls the light-emitting element P2.

It can be understood that, within the space allowable range of the display panel 000, the preset module PY may be set as any one of the anode initialization module P16, the data writing module P17 or the bias module (e.g. the SCAN control signal SCAN4 connected to the control end of the anode initialization module P16 and the SCAN control signal SCAN3 connected to the control end of the data writing module P17 in fig. 32), which is not particularly limited in this embodiment, only the driving circuit 00 needs to be capable of providing a required driving control signal for the pixel circuit P1 of the display area AA, so that the pixel circuit P1 controls the light emitting element P2 to emit light, thereby realizing the display function of the display panel 000.

In this embodiment, the pixel unit P receives a first power supply signal Vpvdd and a second power supply signal Vpvee, where the voltage value of the first power supply signal Vpvdd is greater than the voltage value of the second power supply signal Vpvee; the first power signal line PVDD supplies the first power signal Vpvdd, and the second power signal line PVEE supplies the second power signal Vpvee. Power signal line L in non-display area NA _V For transmitting the second power supply signal Vpvee, the first power supply signal Vpvdd may be an anode voltage signal and the second power supply signal Vpvee may be a cathode voltage signal. That is, the preset signal line LY located in the non-display area NA and overlapping with the preset transistor TY may be the second power signal line PVEE, and the specific second power signal line PVEE of the non-display area NA is the second power bus, and the second power bus for transmitting the second power signal Vpvee is generally made in the non-display area NA of the frame area, and the non-display area NA is generally further provided with the driving circuit 00, so that in order to sufficiently save the frame area, at least a part of the area of the second power signal line PVEE of the non-display area NA as the second power bus overlaps with the driving circuit 00, so that the panel frame can be saved and the narrow frame display can be realized.

The display panel 000 provided in the present embodiment supplies a driving signal to the pixel circuit P1 through the driving circuit 00, and supplies a driving current to the light emitting element P2 of the display panel 000 through the pixel circuit P1; the pixel circuit P1 is connected to the anode of the light emitting element P2 through a first power supply signal line PVDD, the first power supply signal Vpvdd is transmitted to the anode of the light emitting element P2, the second power supply signal line PVEE is connected to the cathode of the light emitting element P2, and the second power supply signal Vpvee is transmitted to the cathode of the light emitting element P2 to drive the light emitting element P2 to emit light; by setting the second power supply signal line PVEE located in the non-display area NA as the preset signal line LY, the second power supply signal line PVEE is disposed to at least partially overlap the driving circuit 00, the occupied area of the bezel area can be effectively reduced, thereby reducing the bezel width of the display panel 000.

In some alternative embodiments, please refer to fig. 1, 33 and 34, 35 and 36 in combination, fig. 33 is another schematic block diagram of the shift register in fig. 1, fig. 34 is a schematic block diagram of the shift register in fig. 33, fig. 35 is another schematic block diagram of the shift register in fig. 1, fig. 36 is a schematic block diagram of the shift register in fig. 35, the first node N1 and the third node N3 in fig. 33 and 34 are directly connected, and the first node N1 and the third node N3 in fig. 35 and 36 are connected through the first adjusting module 301.

As shown in fig. 1, 33 and 35, the shift register 01 further includes a second adjustment module 302; the second adjusting module 302 is connected to at least the fifth node N5 and the third node N3, and the second adjusting module 302 is further connected to the second voltage signal line VGH, the second clock signal line XCK and the second node N2. The second clock signal supplied from the second clock signal line XCK is opposite to the first clock signal supplied from the first clock signal line CK. The second adjusting module 302 is configured to further optimize the potential of the third node M3 under the signal control of the second voltage signal line VGH, the second clock signal line XCK, the second node N2, and the fifth node N5, so that the potential of the third node N3 can ensure that the first output module 401 is fully turned on, the first voltage signal can be directly transmitted to the output signal terminal OUT, and the problem that the output signal of the output signal terminal OUT is not directly changed into the tailing of the first voltage signal due to insufficient conduction of the first output module 401 is avoided, thereby being beneficial to optimizing the stability of the output signal terminal OUT.

In particular, the method comprises the steps of,

as shown in fig. 33 and 34, the input module 10 includes a fifth transistor M5 and a sixth transistor M6; the first end of the fifth transistor M5 is connected to the input signal terminal STV, the second end of the fifth transistor M5 is connected to the first node N1, and the control end of the fifth transistor M5 is connected to the first clock signal line CK. The first terminal of the sixth transistor M6 is connected to the input signal terminal STV, the second terminal of the sixth transistor M6 is connected to the fourth node N4, and the control terminal of the sixth transistor M6 is connected to the first clock signal line CK. The fifth transistor M5 and the sixth transistor M6 of the input module 10 form a parallel structure controlled by the same first clock signal line CK, so that the potential transmitted to the first node N1 by the input module 10 can be made more stable, which is advantageous for improving the driving stability of the entire shift register circuit.

The second adjusting module 302 includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a third capacitor C3; the first terminal and the control terminal of the ninth transistor M9 are connected to the fifth node N5 (the fourth node N4 and the fifth node N5 are directly connected), and the second terminal of the ninth transistor M9 is connected to the third node N3. The first end of the tenth transistor M10 is connected to the second clock signal line XCK, the second end of the tenth transistor M10 is connected to the sixth node N6, and the control end of the tenth transistor M10 is connected to the fifth node N5 (i.e., the fourth node N4); the first end of the eleventh transistor M11 is connected to the second voltage signal line VGH, the second end of the eleventh transistor M11 is connected to the sixth node N6, and the control end of the eleventh transistor M11 is connected to the second node N2; the first plate of the third capacitor C3 is connected to the fifth node N5 (i.e., the fourth node N4), and the second plate of the third capacitor C3 is connected to the sixth node N6.

As shown in fig. 35 and 36, the input module 10 includes a fifth transistor M5 and a sixth transistor M6; the first end of the fifth transistor M5 is connected to the input signal terminal STV, the second end of the fifth transistor M5 is connected to the first node N1, and the control end of the fifth transistor M5 is connected to the first clock signal line CK. The first terminal of the sixth transistor M6 is connected to the input signal terminal STV, the second terminal of the sixth transistor M6 is connected to the fourth node N4, and the control terminal of the sixth transistor M6 is connected to the first clock signal line CK. The fifth transistor M5 and the sixth transistor M6 of the input module 10 form a parallel structure controlled by the same first clock signal line CK, so that the electric potentials transferred to the first node N1 and the fourth node N4 by the input module 10 can be more stable, which is advantageous for improving the driving stability of the entire shift register circuit.

The first adjusting module 301 includes a seventh transistor M7 and an eighth transistor M8, wherein a first end (may be a source of the seventh transistor M7) of the seventh transistor M7 is connected to the first node N1, a second end (may be a drain of the seventh transistor M7) of the seventh transistor M7 is connected to the third node N3, and a control end (may be a gate of the seventh transistor M7) of the seventh transistor M7 is connected to the first voltage signal line VGL. The seventh transistor M7 receives at least the signal of the first node N1 and the first voltage signal supplied from the first voltage signal line VGL, and controls the signal of the third node N3. The first end of the eighth transistor M8 is connected to the fourth node N4, the second end of the eighth transistor M8 is connected to the fifth node N5, and the control end of the eighth transistor M8 is connected to the first voltage signal line VGL. The eighth transistor M8 receives at least the signal of the fourth node N4 and the first voltage signal supplied from the first voltage signal line VGL, and controls the signal of the fifth node N5. The seventh transistor M7 and the eighth transistor M8 of the first adjustment module 301 form a parallel structure controlled by the same first voltage signal line VGL, so that the electric potential transmitted to the third node N3 and the fifth node N5 by the first adjustment module 301 can be more stable, which is beneficial to improving the driving stability of the entire shift register circuit.

The second adjusting module 302 includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a third capacitor C3; the first and control terminals of the ninth transistor M9 are connected to the fifth node N5 (the fourth node N4 and the fifth node N5 are connected through the eighth transistor M8), and the second terminal of the ninth transistor M9 is connected to the third node N3. A first end of the tenth transistor M10 is connected to the second clock signal line XCK, a second end of the tenth transistor M10 is connected to the sixth node N6, and a control end of the tenth transistor M10 is connected to the fifth node N5; the first end of the eleventh transistor M11 is connected to the second voltage signal line VGH, the second end of the eleventh transistor M11 is connected to the sixth node N6, and the control end of the eleventh transistor M11 is connected to the second node N2; the first electrode of the third capacitor C3 is connected to the fifth node N5, and the second electrode of the third capacitor C3 is connected to the sixth node N6.

In this embodiment, the second adjusting module 302 is provided, when the second clock signal provided by the second clock signal line XCK is a low level signal, the fifth node N5 controls the first end and the second end of the tenth transistor M10 to be turned on, the sixth node N6 is a second extremely low level signal of the third capacitor C3, and then the first pole (fifth node N5) plate of the third capacitor C3 is coupled to be a low level signal, and the signal of the fifth node N5 controls the first end and the second end of the ninth transistor M9 to be turned on, so as to control the potential of the third node N3 to be pulled down. Therefore, in this embodiment, the connection structure of the transistor and the third capacitor C3 included in the second adjusting module 302 may further optimize the potential of the third node N3, so that the potential of the third node N3 is as low as possible, thereby ensuring that the third transistor M3 is fully turned on, and the low-level first voltage signal may be directly output from the output signal terminal OUT, so as to improve the tailing phenomenon.

Alternatively, please refer to fig. 36 and fig. 37 in combination, fig. 37 is a timing chart of the shift register circuit in fig. 36, taking the circuit structure of the shift register 01 shown in fig. 36 as an example, the shift register 01 works:

as shown in fig. 37 and 38, in the first period t1, fig. 38 is a conduction state diagram of the transistor in the first period (the schematic "x" on the transistor in the drawing indicates that the transistor is not conductive, and any sign indicates that the transistor is conductive) of the circuit structure in fig. 36, and the seventh transistor M7 and the eighth transistor M8 remain conductive under the first voltage signal supplied from the first voltage signal line VGL. The input signal of the input signal terminal STV is low, the first clock signal provided by the first clock signal line CK is low, the second clock signal provided by the second clock signal line XCK is high, the fifth transistor M5 and the sixth transistor M6 are turned on, the first node N1 and the fourth node N4 are both low, the third node N3 and the fifth node N5 are both low, the second transistor M2 is turned on, the third transistor M3 is turned on, the first transistor M1 is turned off, the second voltage signal of the high level transmitted by the second voltage signal line VGH is transmitted to the second node N2, the fourth transistor M4 is turned off, the first voltage signal of the low level transmitted by the first voltage signal line VGL is transmitted to the output signal terminal OUT, and the output signal of the output signal terminal OUT is a low level signal. At this time, since the second node N2 is at a high level, the eleventh transistor M11 is turned off, the fifth node N5 is first at a low level under the influence of the fourth node N4, the tenth transistor M10 is turned on, when the second clock signal at a high level is transmitted to the sixth node N6 through the tenth transistor M10, the potential of the fifth node N5 is pulled up by the coupling effect of the third capacitor C3, the ninth transistor M9 is turned off, the potential of the third node N3 is not affected by the potential of the fifth node N5, so that the potential of the third node N3 is kept at a low potential, and the third transistor M3 is kept on, so that the output signal of the output signal terminal OUT is continuously at a low level signal.

A second period t2, as shown in fig. 37 and 39, fig. 38 is a circuit configuration in fig. 36

The on-state diagram of the transistor in the second period (the "x" on the transistor in the figure indicates that the transistor is not on, and any sign indicates that the transistor is on), the seventh transistor M7 and the eighth transistor M8 remain on under the first voltage signal supplied from the first voltage signal line VGL. The input signal of the input signal terminal STV is at a high level, the first clock signal provided by the first clock signal line CK is at a high level, the second clock signal provided by the second clock signal line XCK is at a low level, the fifth transistor M5 and the sixth transistor M6 are turned off, the first node N1 and the fourth node N4 remain at a low level due to the conduction of the seventh transistor M7 and the eighth transistor M8, the second transistor M2 is turned on, the first transistor M1 is turned off, the third node N3 is at a low level, the third transistor M3 is continuously turned on, and the low-level first voltage signal transmitted by the first voltage signal line VGL is transmitted to the output signal terminal OUT, so that the output signal of the output signal terminal OUT is at a low level signal. Since the second transistor M2 is continuously turned on, the high-level second voltage signal transmitted by the second voltage signal line VGH is transmitted to the second node N2, the fourth transistor M4 is still turned off, and the second capacitor C2 can stabilize the potential of the second node N2 to be the high-level signal, so as to ensure that the fourth transistor M4 is continuously turned off, and avoid the influence of the high-level second voltage signal transmitted to the output signal terminal OUT on the output low-level signal. At this time, since the second node N2 is at a high level, the eleventh transistor M11 is still turned off, the fifth node N5 is at a low level under the influence of the fourth node N4, the tenth transistor M10 is turned on, when the second clock signal at a low level is transmitted to the sixth node N6 through the tenth transistor M10, the potential of the fifth node N5 is pulled down by the coupling effect of the third capacitor C3, the ninth transistor M9 is turned on, the potential of the third node N3 is affected by the second clock signal at a low level of the fifth node N5, so that the potential of the third node N3 is kept at a low potential, and the third transistor M3 is kept on, so that the output signal of the output signal terminal OUT is continuously at a low level. In addition, in the embodiment, the arrangement of the seventh transistor M7 and the eighth transistor M8 may make the potential of the third node N3 as low as possible, so that the low potential of the third node N3 is not affected by the potential of the first node N1, and the low potential of the third node N3 may be pulled down as low as possible, so as to ensure the on effect of the third transistor M3, so that the third transistor M3 is fully turned on, and the output signal of the output signal terminal OUT is kept as the first voltage signal of the low level signal.

As shown in fig. 37 and 40, in the third period t3, fig. 40 is a conduction state diagram of the transistor in the third period (the schematic "x" in the drawing indicates that the transistor is not on, and any sign indicates that the transistor is on) of the circuit structure in fig. 36, and the seventh transistor M7 and the eighth transistor M8 remain on under the first voltage signal supplied from the first voltage signal line VGL. The input signal of the input signal terminal STV is at a high level, the first clock signal provided by the first clock signal line CK is at a low level, the second clock signal provided by the second clock signal line XCK is at a high level, the fifth transistor M5 and the sixth transistor M6 are turned on, the first node N1 and the fourth node N4 are high level signals due to the control of the input signal at the high level, the second transistor M2 is turned off, the first transistor M1 is turned on, the third node N3 and the fifth node N5 are at a high level, the third transistor M3 is turned off, and the low level first voltage signal transmitted by the first voltage signal line VGL cannot be transmitted to the output signal terminal OUT. Since the first transistor M1 is turned on, the low-level first voltage signal of the first voltage signal line VGL is transmitted to the second node N2, the second node N2 is low, the fourth transistor M4 is turned on, and the high-level second voltage signal transmitted by the second voltage signal line VGH is transmitted to the output signal terminal OUT, so that the output signal of the output signal terminal OUT is a high-level signal. At this time, since the fifth node N5 is at a high level, the ninth transistor M9 and the tenth transistor M10 are turned off, the second node N2 is at a low level, the eleventh transistor M11 is turned on, the high-level second voltage signal transmitted by the second voltage signal line VGH is transmitted to the sixth node N4, the fifth node N5 is kept at a high level by the coupling of the third capacitor C3, the ninth transistor M9 is continuously turned off, the third node N3 is ensured to be a high-level signal, and the third transistor M3 is continuously turned off, so that the high-level signal outputted from the output signal terminal OUT is not affected by the first voltage signal.

In the fourth period t4, as shown in fig. 37 and 41, fig. 41 is a diagram of the circuit structure in fig. 36 in the on state of the transistor in the fourth period (the schematic "x" in the drawing indicates that the transistor is not on, and any sign indicates that the transistor is on), and the seventh transistor M7 and the eighth transistor M8 remain on under the first voltage signal supplied from the first voltage signal line VGL. The input signal of the input signal terminal STV is at a high level, the first clock signal provided by the first clock signal line CK is at a high level, the second clock signal provided by the second clock signal line XCK is at a low level, the fifth transistor M5 and the sixth transistor M6 are turned off, the first node N1 and the fourth node N4 continue to be high level signals due to the conduction of the seventh transistor M7 and the eighth transistor M8, the second transistor M2 is turned off, the first transistor M1 is turned on, the third node N3 remains at a high level signal due to the latch voltage of the first capacitor C1, the third node N3 and the fifth node N5 are at a high level, the third transistor M3 is turned off, and the low level first voltage signal transmitted by the first voltage signal line VGL cannot be transmitted to the output signal terminal OUT. Since the first transistor M1 is turned on, the low-level first voltage signal of the first voltage signal line VGL is transmitted to the second node N2, the second node N2 is low, the fourth transistor M4 is turned on, and the high-level second voltage signal transmitted by the second voltage signal line VGH is transmitted to the output signal terminal OUT, so that the output signal of the output signal terminal OUT is a high-level signal.

In the fifth period t5, as shown in fig. 37 and 38, the on-state diagram of the transistor in the circuit structure in fig. 36 in the fifth period may refer to fig. 38, and the seventh transistor M7 and the eighth transistor M8 remain on under the first voltage signal supplied from the first voltage signal line VGL. The input signal of the input signal terminal STV is low, the first clock signal provided by the first clock signal line CK is low, the second clock signal provided by the second clock signal line XCK is high, the fifth transistor M5 and the sixth transistor M6 are turned on, the first node N1 and the fourth node N4 are low signals, the second transistor M2 is turned on, the first transistor M1 is turned off, the third node N3 and the fifth node N5 are low, the third transistor M3 is turned on, and the low-level first voltage signal transmitted by the first voltage signal line VGL is transmitted to the output signal terminal OUT. Since the second transistor M2 is turned on, the high-level second voltage signal of the second voltage signal line VGH is transmitted to the second node N2, the second node N2 is high, the fourth transistor M4 is turned off, and the high-level second voltage signal transmitted by the second voltage signal line VGH cannot be transmitted to the output signal terminal OUT.

At this time, since the second node N2 is at a high level, the eleventh transistor M11 is turned off, the fifth node N5 is first at a low level under the influence of the fourth node N4, the tenth transistor M10 is turned on, when the second clock signal at a high level is transmitted to the sixth node N6 through the tenth transistor M10, the potential of the fifth node N5 is pulled up by the coupling effect of the third capacitor C3, the ninth transistor M9 is turned off, the potential of the third node N3 is not affected by the potential of the fifth node N5, so that the potential of the third node N3 is kept at a low potential, and the third transistor M3 is kept on, so that the output signal of the output signal terminal OUT is continuously at a low level signal.

As shown in fig. 36 and 37, the circuit structure of the shift register 01 of the present embodiment sets the first capacitor C1 between the third node N3 and the output signal terminal OUT, when the input signal of the input signal terminal STV jumps from the high level to the low level and the first clock signal provided by the first clock signal line CK is at the low level and the second clock signal provided by the second clock signal line XCK is at the high level in the fifth period t5The potential of the output signal end OUT is pulled low, and due to the coupling effect of the first capacitor C1, the potential of the output signal end OUT becomes low, so that the first capacitor C1 can couple the third node N3 to a negative potential direction, and the potential of the third node N3 is as much lower than V as possible _VGL - |Vth| further ensures the conduction stability of the third transistor M3, the first voltage signal of the first voltage signal line VGL is directly transmitted to the output signal end OUT through the third transistor M3, the potential of the output signal end OUT is directly pulled down to the first voltage signal of the low level, further the problem of waveform trailing of the output signal end OUT in a fifth time period t5 can be avoided, the output signal of the shift register 01 is more stable, and further the display effect of the display panel 000 is further ensured.

The circuit structure of the shift register 01 provided in this embodiment not only can ensure the shift register function of the shift register 01, but also can simplify the circuit while providing control signals for the pixel circuits of the display area AA, so that the number of transistors in the driving circuit 00 is reduced as much as possible, which is more beneficial to the design of a narrow frame, and the design of a plurality of transistors and a third capacitor C3 in the first capacitor C1 and the second adjusting module 302 of the first latch module 4011 can be further used, so that the output signals of the shift register 01 are more stable, the problem of tailing of the output signals of the shift register 01 is improved, and further the display effect of the display panel 000 is further beneficial to be ensured.

In some alternative embodiments, please refer to fig. 42, fig. 42 is a schematic plan view of a display device according to an embodiment of the present invention, and the display device 111 according to the present embodiment includes the display panel 000 according to the above embodiment of the present invention. The embodiment of fig. 42 is only an example of a mobile phone, and the display device 111 is described, and it is to be understood that the display device 111 provided in the embodiment of the present invention may be other display devices 111 having a display function, such as a computer, a television, and a vehicle-mounted display device, which is not particularly limited in the present invention. The display device 111 provided in the embodiment of the present invention has the beneficial effects of the display panel 000 provided in the embodiment of the present invention, and the specific description of the display panel 000 in the above embodiments may be referred to specifically, and this embodiment is not repeated here.

As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, comprising:

a driving circuit including a shift register, the shift register including:

the input module is at least connected with the input signal end, the first clock signal line and the first node;

the control module is at least connected with a first voltage signal line, a second voltage signal line, the first node, the second node and a third node, and the first node is directly connected with the third node or is connected with the third node through a first adjusting module;

the output module comprises a first output module and a second output module, wherein the first output module is at least connected with the first voltage signal line, the third node and the output signal end, and the second output module is at least connected with the second voltage signal line, the second node and the output signal end.

2. The display panel of claim 1, wherein the display panel comprises,

the input module receives at least an input signal and a first clock signal and controls the signal of the first node;

the control module receives at least a first voltage signal, a second voltage signal, signals of the first node and the third node, and signals of the second node;

the first output module receives at least a first voltage signal and a signal of the third node to control an output signal, and the second output module receives at least a second voltage signal and a signal of the second node to control an output signal.

3. The display panel of claim 2, wherein the display panel comprises,

the first voltage signal is a low level signal and the second voltage signal is a high level signal.

4. The display panel of claim 1, wherein the display panel comprises,

the control module comprises a first control module and a second control module;

the first control module is at least connected to the first voltage signal line, the second node and the third node;

the second control module is connected to at least the second voltage signal line, the first node, and the second node.

5. The display panel of claim 4, wherein the display panel comprises,

the first control module receives at least a first voltage signal and a signal of the third node, and controls a signal of the second node;

the second control module receives at least a second voltage signal and a signal of the first node and controls the signal of the second node.

6. The display panel of claim 4, wherein the display panel comprises,

the control end of the first control module is connected with the third node, and the control end of the second control module is connected with the first node;

when the signal of the third node controls the first control module to be started, the signal of the first node controls the second control module to be started; or,

when the signal of the third node controls the first control module to be turned off, the signal of the first node controls the second control module to be turned on.

7. The display panel of claim 4, wherein the display panel comprises,

the first control module comprises a first transistor, and the second control module comprises a second transistor;

a first end of the first transistor is connected to the first voltage signal line, a second end of the first transistor is connected to the second node, and a control end of the first transistor is connected to the third node; and/or the number of the groups of groups,

The first end of the second transistor is connected to the second voltage signal line, the second end of the second transistor is connected to the second node, and the control end of the second transistor is connected to the first node.

8. The display panel of claim 7, wherein the display panel comprises,

when the signal of the third node controls the first transistor to be turned on, the signal of the first node controls the second transistor to be turned off; or,

when the signal of the third node controls the first transistor to be turned off, the signal of the first node controls the second transistor to be turned on.

9. The display panel of claim 7, wherein the display panel comprises,

the first transistor is of a different type than the channel region of the second transistor.

10. The display panel of claim 7, wherein the display panel comprises,

the first transistor is an N-type channel transistor, and the second transistor is a P-type channel transistor; or,

the first transistor is a P-type channel transistor, and the second transistor is an N-type channel transistor.

11. The display panel of claim 10, wherein the display panel comprises,

the active layer of the first transistor includes silicon, and the active layer of the second transistor includes an oxide semiconductor; or,

The active layer of the first transistor includes an oxide semiconductor, and the active layer of the second transistor includes silicon.

12. The display panel of claim 11, wherein the display panel comprises,

the first transistor comprises a first grid electrode, a first active layer, a first source electrode and a second drain electrode;

the second transistor comprises a second grid electrode, a second active layer, a second source electrode and a second drain electrode;

the first active layer includes silicon, and the second active layer includes an oxide semiconductor; or,

the first active layer includes an oxide semiconductor, and the second active layer includes silicon.

13. The display panel of claim 12, wherein the display panel comprises,

the first transistor further comprises a third grid electrode, the first grid electrode and the third grid electrode are respectively positioned at two sides of the first active layer, and the first active layer comprises an oxide semiconductor; or,

the second transistor further comprises a fourth grid electrode, the second grid electrode and the fourth grid electrode are respectively positioned at two sides of the second active layer, and the second active layer comprises an oxide semiconductor.

14. The display panel of claim 7, wherein the display panel comprises,

the multi-stage shift register of the driving circuit extends along a first direction;

The first transistor and the second transistor are arranged along the first direction.

15. The display panel of claim 7, wherein the display panel comprises,

the first transistor and the second transistor are arranged along a second direction, and the first direction intersects the second direction.

16. The display panel of claim 7, wherein the display panel comprises,

the display panel comprises a substrate, and the driving circuit is formed on the substrate;

the display panel further comprises an initial input signal line and/or a power signal line, wherein the initial input signal line is used for providing an initial input signal for the driving circuit, and/or the power signal line is used for providing a power signal for a light-emitting element of the display panel;

at least one of the initial input signal line, the first clock signal line, the first voltage signal line, the second voltage signal line and the power signal line is a preset signal line, and the preset signal line is positioned on one side of a film layer where a transistor of the driving circuit is positioned, which is far away from the substrate.

17. The display panel of claim 16, wherein the display panel comprises,

the preset signal line overlaps at least one of the first transistor and the second transistor in a direction perpendicular to the substrate base.

18. The display panel of claim 16, wherein the display panel comprises,

n-type channel transistors in the first transistor and the second transistor are preset transistors;

the preset signal line overlaps the preset transistor in a direction perpendicular to the substrate.

19. The display panel of claim 18, wherein the display panel comprises,

the width of the preset signal line along the second direction is W1, the width of the preset transistor along the second direction is W2, and the first direction is intersected with the second direction; wherein,

W1＞W2。

20. the display panel of claim 19, wherein the display panel comprises,

the preset signal line completely covers the preset transistor at least in the second direction.

21. The display panel of claim 16, wherein the display panel comprises,

the display panel comprises a pixel unit, wherein the pixel unit comprises a pixel circuit and a light-emitting element;

The pixel unit receives a first power supply signal and a second power supply signal, wherein the voltage value of the first power supply signal is larger than that of the second power supply signal;

the power signal line is used for transmitting the second power signal.

22. The display panel of claim 1, wherein the display panel comprises,

the first node is directly connected with the third node.

23. The display panel of claim 1, wherein the display panel comprises,

the first node is connected with the third node through the first adjusting module, and the first adjusting module is at least connected with the first node, the third node and the first voltage signal line.

24. The display panel of claim 23, wherein the display panel comprises,

the first regulation module receives at least the signal of the first node and a first voltage signal provided by the first voltage signal line, and controls the signal of the third node.

25. The display panel of claim 1, wherein the display panel comprises,

the first output module comprises a first latch module which is connected between the third node and the output signal end; and/or the number of the groups of groups,

the second output module comprises a second latch module, and the second latch module is connected between the second node and the second voltage signal line.

26. The display panel of claim 25, wherein the display panel comprises,

the first latch module comprises a first capacitor, a first polar plate of the first capacitor is connected to the third node, and a second polar plate of the first capacitor is connected to the output signal end; and/or the number of the groups of groups,

the second latch module comprises a second capacitor, a first polar plate of the second capacitor is connected to the second node, and a second polar plate of the second capacitor is connected to the second voltage signal line.

27. The display panel of claim 1, wherein the display panel comprises,

the first output module includes a third transistor, and the second output module includes a fourth transistor;

a first end of the third transistor is connected to the first voltage signal line, a second end of the third transistor is connected to the output signal end, and a control end of the third transistor is connected to the third node;

the first end of the fourth transistor is connected to the second voltage signal line, the second end of the fourth transistor is connected to the output signal end, and the control end of the fourth transistor is connected to the second node.

28. The display panel of claim 1, wherein the display panel comprises,

The input module includes a fifth transistor;

the first end of the fifth transistor is connected to the input signal end, the second end of the fifth transistor is connected to the first node, and the control end of the fifth transistor is connected to the first clock signal line.

29. The display panel of claim 28, wherein the display panel comprises,

the input module includes a sixth transistor;

the first end of the sixth transistor is connected to the input signal end, the second end of the sixth transistor is connected to the fourth node, and the control end of the sixth transistor is connected to the first clock signal line.

30. The display panel of claim 29, wherein the display panel comprises,

the first node is connected with the third node through the first adjusting module;

the first regulation module includes a seventh transistor;

the first end of the seventh transistor is connected to the first node, the second end of the seventh transistor is connected to the third node, and the control end of the seventh transistor is connected to the first voltage signal line.

31. The display panel of claim 30, wherein the display panel comprises,

the first regulation module includes an eighth transistor;

The first end of the eighth transistor is connected to the fourth node, the second end of the eighth transistor is connected to the fifth node, and the control end of the eighth transistor is connected to the first voltage signal line.

32. The display panel of claim 31, wherein the display panel comprises,

the shift register further comprises a second adjusting module;

the second regulation module is connected to at least the fifth node and the third node.

33. The display panel of claim 32, wherein the display panel comprises,

the second regulation module includes a ninth transistor;

the first and control terminals of the ninth transistor are connected to the fifth node, and the second terminal of the ninth transistor is connected to the third node.

34. The display panel of claim 33, wherein the display panel comprises,

the second regulation module is also connected to the second voltage signal line, the second clock signal line and the second node.

35. The display panel of claim 34, wherein the display panel comprises,

the second regulation module comprises a tenth transistor, an eleventh transistor and a third capacitor;

a first end of the tenth transistor is connected to the second clock signal line, a second end of the tenth transistor is connected to a sixth node, and a control end of the tenth transistor is connected to the fifth node;

A first end of the eleventh transistor is connected to the second voltage signal line, a second end of the eleventh transistor is connected to the sixth node, and a control end of the eleventh transistor is connected to the second node;

the first polar plate of the third capacitor is connected to the fifth node, and the second polar plate of the third capacitor is connected to the sixth node.

36. The display panel of claim 1, wherein the display panel comprises,

the display panel includes:

the pixel circuit comprises a preset module;

the driving circuit is used for providing a control signal for the preset module.

37. The display panel of claim 36, wherein the display panel comprises,

the pixel circuit comprises a driving module, a resetting module, a light-emitting control module and a compensation module;

the reset module is connected to the control end of the driving module and is used for providing a reset signal for the driving module;

the light-emitting control module is connected between a first power signal wire and a first end of the driving module, and/or is connected between a second end of the driving module and a light-emitting element of the display panel;

The compensation module is connected between the second end of the driving module and the control end of the driving module; wherein,

the preset module is at least one of the reset module, the light-emitting control module and the compensation module.

38. A display device comprising the display panel of any one of claims 1-37.