CN117098317A

CN117098317A - Method for manufacturing circuit board and stacking structure

Info

Publication number: CN117098317A
Application number: CN202210510399.2A
Authority: CN
Inventors: 郭俊宏
Original assignee: Unimicron Technology Corp
Current assignee: Unimicron Technology Corp
Priority date: 2022-05-11
Filing date: 2022-05-11
Publication date: 2023-11-21

Abstract

The invention relates to a method for manufacturing a circuit board and a stacking structure. The method of manufacturing the circuit board includes providing a composite film having a metal film and a polymer film, disposing a dielectric layer on the polymer film to form a stacked structure, forming a wiring layer having a connection pad on a substrate, laminating the stacked structure on the substrate and the wiring layer such that the dielectric layer directly contacts the substrate and completely covers the wiring layer, and forming a first opening in the metal film to form a patterned metal film, wherein the first opening penetrates through the metal film. The method of manufacturing the circuit board further includes plasma etching the dielectric layer using the patterned metal film as a mask to form a second opening in the dielectric layer exposing the connection pad, removing the composite film, and depositing a conductive material in the second opening to form a conductive blind via electrically connecting the connection pad. Thereby improving the reliability of the circuit board.

Description

Method for manufacturing circuit board and stacking structure

Technical Field

The present disclosure provides a method of manufacturing a circuit board and a stacked structure, wherein the stacked structure can be applied to the method of manufacturing the circuit board.

Background

The trend in electronic products has been toward rapid, multi-functional, miniaturized, and high performance. To meet the miniaturization requirements of electronic products, it has become a challenge for those skilled in the art to fabricate lighter, thinner, shorter and smaller high reliability circuit boards.

Disclosure of Invention

According to some embodiments of the present disclosure, a method of manufacturing a circuit board includes providing a composite film having a metal film and a polymer film, disposing a dielectric layer on the polymer film to form a stacked structure, forming a first wiring layer having at least one connection pad on a substrate, pressing the stacked structure on the substrate and the first wiring layer such that the dielectric layer directly contacts the substrate and completely covers the first wiring layer, and forming a first opening in the metal film to form a patterned metal film, wherein the first opening penetrates the metal film. The method of manufacturing a circuit board further includes plasma etching the dielectric layer using the patterned metal film as a mask to form a second opening in the dielectric layer exposing the at least one connection pad, removing the composite film, and depositing a conductive material in the second opening to form a conductive blind via electrically connecting the at least one connection pad.

In some embodiments, the method of manufacturing a circuit board further includes surface treating the polymer film prior to disposing the dielectric layer on the polymer film such that the polymer film has a first roughened surface, wherein the first roughened surface has an average roughness (Ra) of less than 1 μm (micrometer).

In some embodiments, a method of surface treating a polymer film includes performing a plasma process on the polymer film.

In some embodiments, when the dielectric layer is disposed on the polymer film, the dielectric layer is brought into full contact with the first roughened surface such that the dielectric layer has a second roughened surface having an average roughness of less than 1 μm.

In some embodiments, the average roughness of the second roughened surface is substantially equal to the average roughness of the first roughened surface.

In some embodiments, the method of manufacturing a circuit board further includes depositing a conductive material on the dielectric layer to form a second wiring layer, wherein the second wiring layer fully contacts the second roughened surface such that the second wiring layer has a third roughened surface, and an average roughness (Ra) of the third roughened surface is less than 1 μm.

In some embodiments, the method of forming the opening includes performing a laser drilling process.

In some embodiments, when the opening is formed, the opening is configured to be located directly above the at least one connection pad of the first wiring layer.

In some embodiments, the dielectric layer remains completely covering the first circuit layer after the openings are formed.

In some embodiments, the width of the through-hole blind hole is equal to or less than the width of the opening.

In some embodiments, the first wiring layer has a thickness of less than 8 μm.

According to other embodiments of the present disclosure, a stacked structure includes a composite film having a metal film and a polymer film, a dielectric layer, and a release layer. The dielectric layer is disposed on the composite film and directly contacts the polymer film. The release film is disposed on the dielectric layer and directly contacts the dielectric layer.

In some embodiments, the material of the polymeric film is substantially the same as the material of the release film.

In some embodiments, the polymer film has a first roughened surface that contacts the dielectric layer, and the dielectric layer has a second roughened surface that contacts the polymer film, the first roughened surface and the second roughened surface cooperating.

In some embodiments, the first roughened surface is an irregular undulating topography.

In some embodiments, the polymer film is sandwiched between a metal film and a dielectric layer.

According to still further embodiments of the present disclosure, a method of manufacturing a circuit board includes providing a stacked structure having a composite film composed of a metal film and a polymer film, a dielectric layer disposed on the composite film and in direct contact with the polymer film, and a release film disposed on the dielectric layer and in direct contact with the dielectric layer. The method for manufacturing the circuit board further comprises the step of pressing the dielectric layer and the composite material film on the first circuit layer after the release film is removed, wherein the first circuit layer is provided with a connecting pad, and the dielectric layer is in direct contact with the first circuit layer. The method for manufacturing the circuit board further comprises patterning the metal film and etching the dielectric layer by a plasma process to expose the connection pads of the first circuit layer, wherein the patterned metal film is used as an etching mask. The method of manufacturing a circuit board further includes removing the composite film after exposing the connection pads of the first wiring layer. The method for manufacturing the circuit board further comprises the steps of forming a conductive blind hole on the connecting pad of the first circuit layer and forming a second circuit layer on the dielectric layer, wherein the second circuit layer is electrically connected with the first circuit layer through the conductive blind hole.

The embodiment of the disclosure provides a stacking structure and a method for manufacturing a circuit board by using the stacking structure so as to improve the reliability of the circuit board.

Drawings

The following methods are read in conjunction with the accompanying drawings to provide a clear understanding of the aspects of the present disclosure. It should be noted that the various features are not drawn to scale according to industry standard practices. In fact, the dimensions of the various features may be arbitrarily expanded or reduced for clarity of discussion.

Fig. 1A-1C illustrate cross-sectional views of various stages in the fabrication of a stacked structure, according to some embodiments of the present disclosure.

Fig. 2A-2E illustrate cross-sectional views of various stages of manufacturing a circuit board, according to some embodiments of the present disclosure.

Fig. 3A-3B illustrate cross-sectional views of various stages in the fabrication of a stacked structure, according to further embodiments of the present disclosure.

Fig. 4A-4C illustrate cross-sectional views of various stages of manufacturing a circuit board according to further embodiments of the present disclosure.

[ Main element symbols description ]

100: stacked structure 102: metal film

102': patterning metal film 104: polymer film

106: dielectric layer 108: release film

110: composite film 120: stacked structure

200: circuit board 202: substrate board

204: first circuit layer 206: second circuit layer

208: connection pad 210: a first opening

210': first opening 210": a first opening

220: second opening 220': a second opening

220": second opening 220A: a second opening

220A': second opening 220A ": a second opening

230: conductive blind via 230': conductive blind hole

230": conductive blind via 300: stacked structure

304: polymer film 304S: a first rough surface

306: dielectric layer 306S: a second rough surface

310: composite film 320: stacked structure

400: circuit board 406: second circuit layer

406S: third roughened surface 420: a second opening

420': second opening 420": a second opening

420A: second opening 420A': a second opening

420A ": second opening 430: conductive blind hole

430': conductive blind via 430": conductive blind hole

P1: plasma process P2: surface treatment

Detailed Description

When an element is referred to as being "on" …, it can be broadly interpreted as referring to the element directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, it can be without other elements present therebetween. As used herein, the term "and/or" includes any combination of one or more of the listed associated items.

The terms first, second, third, etc. are used herein to describe various elements, components, regions, layers and/or blocks. These elements, components, regions, layers and/or blocks should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Accordingly, a first element, component, region, layer and/or section discussed below could be termed a second element, component, region, layer and/or section without departing from the spirit of the present disclosure.

Moreover, spatially relative terms, such as "under", "lower", "upper", and the like, may be used for convenience in describing the relationship of one element or feature to another element(s) or feature in the drawings. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is turned to a different orientation (e.g., rotated 90 degrees or other orientations), the spatially relative descriptors used herein interpreted in accordance with the turned orientation.

Unless otherwise indicated, when the following embodiments are illustrated or described as a series of acts or events, the order of their description should not be limited. For example, some operations or events may occur in different orders than those shown in the present disclosure, some may occur concurrently, some may not be required, and/or some may be repeated. Moreover, the actual process may require additional operations before, during, or after each step. Thus, the present disclosure may briefly describe some of the additional operations.

Fig. 1A-1C illustrate cross-sectional views of various stages in the fabrication of a stacked structure 100, according to some embodiments of the present disclosure. Referring to fig. 1A, a composite film 110 is provided, wherein the composite film 110 has a metal film 102 and a polymer film 104. The composite film 110 may be a two-layer or multi-layer structure. In some embodiments, the lower surface of the composite film 110 is the lower surface of the polymer film 104, and the upper surface of the composite film 110 is the upper surface of the metal film 102.

In an embodiment in which the composite film 110 is a bilayer structure comprising the metal film 102 and the polymer film 104, the method of forming the composite film 110 may include forming the metal film 102 on the upper surface of the polymer film 104, wherein the metal film 102 entirely covers the upper surface of the polymer film 104. Methods of forming the metal film 102 may include physical vapor deposition, electroless plating (i.e., electroless plating), or attaching a metal foil layer to the polymer film 104. The corresponding formation method can be selected according to the process conditions or the product design requirements to obtain the corresponding thickness value of the metal film 102.

In some embodiments, when physical vapor deposition is employed to form the metal film 102, the thickness of the metal film 102 may be between about 0.05 μm (micrometers) to about 1.00 μm. In some embodiments, when electroless plating (electroless plating) is employed to form the metal film 102, the thickness of the metal film 102 may be between about 0.1 μm and about 2.0 μm. In some embodiments, when the metal film 102 is a metal foil layer, the thickness of the metal film 102 can be between about 1 μm to about 12 μm.

The material of the polymer film 104 may include Polyimide (PI), polyethylene terephthalate (polyethylene terephthalate, PET), polyethylene naphthalate (polythylene naphthalate, PEN), polyurethane (PU), polyethylene (PE), polypropylene (PP), polytetrafluoroethylene (PTFE), polyvinylchloride (polyvinyl chloride polymer, PVC), other suitable materials, or any combination of the above. The thickness of the polymer film 104 may be between about 5 μm to about 100 μm. If the thickness of the polymer film 104 is less than the aforementioned lower limit, the operational difficulty of the subsequent process (e.g., tearing the composite film 110) may be increased.

Referring to fig. 1B, a dielectric layer 106 is disposed on a composite film 110 to form a stacked structure 120. Specifically, the dielectric layer 106 is disposed on the lower surface of the polymer film 104 of the composite film 110. In some embodiments, the dielectric layer 106 directly contacts the polymer film 104. Thus, one side of the polymer film 104 of the composite film 110 is covered by the dielectric layer 106, while one side of the metal film 102 of the composite film 110 remains exposed. In an embodiment in which the composite film 110 is a bilayer structure of the metal film 102 and the polymer film 104, the polymer film 104 is sandwiched between the metal film 102 and the dielectric layer 106. When the polymer film 104 is selected from materials having suitable mechanical strength (e.g., tensile, compressive, elastic, etc.), the polymer film 104 can protect the ductile metallic film 102 from damage, such as reducing the risk of crushing the metallic film 102 due to external forces. For example, the material of the polymer film 104 may be selected from PET, wherein the tensile strength of PET may be between about 75MPa and about 85MPa, the compression modulus may be between about 2600MPa and about 2800MPa, or the elastic modulus may be between about 3100MPa and about 3200MPa, although the disclosure is not limited thereto.

The material of the dielectric layer 106 may include a liquid crystal polymer (liquidcrystal polymer, LCP), a bismaleimide-triazine (BT), a Film (prepreg), a resin containing an inorganic filler (e.g., ajinomoto Build-up Film, ABF), an epoxy, a Polyimide (PI), or other resin materials, but the disclosure is not limited to the above examples. In some embodiments, the material of the dielectric layer 106 may include a material having a dielectric constant below 3.9 to reduce dielectric losses. In some embodiments, the material of the dielectric layer 106 may include photo-imageable (photo-imageable) dielectric materials or photoactive (photo-activatable) dielectric materials. The method of disposing the dielectric layer 106 on the composite film 110 may include coating a dielectric material (not depicted) on the polymer film 104, and then drying the dielectric material.

Referring to fig. 1C, the release film 108 is disposed on the stack structure 120 to further form the stack structure 100. Specifically, the release film 108 is disposed on the dielectric layer 106. In some embodiments, the release film 108 may directly contact the dielectric layer 106. The release film 108 may provide the function of protecting the stack 120, particularly when the stack 100 is placed in a roll-to-roll fashion (not depicted).

The material of the release film 108 may include PI, PET, PEN, PU, PE, PP, PTFE, PVC, other suitable materials, or any combination thereof. In some embodiments, the material of the release film 108 is substantially the same as the material of the polymer film 104.

Fig. 2A-2E illustrate cross-sectional views of various stages of manufacturing a circuit board 200, according to some embodiments of the present disclosure. In this embodiment, the stacked structure 100 or the stacked structure 120 (refer to fig. 1C) is applied to manufacture the circuit board 200.

Referring to fig. 2A, a first circuit layer 204 is formed on a substrate 202, wherein the first circuit layer 204 has one or more connection pads 208. The formation of the first circuit layer 204 may include a deposition process of conductive material (not shown), an exposure and development process, an etching process, other suitable processes, or a combination thereof. The deposition process may include an electroplating (electroless) process, an electroless plating process, a physical vapor deposition process, other suitable processes, or a combination thereof. In a subsequent process, the first circuit layer 204 may be electrically connected to other devices (not shown).

After the first circuit layer 204 is formed on the substrate 202, the stacked structure 120 is pressed on the substrate 202 and the first circuit layer 204. In some embodiments, the dielectric layer 106 may directly contact the substrate 202 and completely cover the first circuit layer 204.

In some embodiments, before laminating the stack structure 120 to the substrate 202 and the first circuit layer 204, the stack structure 100 shown in fig. 1C may be provided, and the release film 108 is removed from the stack structure 100, and the remaining stack structure 120 may be used in the lamination process described in fig. 2A. In other embodiments, the operations of FIG. 2A may be directly subsequent to the operations of FIG. 1B. That is, the stacked structure 120 in fig. 1B may be directly bonded to the substrate 202 and the first circuit layer 204, and the step of disposing the release film 108 on the stacked structure 120 may be omitted.

Referring to fig. 2B, a first opening 210 is formed in the metal film 102 to form a patterned metal film 102'. The first opening 210 may be disposed directly above the first circuit layer 204. In some embodiments, the first opening 210 may be disposed directly above the connection pad 208 of the first circuit layer 204. In other words, the projection of the first opening 210 on the substrate 202 and the projection of the first circuit layer 204 (or the connection pad 208) on the substrate 202 overlap each other. In some embodiments, the projection of the first opening 210 on the substrate 202 is entirely within the projection of the first wiring layer 204 (or the connection pad 208) on the substrate 202.

In the embodiment shown in fig. 2B, the first opening 210 is shown to penetrate only the metal film 102, but the disclosure is not limited thereto. In fact, the first openings 210 may have different depths, wherein the first openings 210 penetrate at least the metal film 102, i.e. the depth of the first openings 210 may be equal to or greater than the thickness of the metal film 102. Thus, a film layer (e.g., polymer film 104) located under the metal film 102 may be exposed in the first opening 210. Fig. 2B is an exemplary embodiment for illustrating that the appearance of the first opening 210 may be the first opening 210' or the first opening 210", and the appearance may have different depths, but the disclosure is not limited thereto.

Specifically, the first opening 210' extends through the metal film 102 and to the polymer film 104, and the first opening 210″ extends through the metal film 102 and to the dielectric layer 106. The opening pattern (e.g., first opening 210', first opening 210", or the like) and the number of openings may be adjusted according to process conditions or product design requirements. It should be noted that although the first opening 210 "may extend to the dielectric layer 106, as shown in fig. 2B, the first opening 210" does not extend through the dielectric layer 106. In short, after the first opening 210 "is formed, the metal film 102 is penetrated by the first opening 210", while the dielectric layer 106 remains completely covering the first circuit layer 204 so that the first circuit layer 204 is not exposed in the first opening 210 ".

The method of forming the first opening 210 may include a dry etching process or a wet etching process, such as a laser drilling process (laser drill process), a mechanical drilling process, a photolithography or electron beam lithography process, an etching process, any suitable patterning technique, or a combination thereof. In some embodiments in which the first opening 210 is formed using a laser drilling process, both the depth and width of the first opening 210 are positively correlated because the laser energy exhibits a gaussian distribution, e.g., the deeper the depth of the first opening 210 formed using a laser, the wider the width of the first opening 210.

In addition, the depth of the first opening 210 can be determined by adjusting the parameters of the laser, such as the type of laser (e.g., CO ₂ Ultraviolet light, etc.), laser energy, laser beam size, number of laser shots, etc., thereby further determining the width of the first opening 210. For example, when the laser is focused on the metal film 102, it is advantageous to form a small first opening 210, such as the first opening 210 shown in fig. 2B, which has a depth and a width smaller than those of the first opening 210'. In some embodiments, the width of the first opening 210 may be controlled below about 20 μm. It should be noted that the width of the first opening 210 refers to a measured width with reference to the upper surface of the metal film 102. In addition, the laser does not directly irradiate the first circuit layer 204, thereby reducing the risk of damage to the first circuit layer 204 by the laser. Thus, the dielectric layer 106 may remain completely covering the first wiring layer 204.

In some embodiments, after the first opening 210 is formed, a cleaning process, such as desmear (desmear), may be performed on the structure of fig. 2B to remove byproducts (e.g., desmear, carbon residue generated by the laser process) generated during the formation of the first opening 210. In the cleaning process, since the polymer film 104 remains covering the dielectric layer 106, the risk of damage to the dielectric layer 106 by cleaning reactants of the cleaning process is reduced, thereby improving the integrity of the dielectric layer 106 and improving the reliability of the circuit board.

Referring to fig. 2C, the polymer film 104 and the dielectric layer 106 are etched by the plasma process P1 using the patterned metal film 102' as a mask to form a second opening 220 in the dielectric layer 106 and the polymer film 104, wherein the second opening 220 exposes a portion of the first circuit layer 204. The second opening 220 may be referred to as a blind hole. In some embodiments, the second opening 220 exposes the connection pad 208 of the first circuit layer 204.

The plasma process P1 opens the first opening 210 (see fig. 2B) to a second opening 220 extending to the first circuit layer 204. The plasma process P1 selectively etches the metal film 102 and the dielectric layer 106 and the polymer film 104 without metal material through the first opening 210 (see fig. 2B) in the metal film 102 to remove a portion of the dielectric layer 106 and the polymer film 104, but does not substantially etch the metal film 102. Furthermore, if the plasma process P1 is an anisotropic etch, the second opening 220 may be formed with a sidewall substantially perpendicular to the substrate 202.

The first opening 210 (see fig. 2B) in the metal film 102 may define the width of the second opening 220, and other features of the first opening 210, such as the first opening 210 'and the first opening 210", may define the second opening 220' and the second opening 220", respectively. If the plasma process P1 is an anisotropic etching, the width of the second opening 220 may be equal to or smaller than the width of the first opening 210, thereby facilitating the formation of the second opening 220 with a narrow width. For example, the first opening 210 formed using the laser drilling process may have inclined sidewalls (i.e., the opening cross-section is inverted trapezoid), and the width of the second opening 220 may be smaller than the width of the first opening 210. It should be noted that the width of the first opening 210 refers to the measured width with reference to the upper surface of the metal film 102, and the width of the second opening 220 refers to the measured width with reference to the upper surface of the polymer film 104.

In the conventional process, when the opening is formed on the circuit layer by directly using the laser drilling process, the laser may directly irradiate the circuit layer to damage the circuit layer. Therefore, the thickness of the circuit layer in the conventional process may be increased to compensate for the damage. In contrast, the second opening 220 is formed on the first circuit layer 204 by the plasma process P1, and the plasma process P1 is used to reduce the damage to the first circuit layer 204 because the plasma process P1 has an etching selectivity to non-metal materials (e.g., the dielectric layer 106 and the polymer film 104) and metal materials (e.g., the metal film 102 and the first circuit layer 204). Therefore, the first circuit layer 204 can be made thinner, which contributes to a thinner circuit board. In some embodiments, the thickness of the first wiring layer 204 may be less than 8 μm.

In some embodiments, the gases used in the plasma process P1 may include oxygen, nitrogen, helium, neon, argon, xenon, and methyl etherAlkane (CH) ₄ ) Ammonia (NH) ₃ ) Nitrogen trifluoride (NF) ₃ ) Nitric Oxide (NO), carbon tetrafluoride (CF) ₄ ) Silicon tetrafluoride (SiF) ₄ ) Silicon tetrachloride (SiCl) ₄ ) Trimethylsilane (Si (CH) ₃ ) ₃ H) Monosilane (SiH) ₄ ) Dichlorosilane (Cl) ₂ SiH ₂ ) Disilane (Si) ₂ Cl ₆ ) Hexachlorodisilane (Si) ₂ F ₆ ) Other suitable gases, or combinations of the above. In some embodiments, the flow rate of the gas may be between about 1sccm (standard cubic centimeter per minute) to about 1500 sccm. In some embodiments, the plasma process P1 may last between about 0.1 minutes and about 30 minutes. In some embodiments, the pressure of the chamber in the plasma process P1 may be between about 5 millitorr (mtorr) and about 500 millitorr. In some embodiments, the temperature of the chamber in the plasma process P1 may be between about 10 ℃ and about 120 ℃.

Referring to fig. 2D, the composite film 110 is removed, so that the second opening 220 (referring to fig. 2C) is reduced in height to form a second opening 220A, wherein the second opening 220A is in the dielectric layer 106. Specifically, the composite film 110 is peeled off (pel). The second opening 220A is substantially identical to the second opening 220 except for the difference in height. Likewise, for other features, the second opening 220A 'is substantially identical to the second opening 220', and the second opening 220A "is substantially identical to the second opening 220". Thus, the second opening 220A remains exposed portions of the first wiring layer 204. In some embodiments, the second opening 220A remains exposed at the connection pad 208 of the first circuit layer 204. After removing the composite film 110, the upper surface of the dielectric layer 106 is exposed. The second opening 220A may be referred to as a blind hole.

Referring to fig. 2E, a conductive material is deposited in the second opening 220A (referring to fig. 2D) and on the upper surface of the dielectric layer 106 to form a conductive via 230 and a second circuit layer 206. In some embodiments, the second wiring layer 206 is interconnected with the conductive blind via 230.

Since the first circuit layer 204 is exposed in the second opening 220A (see fig. 2D), the conductive via 230 is formed to directly connect with the connection pad 208 of the first circuit layer 204. In some embodiments, the conductive blind via 230 electrically connects the connection pad 208 of the first circuit layer 204 in direct contact. In this embodiment, the second circuit layer 206 may be electrically connected to the first circuit layer 204 through the conductive via 230.

The second opening 220A (see fig. 2D) may define the conductive blind via 230, and other features of the second opening 220A, such as the second opening 220A 'and the second opening 220A ", may define the conductive blind via 230' and the conductive blind via 230", respectively. As described above, in the embodiment of forming the first opening 210 (see fig. 2B) by using the laser drilling process, when the laser is focused on the metal film 102, it is advantageous to form the small first opening 210, thereby forming the second opening 220A with a narrow width, and further forming the conductive blind hole 230 with a narrow width.

Fig. 3A-3B illustrate cross-sectional views of various stages in the fabrication of a stacked structure 300, according to further embodiments of the present disclosure. Referring to fig. 3A, a composite film 310 is provided, wherein the composite film 310 has a metal film 102 and a polymer film 304. Next, the composite film 310 is subjected to a surface treatment P2. In detail, the polymer film 304 of the composite film 310 is subjected to the surface treatment P2 such that the polymer film 304 has a first roughened surface 304S.

The composite film 310 is substantially similar to the composite film 110 (see fig. 1A), except that the polymer film 304 of the composite film 310 has a first roughened surface 304S due to the surface treatment P2. Thus, the description and operation of the composite film 110 in FIG. 1A may be applicable to the composite film 310, except for the surface treatment P2 and the first roughened surface 304S, for example, the polymer film 304 may correspond to the polymer film 104, and thus will not be described in detail herein.

The purpose of the surface treatment P2 of the polymer film 304 is to roughen the surface of the polymer film 304. The surface treatment P2 may include a plasma process, a laser process, an etching process, any technique that may be used to roughen the surface of the polymer film 304, or a combination thereof.

Since the first roughened surface 304S may affect the roughness of subsequently formed wiring layers, in some embodiments, the average roughness (Ra) of the first roughened surface 304S of the polymer film 304 is controlled to be about 1 μm or less. In some embodiments, the first roughened surface 304S may be an irregular undulating topography.

Referring to fig. 3B, a dielectric layer 306 is disposed on a composite film 310 to form a stacked structure 320. Specifically, the dielectric layer 306 is coated on the polymer film 304, and the dielectric layer 306 is brought into contact with the first roughened surface 304S of the polymer film 304. Since the dielectric layer 306 contacts a non-planar surface (i.e., the first roughened surface 304S), the dielectric layer 306 may have a second roughened surface 306S.

Specifically, the dielectric layer 306 may fully contact the first roughened surface 304S such that the dielectric layer 306 conforms along the undulating topography of the first roughened surface 304S. In this way, the second rough surface 306S of the dielectric layer 306 and the first rough surface 304S of the polymer film 304 may cooperate with each other. In this embodiment, the average roughness (Ra) of the second roughened surface 306S is substantially the same as the average roughness (Ra) of the first roughened surface 304S. In this way, when the average roughness (Ra) of the first rough surface 304S is adjusted to be less than about 1 μm, the average roughness (Ra) of the second rough surface 306S may also be less than about 1 μm. In some embodiments, the second roughened surface 306S may be an irregular undulating topography.

The dielectric layer 306 is substantially similar to the dielectric layer 106 (see fig. 1B), except that the dielectric layer 306 has a second roughened surface 306S. Accordingly, the description and operation of the dielectric layer 106 in FIG. 1B are applicable to the dielectric layer 306 except for the second roughened surface 306S, and therefore will not be described in detail herein.

In addition, in the embodiment where the composite film 310 is a bilayer structure composed of the metal film 102 and the polymer film 304, the polymer film 304 is sandwiched between the metal film 102 and the dielectric layer 306. When the polymer film 304 is selected from materials having suitable mechanical strength (e.g., tensile, compressive, elastic, etc.), the polymer film 304 may protect the malleable metal film 102 from damage, such as reducing the risk of crushing the metal film 102 due to external forces. Furthermore, the polymer film 304 can also protect the uniformity of the second rough surface 306S of the dielectric layer 306, so as to reduce the uneven second rough surface 306S caused by local crush of the dielectric layer 306 due to external force. In some embodiments, the material of the polymer film 104 may be selected from PET, wherein the tensile strength of PET may be between about 75MPa and about 85MPa, the compression modulus may be between about 2600MPa and about 2800MPa, or the elastic modulus may be between about 3100MPa and about 3200MPa, although the disclosure is not limited thereto.

After forming the stack 320, the release film 108 is disposed on the stack 320 to form the stack 300. The stacked structure 300 is substantially similar to the stacked structure 100 (see fig. 1C), except that the polymer film 304 has a first rough surface 304S and the dielectric layer 306 has a second rough surface 306S. In other words, the description and operation of the stacked structure 100 in fig. 1B and 1C are applicable to the stacked structure 300 except for the first rough surface 304S of the polymer film 304 and the second rough surface 306S of the dielectric layer 306, for example, the polymer film 304 may correspond to the polymer film 104 and the dielectric layer 306 may correspond to the dielectric layer 106, and thus will not be described in detail herein.

Fig. 4A-4C illustrate cross-sectional views of various stages of manufacturing a circuit board 400, according to some embodiments of the present disclosure. In this embodiment, the stacked structure 300 or the stacked structure 320 (see fig. 3B) is used to manufacture the circuit board 400.

Referring to fig. 4A, the stacked structure 320 is pressed on the substrate 202 and the first circuit layer 204. In some embodiments, the dielectric layer 306 may directly contact the substrate 202 and completely cover the first circuit layer 204. Subsequently, a second opening 420 is formed in the dielectric layer 306 and the polymer film 304 using the operations described in fig. 2B and 2C to form a patterned metal film 102', wherein the second opening 420 exposes a portion of the first circuit layer 204. In some embodiments, the second opening 420 exposes the connection pad 208 of the first circuit layer 204. Likewise, the appearance of the second opening 420 may be the second opening 420' or the second opening 420".

The structure shown in fig. 4A is similar to that shown in fig. 2C, except that the stacked structure 320 in fig. 4A replaces the stacked structure 120 in fig. 2C. In addition, the structure shown in fig. 4A can be achieved by the operations of fig. 2A to 2C. In other words, the description and operation related to fig. 2A-2C are applicable to the structure shown in fig. 4A except that the polymer film 304 has the first rough surface 304S and the dielectric layer 306 has the second rough surface 306S, for example, the second opening 420 may correspond to the second opening 220, and other aspects such as the second opening 420 'and the second opening 420 "may correspond to the second opening 220' and the second opening 220", respectively, and thus will not be described herein.

Referring to fig. 4B, the composite film 310 is removed, such that the second opening 420 (referring to fig. 4A) is reduced in height to form a second opening 420A, wherein the second opening 420A is in the dielectric layer 306. The second opening 420A is substantially identical to the second opening 420 except for the difference in height. Likewise, for other features, the second opening 420A 'is substantially identical to the second opening 420', and the second opening 420A "is substantially identical to the second opening 420". The second opening 420A may be referred to as a blind hole. After removing the composite film 310, the second roughened surface 306S of the dielectric layer 306 is exposed.

The structure shown in fig. 4B is similar to the structure shown in fig. 2D, except that the second roughened surface 306S of the dielectric layer 306. In other words, except that the dielectric layer 306 has the second rough surface 306S, the description and operation in fig. 2D may be applied to the structure shown in fig. 4B, for example, the second openings 420A, 420A 'and 420a″ may correspond to the second openings 220A, 220A' and 220a″ and thus will not be described herein.

Referring to fig. 4C, a conductive material is deposited in the second opening 420A (referring to fig. 4B) and on the second rough surface 306S of the dielectric layer 306 to form the conductive blind via 430 and the second circuit layer 406. In some embodiments, the second wiring layer 406 is interconnected with the conductive blind via 430. In some embodiments, the conductive blind via 430 may be directly connected to the connection pad 208 of the first circuit layer 204. In some further embodiments, the conductive blind via 430 electrically connects the connection pad 208 of the first circuit layer 204 in direct contact. In this embodiment, the second circuit layer 406 may be electrically connected to the first circuit layer 204 through the conductive via 430. Likewise, other appearances of conductive blind via 430 may be conductive blind via 430' or conductive blind via 430".

In some embodiments, as the conductive material is deposited on the dielectric layer 306 to form the second wiring layer 406, the formed second wiring layer 406 is brought into contact with the second roughened surface 306S of the dielectric layer 306. Because the second wire layer 406 contacts a non-planar surface (i.e., the second roughened surface 306S), in some embodiments, the second wire layer 406 may have a third roughened surface 406S.

In some further embodiments, the second wire layer 406 may fully contact the second roughened surface 306S such that the second wire layer 406 conforms along the undulating topography of the second roughened surface 306S. In this way, the third rough surface 406S of the second circuit layer 406 and the second rough surface 306S of the dielectric layer 306 may cooperate with each other. In this embodiment, the average roughness (Ra) of the third roughened surface 406S is substantially the same as the average roughness (Ra) of the second roughened surface 306S. Thus, when the average roughness (Ra) of the second roughened surface 306S is tuned to be less than about 1 μm, the average roughness (Ra) of the third roughened surface 406S may also be less than about 1 μm. In some embodiments, the third roughened surface 406S may be an irregular undulating topography.

The roughened surface (e.g., the second roughened surface 306S or the third roughened surface 406S) may promote bonding between the dielectric layer 306 and the second circuit layer 406 to reduce the risk of delamination, thereby improving the reliability of the circuit board. However, the roughness of the roughened surface may not be excessively large [ e.g., the average roughness (Ra) is controlled to about 1 μm or less ], so as not to limit the scope of application of the subsequently formed circuit board.

It should be noted that the rough surface is sequentially transferred to different film layers by contact, so the surface treatment is only applied to the initial film. As described above, the polymer film 304 is subjected to the surface treatment P2 (see fig. 3A) to form the first rough surface 304S, and then the roughness of the third rough surface 406S of the second circuit layer 406 can be affected by the second rough surface 306S of the dielectric layer 306. Therefore, the second rough surface 306S of the dielectric layer 306 and the third rough surface 406S of the second circuit layer 406 are formed by contact, and the surface treatment P2 (e.g., a plasma process, a laser process, an etching process, or the like) is only performed on the polymer film 304, but not performed on the dielectric layer 306 and the second circuit layer 406, thereby avoiding damage risk to the dielectric layer 306 and the second circuit layer 406, and improving the reliability of the circuit board.

The structure shown in fig. 4C is similar to the structure shown in fig. 2E, except that the second roughened surface 306S of the dielectric layer 306 and the third roughened surface 406S of the second wiring layer 406. In other words, the descriptions and operations in fig. 2E are applicable to the structure shown in fig. 4C except that the dielectric layer 306 has the second rough surface 306S and the third rough surface 406S of the second circuit layer 406, for example, the conductive blind via 430 'and the conductive blind via 430″ may correspond to the conductive blind via 230, the conductive blind via 230' and the third conductive blind via 230″ and will not be described herein.

In summary, various embodiments of the present disclosure provide a method of manufacturing a circuit board and a stacked structure. The stacked structure can be applied to manufacturing a circuit board. The stacked structure is provided with a dielectric layer and a composite material film capable of protecting the dielectric layer, thereby improving the reliability of the circuit board. In addition, a rough surface can be formed in the stacked structure in advance, so that the dielectric layer forms a corresponding rough surface in a contact manner, thereby preventing the dielectric layer from being damaged by direct surface treatment (roughening).

The foregoing generally describes features of several embodiments of the present disclosure, so that those of ordinary skill in the art may readily understand the present disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes and/or obtaining the same advantages of the embodiments of the present invention. Those skilled in the art should also realize that equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of manufacturing a circuit board, comprising:

providing a composite film, wherein the composite film has a metal film and a polymer film;

disposing a dielectric layer on the polymer film to form a stacked structure;

forming a first circuit layer on a substrate, wherein the first circuit layer is provided with at least one connecting pad;

pressing the stacked structure on the substrate and the first circuit layer, so that the dielectric layer directly contacts the substrate and completely covers the first circuit layer;

forming a first opening in the metal film to form a patterned metal film, wherein the opening penetrates the metal film;

plasma etching the dielectric layer by using the patterned metal film as a mask to form a second opening in the dielectric layer, wherein the second opening exposes the at least one connection pad;

removing the composite film; and

depositing a conductive material in the second opening to form a conductive blind via, wherein the conductive blind via is electrically connected to the at least one connection pad.

2. The method of manufacturing a circuit board according to claim 1, further comprising:

the polymer film is surface treated prior to disposing the dielectric layer on the polymer film such that the polymer film has a first roughened surface, wherein the first roughened surface has an average roughness Ra of less than 1 μm.

3. The method of manufacturing a circuit board according to claim 2, wherein the method of performing the surface treatment on the polymer film comprises performing a plasma process on the polymer film.

4. The method of manufacturing a circuit board according to claim 2, wherein when the dielectric layer is disposed on the polymer film, the dielectric layer is brought into full contact with the first roughened surface such that the dielectric layer has a second roughened surface having an average roughness of less than 1 μm.

5. The method of manufacturing a circuit board of claim 4, wherein the average roughness of the second roughened surface is substantially equal to the average roughness of the first roughened surface.

6. The method of manufacturing a circuit board as defined in claim 4, further comprising:

depositing the conductive material on the dielectric layer to form a second circuit layer, wherein the second circuit layer fully contacts the second rough surface so that the second circuit layer has a third rough surface, and the average roughness Ra of the third rough surface is less than 1 μm.

7. The method of claim 1, wherein forming the opening comprises performing a laser drilling process.

8. The method of manufacturing a circuit board of claim 1, wherein the opening is disposed directly above the at least one connection pad of the first circuit layer when the opening is formed.

9. The method of claim 1, wherein the dielectric layer remains completely covering the first circuit layer after the opening is formed.

10. The method of manufacturing a circuit board according to claim 1, wherein the width of the through hole is equal to or smaller than the width of the opening.

11. The method of manufacturing a circuit board according to claim 1, wherein the thickness of the first wiring layer is less than 8 μm.

12. A stacked structure, comprising:

a composite film comprising:

a metal film; and

a polymer film;

a dielectric layer disposed on the composite film and in direct contact with the polymer film; and

and the release film is arranged on the dielectric layer and is directly contacted with the dielectric layer.

13. The stack of claim 12, wherein the material of the polymer film is substantially the same as the material of the release film.

14. The stack of claim 12, wherein the polymer film has a first roughened surface contacting the dielectric layer and the dielectric layer has a second roughened surface contacting the polymer film, the first roughened surface and the second roughened surface cooperating with each other.

15. The stacked structure according to claim 14, wherein the first roughened surface is an irregular undulating topography.

16. The stacked structure of claim 12, wherein the polymer film is sandwiched between the metal film and the dielectric layer.

17. A method of manufacturing a circuit board, comprising:

providing a stacked structure, the stacked structure comprising:

a composite film having a metal film and a polymer film;

a dielectric layer disposed on the polymer film; and

a release film disposed on the dielectric layer;

after the release film is removed, pressing the dielectric layer and the composite material film on a first circuit layer, wherein the first circuit layer comprises a connecting pad and the dielectric layer is directly contacted with the first circuit layer;

patterning the metal film;

etching the dielectric layer by a plasma process to expose the connection pad of the first circuit layer, wherein the patterned metal film is used as an etching mask;

removing the composite film after exposing the connection pad of the first circuit layer;

forming a conductive blind hole on the connection pad of the first circuit layer; and

a second circuit layer is formed on the dielectric layer, wherein the second circuit layer is electrically connected with the first circuit layer through the conductive blind hole.