CN117096102A - Method for etching through hole by dry method - Google Patents
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- CN117096102A CN117096102A CN202311322628.9A CN202311322628A CN117096102A CN 117096102 A CN117096102 A CN 117096102A CN 202311322628 A CN202311322628 A CN 202311322628A CN 117096102 A CN117096102 A CN 117096102A
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- 238000005530 etching Methods 0.000 title claims abstract description 165
- 238000000034 method Methods 0.000 title claims abstract description 65
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 230000003667 anti-reflective effect Effects 0.000 claims abstract description 10
- 238000001312 dry etching Methods 0.000 claims description 29
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 20
- 230000007547 defect Effects 0.000 abstract description 14
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052799 carbon Inorganic materials 0.000 abstract description 13
- 230000008021 deposition Effects 0.000 abstract description 12
- 239000002245 particle Substances 0.000 abstract description 4
- 239000007789 gas Substances 0.000 description 54
- 238000000151 deposition Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000004090 dissolution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application provides a method for etching a through hole by a dry method, which provides a solution for etching an anti-reflection layer finely into two steps of etching, and particularly comprises the following steps of: etching a dielectric stack deposited on a semiconductor substrate, the dielectric stack including a photoresist layer, a bottom anti-reflective layer, a first TEOS layer, a BD layer, a second TEOS layer, and an etch stop layer; performing first etching on the bottom anti-reflection layer by adopting first etching gas; performing second etching on the bottom anti-reflection layer by adopting the second etching gas; and etching the first TEOS layer, the BD layer and the second TEOS layer in sequence to ensure that the etching barrier layer generates loss and form a target metal layer groove. The anti-reflection layer is etched in two steps through specific etching gas, so that the problem that defects occur in the appearance in the through hole etching process and the problem of carbon particle deposition are effectively avoided.
Description
Technical Field
The application relates to the field of semiconductors, in particular to a method for etching a through hole by a dry method.
Background
With the rapid development of semiconductor technology, the integrated circuit has higher and higher integration level, and the performance and precision requirements of devices have increased, so that etching technology has become a critical technology in integrated circuit manufacturing. The dry etching technique has been widely used in the fields of high-precision semiconductor device fabrication, photoelectric device fabrication, material science, and the like as an etching technique having many advantages.
The etching medium of a dry etching system is a plasma, which is a process that reacts with a surface film to produce volatile substances, or directly bombards the film surface to cause it to etch. However, bowl-shaped defects (bowing) and carbon deposition are very easy to form in the process of dry etching the through holes, and the loss of photoresist is easy to cause in the etching process, so that the pattern size cannot be accurately transferred, and the quality of the through holes and the reliability of devices are affected.
Disclosure of Invention
In view of the above problems, the present application has been made to provide a method of dry etching a via that overcomes the problems or at least partially solves the problems, comprising:
a method of dry etching a via for etching a dielectric stack deposited on a semiconductor substrate, the dielectric stack comprising a photoresist layer, a bottom anti-reflective layer, a first TEOS layer, a BD layer, a second TEOS layer, and an etch stop layer;
the method comprises the following steps:
performing first etching on the bottom anti-reflection layer by adopting the first etching gas;
performing second etching on the bottom anti-reflection layer by adopting the second etching gas;
and etching the first TEOS layer, the BD layer and the second TEOS layer in sequence to ensure that the etching barrier layer generates loss and form a target metal layer groove.
Further, the step of performing the first etching on the bottom anti-reflection layer by using the first etching gas includes:
and stopping the first etching of the bottom anti-reflection layer when the etching is performed for 30-45 s.
Further, the first etching gas comprises CF 4 、CHF 3 And O 2 The gas ratio of the first etching gas is CF 4 ：CHF 3 ：O 2 =150：30：2。
Further, the second etching gas comprises CF 4 And O 2 The gas proportion of the second etching gas is CF 4 ：O 2 =150：11。
Further, the condition of the second etching is O 2 At 25-30MHZ.
Further, the step of sequentially etching the first TEOS layer, the BD layer, and the second TEOS layer to generate a loss amount of the etching barrier layer, and forming a target metal layer trench includes:
etching the first TEOS layer by adopting a third etching gas;
etching the BD layer by adopting a fourth etching gas;
and etching the second TEOS layer by adopting fifth etching gas to ensure that the etching barrier layer generates loss amount, so as to form the target metal layer groove.
Further, the third etching gas includes C 4 F 8 、CH 2 F 2 、Ar、O 2 And N 2 The gas proportion of the third etching gas is C 4 F 8 ：CH 2 F 2 ：Ar：O 2 ：N 2 =9：10：600：7：90。
Further, the fourth etching gas includes C 4 F 8 Ar and N 2 The gas proportion of the fourth etching gas is C 4 F 8 ：Ar：N 2 =9：600：80。
Further, the fifth etching gas includes C 4 F 8 Ar and N 2 The gas proportion of the fifth etching gas is C 4 F 8 ：Ar：N 2 =9：600：120。
Further, before the step of performing the first etching on the bottom anti-reflection layer by using the first etching gas, the method further includes:
patterning the photoresist layer to form a patterned photoresist layer;
and carrying out through hole photoetching by taking the patterned photoresist layer as a mask.
The application has the following advantages:
in the embodiment of the application, compared with the problem that bowl-shaped defects and carbon deposition are easy to form in the existing dry etching technology, the application provides a solution for etching an anti-reflection layer finely into two steps, specifically comprising the following steps: performing first etching on the bottom anti-reflection layer by adopting the first etching gas; performing second etching on the bottom anti-reflection layer by adopting the second etching gas; and etching the first TEOS layer, the BD layer and the second TEOS layer in sequence to ensure that the etching barrier layer generates loss and form a target metal layer groove. The anti-reflection layer is etched in two steps through specific etching gas, so that the problem that defects occur in the appearance in the through hole etching process and the problem of carbon particle deposition are effectively avoided.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the following brief description will be given of the drawings required for the description of the present application, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a flow chart of steps of a method for dry etching a via according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a structure of an etching bottom anti-reflective layer according to a method of dry etching a via according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a method for etching a via by dry etching according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of etching a BD layer by a method of dry etching a via hole according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of etching a second TEOS layer by a method for dry etching a via according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a conventional bowl-shaped defect according to an embodiment of the present application;
fig. 7 is a schematic diagram of an etched finished product of a method for dry etching a via according to an embodiment of the present application.
In the figure, 1, a photoresist layer; 2. a bottom anti-reflection layer; 3. a first TEOS layer; 4. a BD layer; 5. a second TEOS layer; 6. etching the barrier layer; 7. a semiconductor substrate; 8. metal contact points.
Detailed Description
In order that the manner in which the above recited objects, features and advantages of the present application are obtained will become more readily apparent, a more particular description of the application briefly described above will be rendered by reference to the appended drawings. It will be apparent that the described embodiments are some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The inventors found by analyzing the prior art that: dry etching is a common microelectronic fabrication process used to form vias in silicon substrates. In the dry etching process, etching substances are accelerated in a plasma form and react with the surface of the substrate due to uneven etching rate, and the etching rate is inconsistent at different positions, so that uneven erosion of photoresist and bowl-shaped defects can be caused.
In addition, carbon deposition may occur during dry etching. This is because the gas in the plasma reacts with the substrate surface to produce carbide deposits. These carbon deposits can clog the etch apertures, affect the uniformity of the etch, and even impede the etching process.
In addition, during dry etching, loss of photoresist may also result. Photoresists are typically used to protect areas of the substrate that do not require etching. However, dissolution, erosion, or stripping of the photoresist may result from ion bombardment and chemical reactions present during dry etching.
Therefore, how to obtain better through hole etching morphology becomes an important research direction of dry etching technology.
Referring to fig. 1, a method for dry etching a via according to an embodiment of the present application is shown;
the method comprises the following steps:
s110, performing first etching on the bottom anti-reflection layer 2 by adopting the first etching gas;
s120, etching the bottom anti-reflection layer 2 for the second time by adopting the second etching gas;
and S130, sequentially etching the first TEOS layer 3, the BD layer 4 and the second TEOS layer 5 to ensure that the etching barrier layer 6 generates loss and form a target metal layer groove.
In the embodiment of the application, compared with the problem that bowl-shaped defects and carbon deposition are easy to form in the existing dry etching technology, the application provides a solution for etching an anti-reflection layer finely into two steps, specifically comprising the following steps: performing first etching on the bottom anti-reflection layer 2 by adopting the first etching gas; performing second etching on the bottom anti-reflection layer 2 by adopting the second etching gas; and etching the first TEOS layer 3, the BD layer 4 and the second TEOS layer 5 in sequence to ensure that the etching barrier layer 6 generates loss amount, so as to form a target metal layer groove. The anti-reflection layer is etched in two steps through specific etching gas, so that the problem that defects occur in the appearance in the through hole etching process and the problem of carbon particle deposition are effectively avoided.
Next, a method of dry etching a via hole in the present exemplary embodiment will be further described.
It should be noted that in any embodiment of the present application, the present application is used for etching a dielectric stack deposited on a semiconductor substrate 7, where the dielectric stack includes a photoresist layer 1, a bottom anti-reflection layer 2, a first TEOS layer 3, a BD layer 4, a second TEOS layer 5, and an etch stop layer 6.
A semiconductor substrate 7 is provided, which semiconductor substrate 7 is a material substrate for manufacturing semiconductor devices, and in the manufacturing process of integrated circuits, the semiconductor substrate 7 is typically made of silicon, which is a silicon wafer with a device layer, which is provided with metal contacts (Cu) 8, which metal contacts 8 have good electrical conductivity and mechanical stability to ensure reliable transmission of electrical signals.
An etching barrier layer 6 (Nitride Doped Silicon Carbide, abbreviated as NDC) is deposited on the semiconductor substrate 7, wherein the NDC is a carbon-containing silicon nitride film, and the composition is SiCN, and is generally formed by adopting a chemical deposition method, so that a through hole is formed in a later stage process and is filled with metal.
The second TEOS layer 5 is deposited on the etch stop layer 6, TEOS (Tetra-Ethyl OrthoSilicate, tetraethyl orthosilicate) being an important deposition source.
The BD layer 4 is deposited on the second TEOS layer 5, the material of the BD layer 4 being SiCOH. The BD layer 4 is porous black diamond, and is used for manufacturing a through hole and filling metal in a back-end process.
The first TEOS layer 3 is deposited on the BD layer 4, the first TEOS layer 3 being tetraethyl orthosilicate.
The bottom antireflective layer 2 is deposited on the first TEOS layer 3.
In an embodiment of the present application, before step S110, the method further includes:
s100, patterning the photoresist layer 1 to form a patterned photoresist layer 1;
s101, performing through hole photoetching by taking the patterned photoresist layer 1 as a mask.
Coating a Photoresist layer 1 (PR) on the bottom anti-reflection layer 2, exposing and developing the Photoresist layer 1 to form a groove pattern on the Photoresist layer 1; the bottom anti-reflection layer 2 is used as a light absorbing layer, and its main component is typically SiON. And etching the bottom anti-reflection layer 2 by taking the patterned photoresist layer 1 as a mask, removing the photoresist layer 1, and forming an etching window for carrying out subsequent main etching in the bottom anti-reflection layer 2.
The bottom anti-reflection layer 2 is etched for the first time using the first etching gas as described in the step S110.
In an embodiment of the present application, the specific process of "etching the bottom anti-reflection layer 2 twice with the anti-reflection layer etching gas" in step S110 may be further described in conjunction with the following description.
The first etching of the bottom antireflective layer 2 is stopped when the etching is effected for 30-45s, as described in the following steps.
As an example, referring to fig. 2, the etching of the Bottom Anti-reflection layer 2 (Bottom Anti-Reflection Coating, BARC for short) is a two-step etching: barc1+barc2. The first step of etching is particularly important in the dry etching of the bottom anti-reflective layer 2, and in high-integrated circuits bowl defects and carbon deposition can easily occur if conventional one-step etching is used. In the embodiment, the etching condition is O 2 The BARC1 gas is CF at 25-30MHz 4 、CHF 3 And O 2 The BARC1 gas proportion is CF 4 ：CHF 3 ：O 2 =150: 30:2 the bottom anti-reflection layer 2 is etched for the first time for ensuring the dimensions. And stopping the first etching of the bottom anti-reflection layer 2 when the etching action is performed for 30-45s, and performing the second etching of the bottom anti-reflection layer 2 by adopting a second etching gas.
The bottom anti-reflection layer 2 is etched a second time using the second etching gas as described in the step S120.
As an example, referring to FIG. 2, the BARC2 gas is CF 4 And O 2 The gas ratio is CF 4 ：O 2 =150: and 11, etching the bottom anti-reflection layer 2 from the bottom after the first etching is finished for the second time. Under the etching condition of O 2 At 25-30MHz, the highly anisotropic etch performance advantageously reduces the etching of the sidewall BARC, making the sidewall topography more vertical, so that bowl defects hardly occur. The reasonable proportion of gas also reduces defects of carbon deposition, so that patterns can be transferred to the next layer better.
In one specific implementation, the present embodiment subdivides the anti-reflective layer 2 etch into a 2-step bond, which has the advantage that the first step BARC1 facilitates the adjustment of CD linewidth,BARC2 reduces carbon deposition and controls pattern transfer. The BARC1 gas proportion is CF 4 ：CHF 3 ：O 2 =150: 30:2, BARC2 gas ratio is CF 4 ：O 2 =150: 11, it should be noted that the oxygen frequency of BARC2 is at 27 MHZ.
As described in step S130, the first TEOS layer 3, the BD layer 4, and the second TEOS layer 5 are etched in sequence, so that the etching stopper layer 6 generates a loss amount, and a target metal layer trench is formed.
In an embodiment of the present application, the specific process of "etching the first TEOS layer 3, the BD layer 4, and the second TEOS layer 5 sequentially to cause the loss of the etching stopper layer 6 and form the target metal layer trench" in step S130 may be further described in conjunction with the following description.
Etching the first TEOS layer 3 with a third etching gas as follows;
etching the BD layer 4 by using a fourth etching gas as follows;
and etching the second TEOS layer 5 by using a fifth etching gas to generate a loss amount of the etching barrier layer 6, thereby forming the target metal layer trench.
In a specific implementation, referring to fig. 3, after two etches of the bottom anti-reflection layer 2 are completed, a third etching gas C is then used 4 F 8 、CH 2 F 2 、Ar、O 2 And N 2 Dry etching the first TEOS layer 3 to obtain a gas ratio of C 4 F 8 ：CH 2 F 2 ：Ar：O 2 ：N 2 =9: 10:600:7:90. access CH 2 F 2 Has a certain protection effect on PR and can accurately copy the photoetching pattern.
Referring to FIG. 4, a fourth etching gas C is then used 4 F 8 Ar and N 2 Dry etching is carried out on the BD layer 4, wherein the gas proportion is C 4 F 8 ：Ar：N 2 =9: 600:80, precisely controlling the morphology of the through holes.
Referring to FIG. 5, finally, a fifth etching gas is used to contain C 4 F 8 Ar and N 2 Dry etching the second TEOS layer 5 to generate a certain loss of the etching barrier layer 6 with a gas ratio of C 4 F 8 ：Ar：N 2 =9: 600:120. wherein C is 4 F 8 The PR is also protected to a certain extent, and the transverse damage to the TEOS layer and the BD layer 4 can be reduced, so that the vertical appearance of the through hole is ensured.
Referring to fig. 6 and 7, fig. 6 is a schematic diagram of bowl-shaped defects occurring in conventional dry etching, and fig. 7 is a schematic diagram of etching by the dry etching through-hole method of the present application, it can be seen that the vertical morphology of the through-hole is ensured by the etching method of the present application, and bowl-shaped defects are avoided.
In the dry etching method provided by the application, the selection of process parameters such as temperature, pressure, time and the like is determined according to specific processing requirements so as to ensure that the semiconductor device can achieve the required precision and performance. The application effectively avoids the problem of morphology defect and reduces the problem of carbon particle deposition in the process of etching the through hole by reasonably adjusting the etching gas proportion and the fine etching step. Meanwhile, the gas components and the gas proportion are reasonably adjusted in the etching process, so that the photoresist can be properly protected from being lost in the etching process, and the method has higher practicability and economic benefit.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the application.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The above description of the method for etching a through hole by dry method provided by the application applies specific examples to illustrate the principle and implementation of the application, and the above examples are only used to help understand the method and core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. A method for dry etching a via for etching a dielectric stack deposited on a semiconductor substrate, the dielectric stack comprising a photoresist layer, a bottom anti-reflective layer, a first TEOS layer, a BD layer, a second TEOS layer, and an etch stop layer;
the method comprises the following steps:
performing first etching on the bottom anti-reflection layer by adopting the first etching gas;
performing second etching on the bottom anti-reflection layer by adopting the second etching gas;
and etching the first TEOS layer, the BD layer and the second TEOS layer in sequence to ensure that the etching barrier layer generates loss and form a target metal layer groove.
2. The method of claim 1, wherein the step of first etching the bottom antireflective layer with the first etching gas comprises:
and stopping the first etching of the bottom anti-reflection layer when the etching is performed for 30-45 s.
3. The method of claim 1, wherein the first etching gas comprises CF 4 、CHF 3 And O 2 The gas ratio of the first etching gas is CF 4 ：CHF 3 ：O 2 =150：30：2。
4. The method of claim 1, wherein the second etching gas comprises CF 4 And O 2 The gas proportion of the second etching gas is CF 4 ：O 2 =150：11。
5. The method of claim 4, wherein the second etching is performed under the condition of O 2 At 25-30MHZ.
6. The method of claim 1, wherein the step of sequentially etching the first TEOS layer, the BD layer, and the second TEOS layer to create a loss amount in the etch stop layer, and forming a target metal layer trench comprises:
etching the first TEOS layer by adopting a third etching gas;
etching the BD layer by adopting a fourth etching gas;
and etching the second TEOS layer by adopting fifth etching gas to ensure that the etching barrier layer generates loss amount, so as to form the target metal layer groove.
7. The method of claim 6, wherein the third etching gas comprises C 4 F 8 、CH 2 F 2 、Ar、O 2 And N 2 The gas proportion of the third etching gas is C 4 F 8 ：CH 2 F 2 ：Ar：O 2 ：N 2 =9：10：600：7：90。
8. The method of claim 6, wherein the fourth etching gas comprises C 4 F 8 Ar and N 2 The gas proportion of the fourth etching gas is C 4 F 8 ：Ar：N 2 =9：600：80。
9. The method of claim 6, wherein the fifth etching gas comprises C 4 F 8 Ar and N 2 The gas proportion of the fifth etching gas is C 4 F 8 ：Ar：N 2 =9：600：120。
10. The method of claim 1, wherein prior to the step of first etching the bottom antireflective layer with the first etching gas, further comprising:
patterning the photoresist layer to form a patterned photoresist layer;
and carrying out through hole photoetching by taking the patterned photoresist layer as a mask.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311322628.9A CN117096102B (en) | 2023-10-13 | 2023-10-13 | Method for etching through hole by dry method |
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| CN202311322628.9A CN117096102B (en) | 2023-10-13 | 2023-10-13 | Method for etching through hole by dry method |
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| CN117096102A true CN117096102A (en) | 2023-11-21 |
| CN117096102B CN117096102B (en) | 2024-01-23 |
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| CN103854995A (en) * | 2012-12-06 | 2014-06-11 | 中微半导体设备(上海)有限公司 | Etching method and device for improving side wall streaks |
| CN107195561A (en) * | 2016-03-14 | 2017-09-22 | 中国科学院微电子研究所 | A kind of cmp defect inspection method |
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| US20060037701A1 (en) * | 2004-06-21 | 2006-02-23 | Tokyo Electron Limited | Plasma processing apparatus and method |
| CN101140882A (en) * | 2006-09-04 | 2008-03-12 | 中芯国际集成电路制造(上海)有限公司 | Through-hole etching method |
| KR20080104902A (en) * | 2007-05-29 | 2008-12-03 | 성균관대학교산학협력단 | Fabrication of multi-layer resist structures using physical-vapor deposited amorphous carbon and forming thin film pattern using the same |
| CN101764081A (en) * | 2008-12-25 | 2010-06-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing connecting hole |
| CN102044414A (en) * | 2009-10-13 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and manufacturing method thereof |
| CN103854995A (en) * | 2012-12-06 | 2014-06-11 | 中微半导体设备(上海)有限公司 | Etching method and device for improving side wall streaks |
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| CN117096102B (en) | 2024-01-23 |
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