CN117096035A - Method for manufacturing bonding pad - Google Patents
Method for manufacturing bonding pad Download PDFInfo
- Publication number
- CN117096035A CN117096035A CN202311085926.0A CN202311085926A CN117096035A CN 117096035 A CN117096035 A CN 117096035A CN 202311085926 A CN202311085926 A CN 202311085926A CN 117096035 A CN117096035 A CN 117096035A
- Authority
- CN
- China
- Prior art keywords
- bonding pad
- etching
- manufacturing
- photoresist pattern
- passivation layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 68
- 238000002161 passivation Methods 0.000 claims abstract description 46
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 42
- 239000007789 gas Substances 0.000 claims abstract description 40
- 238000004380 ashing Methods 0.000 claims abstract description 33
- 229920000642 polymer Polymers 0.000 claims abstract description 32
- 239000011261 inert gas Substances 0.000 claims abstract description 22
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000001301 oxygen Substances 0.000 claims abstract description 11
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 8
- 239000011737 fluorine Substances 0.000 claims abstract description 8
- 230000003313 weakening effect Effects 0.000 claims abstract description 8
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- 230000036470 plasma concentration Effects 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 109
- 239000002184 metal Substances 0.000 claims description 45
- 229910052751 metal Inorganic materials 0.000 claims description 45
- 239000000463 material Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 238000010849 ion bombardment Methods 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910014038 N2H2 Inorganic materials 0.000 claims description 3
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 125000004432 carbon atom Chemical group C* 0.000 claims description 3
- 125000001153 fluoro group Chemical group F* 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 description 3
- 239000006227 byproduct Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- -1 O2+ N2 Chemical compound 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/1181—Cleaning, e.g. oxide removal step, desmearing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
- H01L2224/13018—Shape in side view comprising protrusions or indentations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention discloses a manufacturing method of a bonding pad, which comprises the following steps: and step one, forming a passivation layer and forming a photoresist pattern. And secondly, performing first etching to form a bonding pad window, forming a hard shell on the surface of the photoresist pattern, and forming a silicon-based polymer on the side surface of the bonding pad window. Step three, carrying out etching post-treatment, wherein the process gas comprises the following components: oxygen, fluorine-based gas, and a first inert gas to increase plasma concentration and create bombardment to weaken crust and polymer. Step four, carrying out an ashing process to remove the photoresist pattern, and dividing the ashing process into a low-temperature pretreatment stage and a high-temperature ashing stage; during the low temperature pretreatment stage, the first temperature ensures that the crust is not hardened so that the plasma penetrates the crust, weakening the adhesion between the crust and the photoresist pattern. And fifthly, performing wet cleaning to remove the polymer. The invention can effectively remove the hard shell and polymer residues generated in the etching of the passivation layer.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a bonding pad.
Background
As shown in fig. 1, a schematic device structure after forming a bonding pad by using a conventional bonding pad manufacturing method is shown; the prior manufacturing method of the bonding pad comprises the following steps:
and firstly, forming a passivation layer on the surface of the semiconductor substrate with the top metal layer 106, and performing a photoetching process to form a photoresist pattern, wherein the photoresist pattern opens the bonding pad area and covers the outside of the bonding pad area.
Typically, the semiconductor substrate comprises a silicon substrate.
The material of the top metal layer 106 includes Al.
A plurality of metal layers 104 are further formed on the bottom of the top metal layer 106, and the metal layers 104 are isolated by an interlayer film 101 and connected by a via 103. In fig. 1, a silicon nitride layer 102 is further formed between the interlayer films 101. Fig. 1 shows 3 layers of the interlayer film 101 and two layers of the silicon nitride layer 102.
Each layer of the bottom of the top metal layer 106 the material of the metal layer 104 comprises copper.
In general, the top metal layer 106 is typically connected to the bottom metal layer 104 through a top via 105 of the top interlayer film 101, and an adhesion barrier layer 109 is formed between the top via 105 and the bottom metal layer 104. The material of the top metal layer 106 is the same as that of the top metal layer 105.
The passivation layer is formed by stacking a first silicon oxide layer 107 and a second silicon nitride layer 108.
Step two, performing first etching by taking the photoresist pattern as a mask, wherein the passivation layer of the pad region is removed by the first etching and a pad window is formed, and the top metal layer 106 is exposed from the bottom surface of the pad window and serves as a pad; and forming a crust of carbon-silicon base (C-Si base) on the surface of the photoresist pattern and forming a polymer of silicon base (Si base) on the side surface of the pad window at the same time.
The time of the first etching is adjusted according to the thickness of the passivation layer, and the thicker the passivation layer is, the longer the time of the first etching is, and the more the residual quantity of the hard shell and the residual quantity of the polymer are.
Typically, the first etch also overetch the top metal layer 106.
Step three, carrying out Post-etching-Treatment (PET), wherein the Post-etching Treatment process gas adopts oxygen and fluorine-based (F-base) gas
And step four, carrying out an ashing process to remove the photoresist pattern, wherein in the ashing process, the semiconductor substrate is placed on a high-temperature hot plate, and the ashing process is carried out under a high-temperature environment such as 250 ℃ or higher to remove the photoresist pattern.
And fifthly, carrying out wet cleaning to remove the polymer.
In the prior art, the passivation layer is typically thinner, e.g. less thanThe time of the first etching is not long, and the accumulated residual quantity of the hard shell and the residual quantity of the polymer are not much; the accumulated crust and polymer residue can be removed in both step three and step five.
However, to match with the back-end packaging process, the thickness of the passivation layer in some processes is increased to 150% to 200% of the original thickness, and the etching time of the first etching needs to be increased to match with the passivation layer structure with a new thickness; however, as the etching time increases, it was found that the polymer generated by the etching cannot be completely removed by the current cleaning method, and as shown in fig. 1, polymer residues 110 are finally formed on the bottom surface or side surface of the pad window and the surface of the passivation layer outside the pad.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a manufacturing method of a bonding pad, which can effectively remove hard shell and polymer residues generated in the etching of a passivation layer, and particularly can still effectively remove hard shell and polymer residues generated in the etching of the passivation layer under the condition that the thickness of the passivation layer is increased.
In order to solve the technical problems, the manufacturing method of the bonding pad provided by the invention comprises the following steps:
and firstly, forming a passivation layer on the surface of the semiconductor substrate with the top metal layer, and performing a photoetching process to form a photoresist pattern, wherein the photoresist pattern opens the bonding pad area and covers the outside of the bonding pad area.
Step two, performing first etching by taking the photoresist pattern as a mask, wherein the passivation layer of the pad area is removed by the first etching, a pad window is formed, and the top metal layer is exposed from the bottom surface of the pad window and serves as a pad; and forming a carbon-silicon-based hard shell on the surface of the photoresist pattern and forming a silicon-based polymer on the side surface of the bonding pad window at the same time in the first etching.
Step three, carrying out post-etching treatment, wherein the post-etching treatment process gas comprises the following components: oxygen, a fluorine-based gas, and a first inert gas having an element with an atomic weight greater than an atomic weight of oxygen; the plasma concentration in the post-etch treatment is increased with the first inert gas and the crust and the polymer are weakened with elemental ion bombardment by the first inert gas.
Step four, carrying out an ashing process to remove the photoresist pattern, and dividing the ashing process into a low-temperature pretreatment stage and a high-temperature ashing stage; the first temperature of the low temperature pretreatment stage is lower than the second temperature of the high temperature ashing stage.
During the low temperature pretreatment stage, the first temperature ensures that the crust is not hardened such that the plasma during the low temperature pretreatment stage passes through the crust, weakening the adhesion between the crust and the photoresist pattern; the photoresist pattern and the crust are completely removed during the high temperature ashing stage.
And fifthly, carrying out wet cleaning to remove the polymer.
A further improvement is that the semiconductor substrate comprises a silicon substrate.
A further improvement is that the material of the top metal layer comprises Al.
The metal layers are isolated by interlayer films and connected by through holes.
A further improvement is that each of the bottom of the top metal layer has a material of the metal layer comprising copper.
The further improvement is that the time of the first etching is adjusted according to the thickness of the passivation layer, and the thicker the passivation layer is, the longer the time of the first etching is, and the more the residual quantity of the hard shell and the residual quantity of the polymer are.
A further improvement is that the passivation layer has a thickness ofThe above.
A further improvement is that the material of the passivation layer comprises silicon oxide or silicon nitride.
In a further development, the passivation layer is formed by laminating a first silicon oxide layer and a second silicon nitride layer.
In a further improvement, in the third step, the first inert gas includes argon.
In the third step, the fluorine-based gas is one gas or a mixed gas of a plurality of gases in CxFy, or SF6, or a mixed gas of one or a plurality of gases in CxFy and SF 6; x represents the number of carbon atoms in CxFy, and y represents the number of fluorine atoms in CxFy.
In a further improvement, in the fourth step, the first temperature is in the range of 80-180 ℃.
A further improvement is that the ashing process gas comprises: from a mixed gas of one or more gases selected from nitrogen, hydrogen, ammonia and N2H2 and oxygen.
The further improvement is that the time of the low-temperature pretreatment stage is longer according to the thickness of the passivation layer or the etching time of the first etching, and the larger the thickness of the passivation layer or the longer the etching time of the first etching is, the longer the time of the low-temperature pretreatment stage is.
Further improvement is that the time of the low temperature pretreatment stage is also adjusted in combination with the type and thickness of the photoresist pattern.
In the second step, the first etching further performs over etching on the top metal layer.
According to the invention, the first inert gas is added into the process gas of the post-etching treatment after the first etching of the passivation layer, the plasma concentration in the post-etching treatment is increased by using the first inert gas, and the weakening of the hard shell and the polymer which are by-product residues of the first etching is realized by using the element ions of the first inert gas, so that the subsequent removal of the hard shell and the polymer is facilitated; the invention also sets the initial stage of the ashing process as a low-temperature pretreatment stage, thus preventing the defects that the hard shell is hardened and the adhesion force between the hard shell and the photoresist is increased due to the high temperature when the ashing process enters the high-temperature ashing stage at the beginning, so that the invention can weaken the adhesion force between the hard shell and the photoresist pattern through the low-temperature pretreatment stage, thereby ensuring that the photoresist pattern is completely removed in the ashing process.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a schematic diagram of a device structure after a bonding pad is formed by a prior bonding pad manufacturing method;
FIG. 2 is a flow chart of a method of manufacturing a bonding pad according to an embodiment of the present invention;
FIGS. 3A-3D are schematic views of a device structure at various steps in a method of fabricating a bonding pad according to an embodiment of the present invention;
FIG. 4A is a photograph of a bond pad formed by a prior art bond pad fabrication method;
fig. 4B is a photograph of a pad formed by a method of manufacturing a pad according to an embodiment of the present invention.
Detailed Description
FIG. 2 is a flow chart of a method of manufacturing a bonding pad according to an embodiment of the present invention; as shown in fig. 3A to 3D, a schematic device structure at each step of the method for manufacturing a bonding pad according to an embodiment of the present invention is shown; the manufacturing method of the bonding pad comprises the following steps:
step one, as shown in fig. 3A, a passivation layer is formed on the surface of the semiconductor substrate where the top metal layer 206 is formed, and a photoresist pattern 210 is formed by performing a photolithography process, where the photoresist pattern 210 opens a pad region and covers the outside of the pad region.
In an embodiment of the present invention, the semiconductor substrate comprises a silicon substrate.
The material of the top metal layer 206 includes Al.
A plurality of metal layers 204 are further formed on the bottom of the top metal layer 206, and the metal layers 204 are isolated from each other by an interlayer film 201 and connected by a via 203. In fig. 3C, a silicon nitride layer 202 is further formed between the corresponding interlayer films 201. Fig. 3C shows the interlayer film 201 of 3 layers and the silicon nitride layer 202 of two layers in total.
Each layer of the material of the metal layer 204 at the bottom of the top metal layer 206 comprises copper.
In the embodiment of the present invention, the top metal layer 206 is generally connected to the bottom metal layer 204 through a top via 205 of the top interlayer film 201, and an adhesion barrier 209 is formed between the top via 205 and the bottom metal layer 204. In some embodiments, the adhesion barrier 209 is composed of Ti, tiN, and TaN superimposed. The material of the top metal layer 206 is the same as that of the top via 205.
In an embodiment of the present invention, the passivation layer has a thickness ofThe above. In contrast to the conventional processes of the prior art,the above thickness is a thicker thickness of the passivation layer, which is introduced for the purpose of cooperating with the subsequent packaging process. However, the increase in thickness of the passivation layer is detrimental to the subsequent first etching, and increases the time of the first etching and increases etching residues.
The material of the passivation layer comprises silicon oxide or silicon nitride. Preferably, the passivation layer is formed by stacking a first silicon oxide layer 207 and a second silicon nitride layer 208.
Step two, as shown in fig. 3A, performing a first etching with the photoresist pattern 210 as a mask, where the passivation layer in the pad area is removed by the first etching and a pad window 211 is formed, and the top metal layer 206 is exposed from the bottom surface of the pad window 211 and serves as a pad; the first etching simultaneously forms a carbon-silicon-based hard shell 301 on the surface of the photoresist pattern 210 and a silicon-based polymer 302 on the side surface of the pad window 211.
In this embodiment of the present invention, the time of the first etching is adjusted according to the thickness of the passivation layer, and the thicker the thickness of the passivation layer, the longer the time of the first etching, the more the residual amount of the hard shell 301 and the residual amount of the polymer 302.
In the embodiment of the present invention, the first etching further performs over etching on the top metal layer 206.
Step three, as shown in fig. 3B, performing post-etching treatment, wherein the process gas for the post-etching treatment includes: oxygen, a fluorine-based gas, and a first inert gas having an element with an atomic weight greater than an atomic weight of oxygen; increasing the plasma concentration in the post-etch treatment with the first inert gas and weakening the crust 301 and the polymer 302 with elemental ion bombardment of the first inert gas; in fig. 3B, each of the recessed areas indicated by reference numeral 303 is an area weakened by the elemental ion bombardment effect of the first inert gas.
In an embodiment of the present invention, the first inert gas includes argon.
In the embodiment of the invention, the fluorine-based gas is one gas or a mixed gas of a plurality of gases in CxFy, or SF6, or a mixed gas of one or a plurality of gases in CxFy and SF 6; x represents the number of carbon atoms in CxFy, and y represents the number of fluorine atoms in CxFy. CxFy represents a gas comprising x C and y F, such as: CF4, C2F6, C3F8, CHF3, CH2F4, and the like.
Step four, as shown in fig. 3C, an ashing process is performed to remove the photoresist pattern 210, and the ashing process is divided into a low temperature pretreatment stage and a high temperature ashing stage; the first temperature of the low temperature pretreatment stage is lower than the second temperature of the high temperature ashing stage.
During the low temperature pretreatment stage, the first temperature ensures that the crust 301 is not hardened such that the plasma during the low temperature pretreatment stage passes through the crust 301, weakening the adhesion between the crust 301 and the photoresist pattern 210; the photoresist pattern 210 and the crust 301 are completely removed during the high temperature ashing stage.
In the embodiment of the invention, the range of the first temperature is 80-180 ℃. The second temperature is usually 250 ℃ or higher.
The ashing process gas includes: from a mixed gas of one or more gases selected from nitrogen, hydrogen, ammonia and N2H2 and oxygen, i.e. O2+ N2, H2, NH3 and N2H 2.
The time of the low-temperature pretreatment stage is longer according to the thickness of the passivation layer or the etching time of the first etching, and the larger the thickness of the passivation layer or the longer the etching time of the first etching is, the longer the time of the low-temperature pretreatment stage is.
The time of the low temperature pretreatment stage is also adjusted in conjunction with the type of photoresist and the thickness of the photoresist pattern 210.
As can be seen from fig. 3C, the crust 301 can be completely removed during the high temperature ashing stage along with the photoresist pattern 210 after the elemental ion bombardment of the first inert gas during the post-etch treatment and after the low temperature pretreatment stage.
Step five, as shown in fig. 3D, a wet clean is performed to remove the polymer 302.
In the embodiment of the present invention, since the hard shell 301 is completely removed, the polymer 302 is weakened by the ion bombardment of the first inert gas element in the post-etching treatment, so that the polymer 302 can be completely removed in the wet cleaning.
Therefore, even if the thickness of the passivation layer is increasedThe above is a modification of the embodiment of the present inventionAfter the treatment, etching residues brought by the first etching can still be effectively removed.
According to the embodiment of the invention, the first inert gas is added into the process gas of the post-etching treatment after the first etching of the passivation layer, the plasma concentration in the post-etching treatment is increased by using the first inert gas, and the weakening of the hard shell 301 and the polymer 302 which are by-product residues of the first etching is realized by using the element ions of the first inert gas, so that the subsequent removal of the hard shell 301 and the polymer 302 is facilitated; the embodiment of the present invention also sets the initial stage of the ashing process to a low temperature pretreatment stage, so that the defect that the hard shell 301 is hardened and thus the adhesion between the hard shell 301 and the photoresist is increased due to the high temperature when the ashing process starts to enter the high temperature ashing stage can be prevented, and therefore, the embodiment of the present invention can weaken the adhesion between the hard shell 301 and the photoresist pattern 210 through the low temperature pretreatment stage, thereby ensuring that the photoresist pattern 210 is completely removed in the ashing process.
As shown in fig. 4A, a photograph of a pad formed by a conventional method of manufacturing a pad; the exposed top metal layer 106a within the pad window is a pad, and it can be seen that there is a polymer residue 110a on both the inner and outer surfaces of the pad.
As shown in fig. 4B, a photograph of a pad formed by the method for manufacturing a pad according to an embodiment of the present invention. The exposed top metal layer 206a within the pad window is the pad, and it can be seen that pentameric and residue remains on both the inner and outer surfaces of the pad.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (16)
1. A method of manufacturing a bonding pad, comprising the steps of:
forming a passivation layer on the surface of the semiconductor substrate with the top metal layer, and performing a photoetching process to form a photoresist pattern, wherein the photoresist pattern opens a bonding pad area and covers the outside of the bonding pad area;
step two, performing first etching by taking the photoresist pattern as a mask, wherein the passivation layer of the pad area is removed by the first etching, a pad window is formed, and the top metal layer is exposed from the bottom surface of the pad window and serves as a pad; forming a carbon-silicon-based hard shell on the surface of the photoresist pattern at the same time of the first etching, and forming a silicon-based polymer on the side surface of the bonding pad window;
step three, carrying out post-etching treatment, wherein the post-etching treatment process gas comprises the following components: oxygen, a fluorine-based gas, and a first inert gas having an element with an atomic weight greater than an atomic weight of oxygen; increasing a plasma concentration in the post-etch treatment with the first inert gas and weakening the crust and the polymer with elemental ion bombardment of the first inert gas;
step four, carrying out an ashing process to remove the photoresist pattern, and dividing the ashing process into a low-temperature pretreatment stage and a high-temperature ashing stage; the first temperature of the low temperature pretreatment stage is lower than the second temperature of the high temperature ashing stage;
during the low temperature pretreatment stage, the first temperature ensures that the crust is not hardened such that the plasma during the low temperature pretreatment stage passes through the crust, weakening the adhesion between the crust and the photoresist pattern; completely removing the photoresist pattern and the crust during the high temperature ashing stage;
and fifthly, carrying out wet cleaning to remove the polymer.
2. The method of manufacturing a bonding pad according to claim 1, wherein: the semiconductor substrate includes a silicon substrate.
3. The method of manufacturing a bonding pad according to claim 1, wherein: the material of the top metal layer comprises Al.
4. A method of manufacturing a bonding pad according to claim 3, wherein: and a plurality of metal layers are formed at the bottom of the top metal layer, and the metal layers are isolated through interlayer films and connected through holes.
5. The method of manufacturing a bonding pad according to claim 4, wherein: each layer of material of the metal layer at the bottom of the top metal layer comprises copper.
6. The method of manufacturing a bonding pad according to claim 1, wherein: the time of the first etching is adjusted according to the thickness of the passivation layer, and the thicker the passivation layer is, the longer the time of the first etching is, and the more the residual quantity of the hard shell and the residual quantity of the polymer are.
7. The method of manufacturing a bonding pad according to claim 6, wherein: the thickness of the passivation layer isThe above.
8. The method of manufacturing a bonding pad according to claim 1, wherein: the material of the passivation layer comprises silicon oxide or silicon nitride.
9. The method of manufacturing a bonding pad according to claim 8, wherein: the passivation layer is formed by laminating a first silicon oxide layer and a second silicon nitride layer.
10. The method of manufacturing a bonding pad according to claim 1, wherein: in the third step, the first inert gas includes argon.
11. The method of manufacturing a bonding pad according to claim 1, wherein: in the third step, the fluorine-based gas is one gas or a mixed gas of a plurality of gases in CxFy, or SF6, or a mixed gas of one or a plurality of gases in CxFy and SF 6; x represents the number of carbon atoms in CxFy, and y represents the number of fluorine atoms in CxFy.
12. The method of manufacturing a bonding pad according to claim 1, wherein: in the fourth step, the first temperature is 80-180 ℃.
13. The method of manufacturing a bonding pad according to claim 12, wherein: the ashing process gas includes: from a mixed gas of one or more gases selected from nitrogen, hydrogen, ammonia and N2H2 and oxygen.
14. The method of manufacturing a bonding pad according to claim 12, wherein: the time of the low-temperature pretreatment stage is longer according to the thickness of the passivation layer or the etching time of the first etching, and the larger the thickness of the passivation layer or the longer the etching time of the first etching is, the longer the time of the low-temperature pretreatment stage is.
15. The method of manufacturing a bonding pad according to claim 14, wherein: the time of the low temperature pretreatment stage is also adjusted in combination with the type and thickness of the photoresist pattern.
16. The method of manufacturing a bonding pad according to claim 1, wherein: in the second step, the first etching further performs over etching on the top metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311085926.0A CN117096035A (en) | 2023-08-25 | 2023-08-25 | Method for manufacturing bonding pad |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311085926.0A CN117096035A (en) | 2023-08-25 | 2023-08-25 | Method for manufacturing bonding pad |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117096035A true CN117096035A (en) | 2023-11-21 |
Family
ID=88773404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311085926.0A Pending CN117096035A (en) | 2023-08-25 | 2023-08-25 | Method for manufacturing bonding pad |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117096035A (en) |
-
2023
- 2023-08-25 CN CN202311085926.0A patent/CN117096035A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7192878B2 (en) | Method for removing post-etch residue from wafer surface | |
| US20100091424A1 (en) | Method for reducing sidewall etch residue | |
| US20120220132A1 (en) | Semiconductor device manufacturing method | |
| JPH10154712A (en) | Manufacturing method of semiconductor device | |
| JPH07201834A (en) | Dry etching method | |
| US20070093069A1 (en) | Purge process after dry etching | |
| US6743725B1 (en) | High selectivity SiC etch in integrated circuit fabrication | |
| CN117096035A (en) | Method for manufacturing bonding pad | |
| KR101037485B1 (en) | Method for Forming Metal Line of Semiconductor Device | |
| KR20070042887A (en) | Method for forming feature definitions | |
| US6740471B1 (en) | Photoresist adhesion improvement on metal layer after photoresist rework by extra N2O treatment | |
| JP4948278B2 (en) | Manufacturing method of semiconductor device | |
| JPH1064916A (en) | Method for manufacturing metal wiring of semiconductor device | |
| KR100190498B1 (en) | Etching method for polysilicon film | |
| KR100461743B1 (en) | Method For Plasma Etching Of Ir-Ta-O Electrode And For Post-Etch Cleaning | |
| JPH05109702A (en) | Manufacture of semiconductor device | |
| KR100559132B1 (en) | Semiconductor and manufacturing method for preventing to contaminate bonding pad | |
| KR100613573B1 (en) | Method for manufacturing a semiconductor device | |
| JP2001332510A (en) | Semiconductor and its manufacturing method | |
| KR100814259B1 (en) | Method of manufacturing semiconductor device | |
| KR100652285B1 (en) | Method for removing photoresist residue | |
| JP4380414B2 (en) | Manufacturing method of semiconductor device | |
| KR100802307B1 (en) | Method of etching metal layer | |
| US10381264B2 (en) | Process for producing connections to an electronic chip | |
| TW415013B (en) | Method for fabricating shallow trench isolation capable of reducing the residues |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |