CN117096010A - Memory manufacturing method and memory - Google Patents
Memory manufacturing method and memory Download PDFInfo
- Publication number
- CN117096010A CN117096010A CN202310400152.XA CN202310400152A CN117096010A CN 117096010 A CN117096010 A CN 117096010A CN 202310400152 A CN202310400152 A CN 202310400152A CN 117096010 A CN117096010 A CN 117096010A
- Authority
- CN
- China
- Prior art keywords
- barrier layer
- memory
- layer
- substrate
- control unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title abstract description 18
- 230000004888 barrier function Effects 0.000 claims abstract description 232
- 239000002245 particle Substances 0.000 claims abstract description 138
- 238000002161 passivation Methods 0.000 claims abstract description 127
- 239000000463 material Substances 0.000 claims description 58
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 40
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 37
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 37
- 239000010703 silicon Substances 0.000 claims description 33
- 229910052710 silicon Inorganic materials 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 31
- 239000004065 semiconductor Substances 0.000 claims description 26
- VQCBHWLJZDBHOS-UHFFFAOYSA-N erbium(iii) oxide Chemical compound O=[Er]O[Er]=O VQCBHWLJZDBHOS-UHFFFAOYSA-N 0.000 claims description 20
- 229910044991 metal oxide Inorganic materials 0.000 claims description 20
- 150000004706 metal oxides Chemical class 0.000 claims description 20
- 229910052757 nitrogen Inorganic materials 0.000 claims description 20
- 239000011856 silicon-based particle Substances 0.000 claims description 19
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 9
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 9
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 9
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 8
- 239000005360 phosphosilicate glass Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims 4
- 239000000758 substrate Substances 0.000 abstract description 181
- 239000001257 hydrogen Substances 0.000 abstract description 113
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 113
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 107
- 238000003860 storage Methods 0.000 abstract description 38
- 238000010438 heat treatment Methods 0.000 abstract description 19
- 238000000034 method Methods 0.000 description 57
- 238000009792 diffusion process Methods 0.000 description 35
- 239000000470 constituent Substances 0.000 description 21
- 230000000694 effects Effects 0.000 description 21
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 17
- 238000006243 chemical reaction Methods 0.000 description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 12
- 238000001755 magnetron sputter deposition Methods 0.000 description 12
- 239000001301 oxygen Substances 0.000 description 12
- 229910052760 oxygen Inorganic materials 0.000 description 12
- 230000000903 blocking effect Effects 0.000 description 10
- 239000010408 film Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 10
- 239000012212 insulator Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920006395 saturated elastomer Polymers 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 239000000376 reactant Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 230000004913 activation Effects 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000013077 target material Substances 0.000 description 4
- -1 SOI) Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- DYCJFJRCWPVDHY-LSCFUAHRSA-N NBMPR Chemical compound O[C@@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C2=NC=NC(SCC=3C=CC(=CC=3)[N+]([O-])=O)=C2N=C1 DYCJFJRCWPVDHY-LSCFUAHRSA-N 0.000 description 1
- GEIAQOFPUVMAGM-UHFFFAOYSA-N Oxozirconium Chemical compound [Zr]=O GEIAQOFPUVMAGM-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
Abstract
The embodiment of the disclosure discloses a manufacturing method of a memory and the memory, wherein the manufacturing method of the memory comprises the following steps: forming a passivation layer on a first substrate having a memory cell; the storage unit is positioned on the first surface of the first substrate, the passivation layer is positioned on the second surface of the first substrate, and the second surface of the first substrate is the opposite surface of the first substrate; forming a first barrier layer having a first dangling bond on a second surface of the first substrate and on the passivation layer; carrying out heat treatment on the passivation layer at a preset temperature; wherein hydrogen particles in the passivation layer are released to the first barrier layer and combine with the first dangling bond to form a first covalent bond.
Description
The application relates to a method for manufacturing a memory and a division application of a Chinese application patent application of which the application date is 2020, 01, 02, 202010002802.1 and the application name is memory.
Technical Field
The embodiment of the disclosure relates to the field of integrated circuits, in particular to a manufacturing method of a memory and the memory.
Background
As feature sizes of semiconductor manufacturing processes become smaller, memory storage densities become higher. By providing a memory prepared by a plurality of memory cells along a direction perpendicular to the stacked structure, the degree of integration on the wafer can be improved, an improvement in memory density can be realized, and the cost can be reduced.
In the preparation process of the memory, as lattice defects exist in the memory cells, the memory cells need to be passivated to remove the defects in the memory cells, so that the quality of the memory is ensured. In the related art, the passivation effect of the memory cell is poor, and it is difficult to ensure the quality of the memory.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a method for manufacturing a memory and the memory.
According to a first aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a memory, including:
forming a passivation layer on a first substrate having a memory cell; the storage unit is positioned on the first surface of the first substrate, the passivation layer is positioned on the second surface of the first substrate, and the second surface of the first substrate is the opposite surface of the first substrate;
forming a first barrier layer having a first dangling bond on a second surface of the first substrate and on the passivation layer;
Carrying out heat treatment on the passivation layer at a preset temperature; wherein hydrogen particles in the passivation layer are released to the first barrier layer and combine with the first dangling bond to form a first covalent bond.
Optionally, forming a first blocking layer with a first dangling bond on the second surface of the first substrate and on the passivation layer includes:
forming the first barrier layer with the first dangling bond on the passivation layer by using a magnetron sputtering method;
or,
the first barrier layer having the first dangling bond is formed on the passivation layer by using a plasma enhanced chemical vapor deposition method.
Optionally, the method further comprises:
forming a second barrier layer having a second dangling bond on a second substrate having a control unit; wherein the control unit and the second barrier layer are both located on the first surface of the second substrate, and the control unit is located between the second barrier layer and the first surface of the second substrate;
bonding the second substrate having the second barrier layer with the first substrate having the passivation layer and the first barrier layer;
after the first substrate and the second substrate are bonded, an electrical connection is formed between the control unit and the storage unit, and the control unit is used for controlling the storage unit in the first substrate to store data;
The heat treatment of the passivation layer at a preset temperature includes:
carrying out the heat treatment on the bonded first substrate and second substrate at the preset temperature; wherein hydrogen particles in the passivation layer are also released to the second barrier layer and combine with the second dangling bond to form a second covalent bond.
Optionally, the forming a second barrier layer with a second dangling bond on a second substrate with a control unit includes:
forming the second barrier layer with the second dangling bond on the second substrate by using a magnetron sputtering method;
or,
and forming the second barrier layer with the second dangling bond on the second substrate by using a plasma enhanced chemical vapor deposition method.
Optionally, the method further comprises:
forming a conductive layer on a first surface of the second substrate having the control unit; wherein the control unit is located between the conductive layer and the first surface of the second substrate;
forming a third barrier layer on the conductive layer; wherein the third blocking layer is used for blocking the conductive layer from diffusing to the first substrate after the first substrate and the second substrate are bonded;
The forming a second barrier layer having a second dangling bond on a second substrate having a control unit includes:
forming the second barrier layer with the second dangling bond on the third barrier layer; wherein the third barrier layer is located between the conductive layer and the second barrier layer.
According to a second aspect of embodiments of the present disclosure, there is provided a memory comprising:
a first substrate having memory cells; wherein the storage unit is positioned on the first surface of the first substrate;
a first barrier layer on a second surface of the first substrate having a first covalent bond; wherein the second surface of the first substrate is an opposite surface of the first substrate;
a passivation layer between the second surface of the first substrate and the first barrier layer;
wherein the first covalent bond is formed by bonding a dangling bond contained in the first barrier layer before the passivation layer is thermally treated and hydrogen particles released in the passivation layer thermal treatment.
Optionally, the material comprising the first barrier layer comprises: silicon nitride; wherein the ratio of silicon particles to nitrogen particles in the first barrier layer is greater than a preset threshold;
Or,
the materials comprising the first barrier layer include: a metal oxide.
Optionally, the memory further comprises:
a second substrate having a control unit bonded to the first substrate having the passivation layer and the first barrier layer; the control unit is positioned on the first surface of the second substrate, and is electrically connected with the storage unit and used for controlling the storage unit in the first substrate to store data;
a second barrier layer located on the first surface of the second substrate and between the first surface of the first substrate and the control unit, having a second covalent bond;
wherein the second covalent bond is formed by bonding a second dangling bond contained in the second barrier layer before bonding the first substrate and the second substrate with hydrogen particles generated in the passivation layer heat treatment.
Optionally, the material comprising the second barrier layer includes: silicon nitride; wherein the ratio of silicon particles to nitrogen particles in the second barrier layer is greater than a preset threshold;
or,
the materials constituting the second barrier layer include: a metal oxide.
Optionally, the memory further comprises:
a conductive layer on the first surface of the second substrate;
and the third barrier layer is positioned between the conductive layer and the second barrier layer and is used for blocking the conductive layer from diffusing to the first substrate.
In the related art, when a first substrate on which a passivation layer is formed is subjected to heat treatment, a part of hydrogen particles released by the passivation layer are diffused into a memory cell formed on the first substrate, so that passivation of the memory cell is realized; another part of the hydrogen particles released from the passivation layer may diffuse into the environment where the first substrate is located, so that the number of hydrogen particles that can be used to passivate the memory cell is reduced, and it is difficult to ensure the passivation effect.
In an embodiment of the disclosure, a first barrier layer having a first dangling bond is formed on a passivation layer such that the barrier layer separates the passivation layer from an external environment. When the passivation layer is subjected to heat treatment, hydrogen particles released in the passivation layer can be combined with a first dangling bond in the first barrier layer to form a first covalent bond, so that the probability of diffusion of the hydrogen particles to the external environment is reduced, the probability of diffusion of the hydrogen particles released in the passivation layer to the storage unit is increased, the passivation effect on the storage unit is improved, the yield and the reliability of the memory are improved, and the quality of the memory is improved.
Drawings
FIG. 1 is a flow chart of a method for manufacturing a memory according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a memory according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another memory according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a further memory according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a further memory according to an embodiment of the present invention;
fig. 6a to fig. 6b are partial flowcharts of a method for manufacturing a memory according to an embodiment of the invention.
Detailed Description
The technical scheme of the invention will be further elaborated with reference to the drawings and examples. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. The advantages and features of the present disclosure will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the disclosure.
In the embodiments of the present disclosure, the term "a is connected to B" includes a case where a is connected to B while A, B is in contact with each other, or a case where A, B is further interposed between the two while a is connected to B without contact.
In the presently disclosed embodiments, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The technical solutions described in the embodiments of the present disclosure may be arbitrarily combined without any conflict.
Fig. 1 is a flow chart illustrating a method of fabricating a memory according to an exemplary embodiment. Referring to fig. 1, the manufacturing method includes the steps of:
s100: forming a passivation layer on a first substrate having a memory cell; the memory cell is positioned on the first surface of the first substrate, the passivation layer is positioned on the second surface of the first substrate, and the second surface of the first substrate is the opposite surface of the first substrate;
s110: forming a first barrier layer having a first dangling bond on a second surface of the first substrate and on the passivation layer;
s120: carrying out heat treatment on the passivation layer at a preset temperature; wherein the hydrogen particles in the passivation layer are released to the first barrier layer and combine with the first dangling bond to form a first covalent bond.
The first substrate is a semiconductor material formed with a plurality of memory cells, such as silicon, silicon-on-insulator (Silicon On Insulator, SOI), or silicon germanium-on-insulator (S-SiGeOI). The first substrate may include a multi-layer structure thereon, for example, may include: a type of insulating layer such as silicon oxide, silicon nitride, or tetraethyl orthosilicate (TEOS); semiconductor layers of single crystal silicon, polycrystalline silicon, and the like; metal wiring layers, and the like.
A memory cell typically includes a polysilicon (Poly-Si) layer and a silicon dioxide layer. Since silicon ions have 4 dangling bonds, even after the silicon ions are oxidized to form oxides, some dangling bonds remain. Thus, at the interface of silicon and silicon dioxide, dangling bonds of silicon may exist. The existence of the dangling bond can cause short circuit in the memory unit, and the yield and reliability of the memory are affected.
Illustratively, dangling bonds in a memory cell may be passivated by bonding free hydrogen particles (H) to dangling bonds in the memory cell to create a covalent bond. Thus, the passivation layer is a material that can release free hydrogen particles for passivating dangling bonds in the memory cell. In general, the passivation layer may include: silicon nitride, phosphosilicate glass, and the like.
Illustratively, taking the example that the constituent material of the passivation layer includes silicon nitride, S100 may include: introducing a first reactant containing nitrogen (such as ammonia NH) into the cavity of the first substrate 3 ) And a second reactant containing elemental silicon (e.g., silane SiH 4 ) The first reactant is reacted with the second reactant and a silicon nitride film is deposited on the second surface of the first substrate by chemical vapor deposition (Chemical Vapor Deposition, CVD).
Since the raw material for forming the silicon nitride film contains a large amount of hydrogen particles, the hydrogen particles formed by ionization enter the silicon nitride film to form silicon-hydrogen bonds (Si-H bonds) with the silicon particles and nitrogen-hydrogen bonds (N-H bonds) with the nitrogen particles. Therefore, after the formation of the silicon nitride film, it is also necessary to activate the hydrogen particles remaining in the silicon nitride film by heat treatment so that the hydrogen particles acquire sufficient energy to be released from the silicon-hydrogen bond and the nitrogen-hydrogen bond, thereby becoming free hydrogen particles.
The hydrogen particles in the free state can diffuse from the silicon nitride film to the memory unit, bond with the dangling bonds in the memory unit to form covalent bonds, realize passivation effect on the memory unit, reduce the number of dangling bonds in the memory unit, and be favorable for improving the yield and reliability of the memory.
However, in the actual manufacturing process, the free hydrogen particles may also diffuse into the external environment where the first substrate is located. And, when the passivation layer is heat-treated, the diffusion rate of hydrogen particles into the external environment is increased. Therefore, under the condition that the quantity of hydrogen particles released by the passivation layer is kept unchanged, the released hydrogen particles can escape to the external environment, so that the quantity of hydrogen particles which can be used for passivating the memory cell is reduced, and a plurality of dangling bonds remain in the memory cell, thereby influencing the yield and the reliability of the memory.
In S110, the constituent material of the first barrier layer may include any material capable of providing a first dangling bond. Wherein the first dangling bond is a chemical bond which is not in a saturated state. When a particle in the crystal has at least one electron in the outermost layer that is not paired to form an electron pair, the particle has a chemical bond that is not in a saturated state, i.e., has a first dangling bond.
The constituent materials of the first barrier layer may include: silicon nitride; wherein the ratio of silicon particles to nitrogen particles in the first barrier layer is greater than a preset threshold; or a metal oxide.
When the composition material of the first barrier layer is silicon nitride, the ratio of silicon particles to nitrogen particles in the first barrier layer is greater than a preset threshold, i.e., the first barrier layer is a silicon-rich silicon nitride layer. Here, the preset threshold may include 0.75, 1, 1.5, 2, or the like. At this time, the first barrier layer may provide dangling bonds of silicon, i.e., the first dangling bonds are dangling bonds of silicon.
When the constituent material of the first barrier layer is a metal oxide, the first barrier layer may provide dangling bonds of oxygen, i.e., the first dangling bond is a dangling bond of oxygen.
Illustratively, the metal oxide comprising the first barrier layer may comprise: alumina (Al) 2 O 3 ) Erbium oxide (Er) 2 O 3 ) Yttria (Y) 2 O 3 ) Zirconium oxide (ZrO) 2 ) Etc.
According to the embodiment of the disclosure, by forming the first barrier layer with the first dangling bond, on one hand, the first barrier layer with the first dangling bond can be bonded with hydrogen particles released in the passivation layer to form the first covalent bond, so that the hydrogen particles in the first covalent bond cannot continue to diffuse into an external environment, and the probability of the diffusion of the hydrogen particles into the external environment can be reduced by the first barrier layer.
On the other hand, after the hydrogen particles and the first dangling bond in the first barrier layer form a first covalent bond, the hydrogen particles in the first covalent bond occupy the position between the lattices in the first barrier layer, so that the gaps between the lattices in the first barrier layer are reduced. Therefore, when other free hydrogen particles need to diffuse into the external environment through the reduced lattice spacing in the first barrier layer, the free hydrogen particles need to have higher diffusion activation energy to continue to diffuse from the reduced lattice spacing into the external environment. I.e. the first barrier layer further reduces the probability of diffusion of hydrogen particles to the environment.
Because the difficulty of diffusion of the free hydrogen particles from the passivation layer to the external environment through the first barrier layer is increased, compared with diffusion to the external environment, the diffusion of the free hydrogen particles from the passivation layer to the first barrier layer can be turned to diffuse to the storage unit, namely, the first barrier layer increases the diffusion probability of the released hydrogen particles in the passivation layer to the storage unit, thereby being beneficial to improving the passivation effect on the storage unit, improving the yield and reliability of the storage and improving the quality of the storage.
S120 may include: and annealing the passivation layer at a preset temperature.
For example, S120 may include: heating the passivation layer to a preset range of 300-500 ℃, keeping the passivation layer in the temperature range for 30 minutes, and then cooling and the like.
By performing heat treatment on the passivation layer, the hydrogen particles in the passivation layer can be activated, so that the hydrogen particles obtain enough energy to be separated from the silicon-hydrogen bond and the nitrogen-hydrogen bond, and become free hydrogen particles. The free hydrogen particles can diffuse into the memory cell, passivating dangling bonds in the memory cell.
In an embodiment of the disclosure, a first barrier layer having a first dangling bond is formed on a passivation layer such that the barrier layer separates the passivation layer from an external environment. When the passivation layer is subjected to heat treatment, hydrogen particles released in the passivation layer can be combined with a first dangling bond in the first barrier layer to form a first covalent bond, so that the probability of diffusion of the hydrogen particles to the external environment is reduced, the probability of diffusion of the hydrogen particles released in the passivation layer to the storage unit is increased, the passivation effect on the storage unit is improved, the yield and the reliability of the memory are improved, and the quality of the memory is improved.
In some embodiments, S110 may include:
forming a first barrier layer with a first dangling bond on the passivation layer by using a magnetron sputtering method;
or,
a first barrier layer having a first dangling bond is formed on the passivation layer using a plasma enhanced chemical vapor deposition method.
For example, taking the case that the constituent material of the first barrier layer is silicon nitride having a ratio of silicon particles to nitrogen particles greater than a preset threshold, S110 may include: by means of plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), ammonia (NH) is introduced into the reaction chamber in which the first substrate is located 3 ) With Silane (SiH) 4 ) Activated to form nitrogen particles, hydrogen particles and silicon particles, and the nitrogen particles and the silicon particles formed by activation are adsorbed on the surface of the passivation layer to perform chemical reaction to form the first barrier layer.
The plasma enhanced chemical vapor deposition method mainly utilizes glow discharge to activate particles in reactants, so that the activated particles undergo chemical vapor deposition. In the plasma formed by glow discharge, the mass of electrons and ions are greatly different, and the process of exchanging energy through collision is relatively slow, so that the temperature of the plasma is not high from a macroscopic view. Thus, chemical reactions that would otherwise need to be carried out at high temperatures can be carried out at lower temperatures, even at ambient temperatures.
As another example, taking the first barrier layer as a constituent material of alumina, S110 may include: and using aluminum as a target material and oxygen as a reaction gas, controlling argon particles to bombard the aluminum target material under the action of an electric field, and enabling the bombarded aluminum particles to react with the oxygen particles and deposit on the surface of the passivation layer to form the aluminum oxide film.
The reaction temperature has a large influence on the performance of the memory. In general, the excessive reaction temperature can cause memory failure, and the yield and reliability of the memory are affected.
Compared with the formation of the first barrier layer by using other high-temperature processes, the first barrier layer with the first dangling bond is formed by the plasma enhanced chemical vapor deposition method or the magnetron sputtering method, the reaction temperature for forming the first barrier layer with the first dangling bond is reduced on the premise that the first barrier layer with the first dangling bond can be normally formed, the yield and the reliability of the memory are guaranteed, and the cost is reduced.
In some embodiments, the method further comprises:
forming a second barrier layer having a second dangling bond on a second substrate having a control unit; the control unit and the second barrier layer are both positioned on the first surface of the second substrate, and the control unit is positioned between the second barrier layer and the first surface of the second substrate;
Bonding a second substrate having a second barrier layer to a first substrate having a passivation layer and a first barrier layer;
after the first substrate and the second substrate are bonded, an electrical connection is formed between the control unit and the storage unit, and the control unit is used for controlling the storage unit in the first substrate to store data;
s120 may include:
performing heat treatment on the bonded first substrate and second substrate at a preset temperature; wherein the hydrogen particles in the passivation layer are also released to the second barrier layer and combine with the second dangling bonds to form a second covalent bond.
The control unit may include: a switching device composed of field-effect transistors (MOSFETs).
The second substrate may comprise a semiconductor material having a control unit, for example: silicon, silicon-on-insulator, or silicon germanium-on-insulator, etc.
The constituent material of the second barrier layer may include any material capable of providing a second dangling bond. The second dangling bond can be similar to the first dangling bond, and is a chemical bond which is not in a saturated state.
The constituent materials of the second barrier layer may include: silicon nitride; wherein the ratio of silicon particles to nitrogen particles in the second barrier layer is greater than a preset threshold; or a metal oxide.
When the composition material of the second barrier layer is silicon nitride, the ratio of silicon particles to nitrogen particles in the second barrier layer is greater than a preset threshold, i.e., the second barrier layer is a silicon-rich silicon nitride layer. In this case, the second barrier layer may provide dangling bonds of silicon, i.e. the second dangling bonds are dangling bonds of silicon.
When the constituent material of the second barrier layer is a metal oxide, the second barrier layer may provide dangling bonds of oxygen, i.e., the second dangling bonds are dangling bonds of oxygen.
Illustratively, the metal oxide comprising the second barrier layer may include: alumina, erbium oxide, yttrium oxide, zirconium oxide, and the like.
When the bonded first and second substrates are heat treated, hydrogen particles released from the passivation layer may not only diffuse to the memory cells but also attempt to diffuse to the control cells on the second substrate. If hydrogen particles enter the control unit, the performance of the control unit is affected, and the memory is disabled.
For example, if hydrogen particles enter the gate oxide layer of the control unit, damage is caused to the gate oxide layer, and the gate performance of the gate oxide layer is reduced, resulting in the occurrence of negative bias temperature instability (NBTI: negative Bias Temperature Instability) effect and hot carrier (Hot Carrier Injection) effect, which affect the on-current (I) on ) Closing current (I) off ) And subthreshold swing (Subthreshold Swing, SS) and other parameters, thereby reducing the switching performance of the field effect transistor and affecting the reliability of the field effect transistor.
In this embodiment, by forming the second barrier layer with the second dangling bond so that the control unit is located between the second barrier layer and the first surface of the second substrate, on one hand, the second barrier layer with the second dangling bond may bond with the hydrogen particles released in the passivation layer to form a second covalent bond, so that the hydrogen particles in the second covalent bond cannot continue to diffuse to the control unit. I.e. the second barrier layer may reduce the probability of diffusion of hydrogen particles to the control unit.
On the other hand, after the hydrogen particles form the second covalent bond with the second dangling bond in the second barrier layer, the hydrogen particles in the second covalent bond occupy the positions between the lattices in the second barrier layer, so that the gaps between the lattices in the second barrier layer are reduced. Thus, when other free hydrogen particles need to diffuse through the reduced lattice spacing control element in the second barrier layer, the free hydrogen particles need to have a higher diffusion activation energy. I.e. the second barrier layer further reduces the probability of diffusion of hydrogen particles to the control unit.
Because the difficulty of diffusing the free hydrogen particles to the control unit through the second barrier layer is increased, compared with diffusing the free hydrogen particles to the control unit, the diffusion of the free hydrogen particles to the storage unit from the passivation layer to the second barrier layer is turned, namely, the probability of diffusing the free hydrogen particles released in the passivation layer to the storage unit is increased by the second barrier layer, the passivation effect on the storage unit is improved, the yield and the reliability of the memory are improved, and the quality of the memory is improved.
And, the second barrier layer can co-act with the first barrier layer to produce a pressure cooker effect (Pressure Cooker Effect), which increases the concentration of hydrogen particles accumulated in the memory cells, is beneficial to improving the passivation effect on the memory cells, improving the yield and reliability of the memory, and improving the quality of the memory.
In some embodiments, the forming a second barrier layer having a second dangling bond on a second substrate having a control unit includes:
forming a second barrier layer with a second dangling bond on a second substrate by using a magnetron sputtering method;
or,
a second barrier layer having a second dangling bond is formed on the second substrate using a plasma enhanced chemical vapor deposition method.
For example, taking the example that the constituent material of the second barrier layer is silicon nitride with a ratio of silicon particles to nitrogen particles greater than a preset threshold, the method for forming the second barrier layer may include: and activating ammonia and silane in the reaction cavity where the first substrate is positioned by introducing plasma to form nitrogen particles and silicon particles, and adsorbing the nitrogen particles and the silicon particles formed by activation on the surface of the control unit to perform chemical reaction to form the second barrier layer.
As another example, taking the aluminum oxide as the constituent material of the second barrier layer as an example, the method of forming the second barrier layer may include: aluminum is used as a target material, oxygen is used as a reaction gas, argon particles are controlled to bombard the aluminum target material under the action of an electric field, and the bombarded aluminum particles react with oxygen particles and are deposited on the surface of the control unit to form the aluminum oxide film.
Compared with the formation of the second barrier layer by using other high-temperature processes, the second barrier layer with the second dangling bond is formed by the plasma enhanced chemical vapor deposition method or the magnetron sputtering method, the reaction temperature for forming the second barrier layer with the second dangling bond is reduced on the premise that the second barrier layer with the second dangling bond can be normally formed, the yield and the reliability of the memory are guaranteed, and the cost is reduced.
In some embodiments, the method further comprises:
forming a conductive layer on a first surface of a second substrate having a control unit; wherein the control unit is positioned between the conductive layer and the first surface of the second substrate;
forming a third barrier layer on the conductive layer; the third barrier layer is used for blocking the conductive layer from diffusing to the first substrate after the first substrate and the second substrate are bonded;
the forming a second barrier layer having a second dangling bond on a second substrate having a control unit includes:
forming a second barrier layer having a second dangling bond on the third barrier layer; wherein the third barrier layer is located between the conductive layer and the second barrier layer.
When the first substrate is bonded to the second substrate, the gate, source and drain of the field effect transistor on the second substrate may be electrically connected to the memory cell on the first substrate through the conductive layer, enabling signal transmission between the first and second substrates.
The composition materials of the conductive layer may include: a conductive metal. Such as copper, tungsten, or aluminum, etc.
It will be appreciated that the first substrate is typically formed with a metal interconnect in an insulating layer on the surface of the memory cell, with one end of the metal interconnect being electrically connected to the memory cell. When the first substrate and the second substrate are bonded, the first substrate and the second substrate are electrically connected by forming a through hole penetrating through the second barrier layer and the third barrier layer and forming a conductive column in the through hole and connecting a metal wire on the first substrate and the conductive layer on the second substrate through the conductive column.
Taking copper as an example of the constituent material of the conductive layer. After the first substrate and the second substrate are bonded, some process flows with higher reaction temperature may exist, so that copper diffuses into an insulating layer on the first substrate, and the reliability of the memory is affected.
The constituent materials of the third barrier layer may include: silicon nitride. The method of forming the third barrier layer may include: plasma enhanced chemical vapor deposition, magnetron sputtering, and the like.
In practical applications, the thickness of the third barrier layer is smaller than the thickness of the first barrier layer. Therefore, at higher temperatures, the third barrier layer releases less hydrogen particles. Typically, a small number of dangling bonds will also be present in the control unit, and therefore, hydrogen particles released by the third barrier layer may bond with dangling bonds in the control unit, passivating dangling bonds in the control unit without affecting the performance of the control unit.
The third barrier layer may also block diffusion of hydrogen particles released in the passivation layer to the control unit, for example. The third barrier layer may also block diffusion of hydrogen particles in the second substrate formed with the control unit to the first substrate formed with the memory unit.
Fig. 2 is a schematic diagram of a memory 100, according to an example embodiment. Referring to fig. 2, the memory 100 includes:
A first substrate 110 having a memory cell 111; wherein the storage unit 111 is located on the first surface of the first substrate 110;
a first barrier layer 112 having a first covalent bond on a second surface of the first substrate 110; wherein the second surface of the first substrate is an opposite surface of the first substrate;
a passivation layer 113 between the second surface of the first substrate and the first barrier layer;
wherein the first covalent bond is formed by bonding a dangling bond contained in the first barrier layer before the passivation layer is heat-treated and hydrogen particles released during the passivation layer heat treatment.
The memory 100 may include a three-dimensional memory (3D memory), such as a 3D NAND flash memory.
The first substrate 110 is a semiconductor material formed with a plurality of memory cells, for example, silicon-on-insulator, silicon germanium-on-insulator, or the like. The first substrate may include a multi-layer structure thereon, for example, may include: an insulating layer of the type silicon oxide, silicon nitride, or tetraethyl orthosilicate; semiconductor layers of single crystal silicon, polycrystalline silicon, and the like; metal wiring layers, and the like.
The constituent materials of the first barrier layer 112 may include any material capable of providing a first dangling bond. Wherein the first dangling bond is a chemical bond which is not in a saturated state. Illustratively, when a particle in the crystal has at least one electron in the outermost layer that is not paired to form an electron pair, the particle has a chemical bond that is not in a saturated state, i.e., has a first dangling bond.
In some embodiments, the materials comprising the first barrier layer 112 include: silicon nitride; wherein the ratio of silicon particles to nitrogen particles in the first barrier layer 112 is greater than a preset threshold;
or,
the materials comprising the first barrier layer 112 include: a metal oxide.
When the constituent material of the first barrier layer 112 is silicon nitride, the ratio of silicon particles to nitrogen particles in the first barrier layer 112 is greater than a predetermined threshold, i.e., the first barrier layer 112 is a silicon-rich silicon nitride layer. Here, the preset threshold may include 0.75, 1, 1.5, 2, or the like. At this time, the first barrier layer 112 may provide dangling bonds of silicon, i.e., the first dangling bond is a dangling bond of silicon.
When the constituent material of the first barrier layer 112 is a metal oxide, the first barrier layer 112 may provide dangling bonds of oxygen, i.e., the first dangling bonds are dangling bonds of oxygen.
Illustratively, the metal oxide comprising the first barrier layer 112 may include: alumina, erbium oxide, yttrium oxide, zirconium oxide, and the like.
According to the embodiment of the disclosure, the hydrogen particles released by the passivation layer and the first suspension in the first barrier layer form the first covalent bond, so that the hydrogen particles in the first covalent bond cannot continue to diffuse into an external environment on one hand.
On the other hand, after the hydrogen particles and the first dangling bond in the first barrier layer form a first covalent bond, the hydrogen particles in the first covalent bond occupy the position between the lattices in the first barrier layer, so that the gaps between the lattices in the first barrier layer are reduced. Thus, the first barrier layer further reduces the probability of diffusion of hydrogen particles to the external environment.
Because the difficulty of diffusion of the free hydrogen particles from the passivation layer to the external environment through the first barrier layer is increased, compared with diffusion to the external environment, the diffusion of the free hydrogen particles from the passivation layer to the first barrier layer can be turned to diffuse to the storage unit, the probability of diffusion of the free hydrogen particles released in the passivation layer to the storage unit is increased, the passivation effect on the storage unit is improved, and the yield and reliability of the storage are improved.
The passivation layer 113 is a material that can release free hydrogen particles. In general, the passivation layer 113 may include: silicon nitride, phosphosilicate glass, and the like.
In the embodiment of the disclosure, the passivation layer is separated from the external environment by disposing the first blocking layer with the first covalent bond on the passivation layer. The first blocking layer with the first covalent bond reduces the probability of diffusion of hydrogen particles to the external environment, increases the probability of diffusion of the hydrogen particles released in the passivation layer to the storage unit, is beneficial to improving the passivation effect on the storage unit and improves the yield and reliability of the memory.
In some embodiments, as shown with reference to fig. 4, memory 100 may further include:
a second substrate 120 having a control unit bonded to the first substrate 110 having the passivation layer 113 and the first barrier layer 112; the control unit is located on the first surface of the second substrate 120, and is electrically connected with the storage unit 111, and is used for controlling the storage unit in the first substrate to store data;
a second barrier layer 121 located on the first surface of the second substrate and between the first surface of the first substrate and the control unit, having a second covalent bond;
wherein the second covalent bond is formed by bonding the second dangling bond contained in the second barrier layer before the bonding of the first substrate and the second substrate with hydrogen particles generated in the heat treatment of the passivation layer.
The control unit may include: a switching device comprising a field effect transistor.
The second substrate 120 may include a semiconductor material having a control unit, for example: silicon, silicon-on-insulator, or silicon germanium-on-insulator, etc.
The constituent material of the second barrier layer 121 may include any material capable of providing a second dangling bond. The second dangling bond can be similar to the first dangling bond, and is a chemical bond which is not in a saturated state.
In some embodiments, the materials comprising the second barrier layer 121 include: silicon nitride; wherein the ratio of silicon particles to nitrogen particles in the second barrier layer is greater than a preset threshold;
or,
the materials constituting the second barrier layer 121 include: a metal oxide.
When the constituent material of the second barrier layer 121 is silicon nitride, the ratio of silicon particles to nitrogen particles in the second barrier layer 121 is greater than a predetermined threshold, i.e., the second barrier layer 121 is a silicon-rich silicon nitride layer. Here, the preset threshold may include 0.75, 1, 1.5, 2, or the like. In this case, the second barrier layer may provide dangling bonds of silicon, i.e. the second dangling bonds are dangling bonds of silicon.
When the constituent material of the second barrier layer 121 is a metal oxide, the second barrier layer 121 may provide dangling bonds of oxygen, i.e., the second dangling bonds are dangling bonds of oxygen.
Illustratively, the metal oxide comprising the second barrier layer 121 may include: alumina, erbium oxide, yttrium oxide, zirconium oxide, and the like.
In this embodiment, the second covalent bond is formed by the second dangling bond in the second barrier layer and the hydrogen particles released by the passivation layer, so that, on the one hand, the hydrogen particles in the second covalent bond cannot continue to diffuse to the control unit. I.e. the second barrier layer may reduce the probability of diffusion of hydrogen particles to the control unit.
On the other hand, the hydrogen particles in the second covalent bond occupy the sites between the lattices in the second barrier layer, so that the gaps between the lattices in the second barrier layer are reduced. Thus, the second barrier layer further reduces the probability of diffusion of hydrogen particles to the control unit.
Because the difficulty of diffusing the free hydrogen particles to the control unit through the second barrier layer is increased, compared with diffusing the free hydrogen particles to the control unit, the hydrogen particles diffused to the second barrier layer from the passivation layer can be turned to diffuse to the storage unit, so that the probability of diffusing the released hydrogen particles to the storage unit in the passivation layer is increased, the passivation effect on the storage unit is improved, and the yield and reliability of the memory are improved.
And moreover, the second barrier layer can work together with the first barrier layer to generate a pressure cooker effect, so that the concentration of hydrogen particles accumulated in the storage unit is increased, the passivation effect on the storage unit is improved, and the yield and the reliability of the memory are improved.
In some embodiments, memory 100 further comprises:
a conductive layer 122 on the first surface of the second substrate;
and a third barrier layer 123 between the conductive layer and the second barrier layer for blocking diffusion of the conductive layer toward the first substrate.
The composition materials of the conductive layer may include: a conductive metal. Such as copper, tungsten, or aluminum, etc.
The constituent materials of the third barrier layer 123 may include: silicon nitride, and the like.
In practical applications, the thickness of the third barrier layer 123 is smaller than the thickness of the first barrier layer 112. Therefore, at higher temperatures, the content of hydrogen particles released in the third barrier layer 123 is smaller. Typically, a small number of dangling bonds will also be present in the control unit, and therefore, hydrogen particles released by the third barrier layer may bond with dangling bonds in the control unit, passivating dangling bonds in the control unit without affecting the performance of the control unit.
For example, the third barrier layer 123 may block diffusion of hydrogen particles released from the passivation layer to the control unit. The third barrier layer 123 may also block diffusion of hydrogen particles in the second substrate formed with the control unit to the first substrate formed with the memory unit.
In some embodiments, as shown with reference to fig. 3, memory 100 may include:
a first substrate 110 having a memory cell 111; wherein the storage unit 111 is located on the first surface of the first substrate 110;
a passivation layer 113 on the second surface of the first substrate;
a second substrate 120 having a control unit, which is attached to the first substrate 110 having the passivation layer 113 and the first barrier layer 112; the control unit is located on the first surface of the second substrate 120, and is electrically connected with the storage unit 111, and is used for controlling the storage unit in the first substrate to store data;
A second barrier layer 121 located on the first surface of the second substrate and between the first surface of the first substrate and the control unit, having a second covalent bond;
wherein the second covalent bond is formed by bonding the second dangling bond contained in the second barrier layer before the bonding of the first substrate and the second substrate with hydrogen particles generated in the heat treatment of the passivation layer.
In order to facilitate understanding of the technical solution of the embodiments of the present invention, the following examples are provided.
By bonding a first substrate including a plurality of memory cells and a second substrate having a field effect transistor, a three-dimensional memory such as a 3D NAND flash (flash) of an X-charging structure can be formed.
During the fabrication of the memory, a polysilicon channel is formed in the memory cell of the first substrate, where dangling bonds are present at the interface of the polysilicon channel and silicon dioxide. In order to passivate the dangling bonds, after the first and second substrates are bonded, hydrogen particles are provided through a passivation layer prepared by a plasma enhanced chemical vapor deposition method, and the hydrogen particles are diffused from the passivation layer to an array (array) region where the memory cells are located and bonded to the dangling bonds.
FIG. 5 is a schematic diagram of a memory shown according to an exemplary embodiment. During passivation, hydrogen particles also pass through the passivation layer, the array region where the memory cells are located, the bonding interface Of the first and second substrates, the Back End Of Line (BEOL) layer Of the second substrate, and the front End Of Line (Front End Of Line, FEOL) layer Of the second substrate in sequence. Referring to fig. 5, the third barrier layer 123 may serve to block diffusion of hydrogen particles from the bonding interface into the second substrate, but has a very limited blocking effect.
The present example provides a method for manufacturing a memory, for forming a memory as shown in fig. 2, comprising the following steps:
after the first substrate 110 having the memory cells 111 and the second substrate having the control cells are bonded, a passivation layer 113 is formed on the first substrate 110; the memory cell 111 is located on a first surface of the first substrate 110, the passivation layer 113 is located on a second surface of the first substrate 110, and the second surface of the first substrate 110 is an opposite surface of the first substrate 110;
forming a first barrier layer 112 having a first dangling bond on a second surface of the first substrate 110 and on the passivation layer 113;
performing a heat treatment on the passivation layer 113 at a preset temperature; wherein hydrogen particles in the passivation layer 113 are released to the first barrier layer 112 and combine with the first dangling bonds to form a first covalent bond.
Therefore, compared with the method of preparing the first barrier layer with the first dangling bond by the common chemical vapor deposition, the method adopts the plasma enhanced chemical vapor deposition method or the magnetron sputtering method to form the first barrier layer with the first dangling bond, so that the reaction temperature can be reduced, the reliability of the rear-end interconnection line layer is ensured, and the yield and the reliability of the memory are further ensured.
After the first substrate 110 and the second substrate 120 are bonded, by forming the first barrier layer 112, the diffusion of the hydrogen particles released in the passivation layer to the external environment can be blocked, the probability of diffusing the hydrogen particles to the memory cell is increased, the passivation effect on the memory cell is improved, and the yield and reliability of the memory are further improved.
The present example also provides another method for manufacturing a memory, for forming a memory as shown in fig. 3, including the following steps:
referring to fig. 6a, a third barrier layer 123 is formed on the second substrate 120 having the control unit;
referring to fig. 6b, a second barrier layer 121 having a second dangling bond is formed on the third barrier layer 123;
bonding the second substrate 120 formed with the second barrier layer 121 with the first substrate 110 having the memory cells 111, and forming a passivation layer 113 on the second surface of the first substrate 110;
carrying out heat treatment on the bonded first substrate and second substrate at a preset temperature; wherein the hydrogen particles in the passivation layer are released to the second barrier layer and combine with the second dangling bond to form a second covalent bond.
The constituent materials of the second barrier layer having the second dangling bond may include: silicon-rich (Si-rich) nitride films, aluminum oxide, erbium oxide, yttrium oxide, zirconium oxide, or the like.
Specifically, the silicon-rich nitride film may be formed by a plasma enhanced chemical vapor deposition method. Alternatively, the alumina, erbium oxide, yttrium oxide, or zirconium oxide thin film is formed by a magnetron sputtering method.
In practical applications, the reaction temperature of conventional chemical vapor deposition may be 700 ℃. The temperature of the plasma enhanced chemical vapor deposition method can be 300 ℃ or 400 ℃, and the reaction temperature of the magnetron sputtering method is normal temperature.
Therefore, compared with the common chemical vapor deposition method for preparing the second barrier layer with the second dangling bond, the second barrier layer with the second dangling bond is formed by adopting the plasma enhanced chemical vapor deposition method or the magnetron sputtering method in the embodiment, the reaction temperature can be reduced, the reliability of the rear-end interconnection line layer is ensured, and the yield and the reliability of the memory are further ensured.
After the first substrate 110 and the second substrate 120 are bonded, the diffusion of hydrogen particles released from the passivation layer to the second substrate having the control unit can be blocked by the second blocking layer 121 between the first substrate 110 and the second substrate 120, and the reliability of the control unit can be improved.
And the second barrier layer is formed after the control unit on the second substrate is formed, so that the process method is simple, the process is easy to control, and the compatibility with the process in the prior art is strong.
The present example also provides another method for manufacturing a memory, for forming a memory as shown in fig. 4, including the steps of:
forming a third barrier layer 123 on the second substrate 120 having the control unit;
forming a second barrier layer 121 having a second dangling bond on the third barrier layer 123;
bonding the second substrate 120 formed with the second barrier layer 121 with the first substrate 110 having the memory cells 111;
and forming a passivation layer 113 on the second surface of the first substrate 110; the memory cell 111 is located on a first surface of the first substrate 110, the passivation layer 113 is located on a second surface of the first substrate 110, and the second surface of the first substrate 110 is an opposite surface of the first substrate 110;
forming a first barrier layer 112 having a first dangling bond on a second surface of the first substrate 110 and on the passivation layer 113;
performing a heat treatment on the passivation layer 113 at a preset temperature; wherein hydrogen particles in the passivation layer 113 are released to the first barrier layer 112 and combine with the first dangling bonds to form a first covalent bond.
Therefore, compared with the method of preparing the first barrier layer with the first dangling bond by the common chemical vapor deposition, the method adopts the plasma enhanced chemical vapor deposition method or the magnetron sputtering method to form the first barrier layer with the first dangling bond, so that the reaction temperature can be reduced, the reliability of the rear-end interconnection line layer is ensured, and the yield and the reliability of the memory are further ensured.
After the first substrate 110 and the second substrate 120 are bonded, by forming the first barrier layer 112, the diffusion of the hydrogen particles released in the passivation layer to the external environment can be blocked, the probability of diffusing the hydrogen particles to the memory cell is increased, the passivation effect on the memory cell is improved, and the yield and reliability of the memory are further improved.
By the second barrier layer 121 between the first substrate 110 and the second substrate 120, diffusion of hydrogen particles released in the passivation layer to the second substrate having the control unit can be blocked, and reliability of the control unit can be improved.
And the second barrier layer is formed after the control unit on the second substrate is formed, so that the process method is simple, the process is easy to control, and the compatibility with the process in the prior art is strong.
In addition, by the combined action of the first barrier layer 112 and the second barrier layer 121, an autoclave effect is generated, the concentration of hydrogen particles accumulated in the memory cell is increased, and the passivation effect on the memory cell is further improved, the yield and reliability of the memory are improved, and the quality of the memory is improved.
In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus, system and method may be implemented in other manners. The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (20)
1. A memory, comprising:
a first semiconductor layer;
a memory cell located at a first side of the first semiconductor layer;
a passivation layer located on a second side of the first semiconductor layer, the second side being disposed opposite to the first side along a thickness direction of the first semiconductor layer;
a first barrier layer located on one side of the passivation layer away from the first semiconductor layer;
the first barrier layer comprises silicon-rich silicon nitride, wherein the proportion of silicon particles to nitrogen particles in the first barrier layer is larger than a preset threshold value;
or,
the first barrier layer includes a metal oxide.
2. The memory of claim 1, the first barrier layer comprising silicon-rich silicon nitride, the preset threshold being 0.75, 1, 1.5, or 2.
3. The memory of claim 1, the first barrier layer comprising a metal oxide comprising at least one of aluminum oxide, erbium oxide, yttrium oxide, zirconium oxide.
4. The semiconductor device of claim 1, further comprising a second barrier layer located on a side of the memory cell remote from the first semiconductor layer.
5. The memory of claim 4, the material composition of the second barrier layer being the same as the material composition of the first barrier layer.
6. The memory of claim 4, the second barrier layer comprising a metal oxide comprising at least one of aluminum oxide, erbium oxide, yttrium oxide, zirconium oxide.
7. The memory of claim 4, the second barrier layer comprising silicon-rich silicon nitride, the preset threshold being 0.75, 1, 1.5, or 2.
8. The memory of claim 4, further comprising a second semiconductor layer and a control unit on the second semiconductor layer, the control unit being located between the second semiconductor layer and the second barrier layer, the control unit being located on a side of the second barrier layer remote from the memory unit, the control unit being connected to the memory unit.
9. The memory of claim 8, further comprising a third barrier layer, the third barrier layer being located between the second barrier layer and the control unit.
10. The memory of claim 1, the passivation layer comprising silicon nitride or phosphosilicate glass.
11. A memory, comprising:
a first semiconductor layer;
a memory cell located at a first side of the first semiconductor layer;
a passivation layer located on a second side of the first semiconductor layer, the second side being disposed opposite to the first side along a thickness direction of the first semiconductor layer;
A first material layer located on one side of the memory cell away from the first semiconductor layer;
the first material layer comprises silicon-rich silicon nitride, wherein the proportion of silicon particles to nitrogen particles in the first material layer is larger than a preset threshold value;
or,
the first material layer comprises a metal oxide.
12. The memory of claim 11, the first material layer comprising silicon-rich silicon nitride, the preset threshold being 0.75, 1, 1.5, or 2.
13. The memory of claim 11, the first material layer comprising a metal oxide comprising at least one of aluminum oxide, erbium oxide, yttrium oxide, zirconium oxide.
14. The memory of claim 11, further comprising a second semiconductor layer and a control unit on the second semiconductor layer, the control unit being located between the second semiconductor layer and the first material layer, the control unit being located on a side of the first material layer remote from the memory unit, the control unit being connected to the memory unit.
15. The memory of claim 14, further comprising a second material layer located between the first material layer and the control unit.
16. The memory of claim 11, further comprising a third material layer located on a side of the passivation layer remote from the first semiconductor layer.
17. The memory of claim 16, the third material layer having a material composition that is the same as a material composition of the first material layer.
18. The memory of claim 16, the third material layer comprising a metal oxide comprising at least one of aluminum oxide, erbium oxide, yttrium oxide, zirconium oxide.
19. The memory of claim 16, the third material layer comprising silicon-rich silicon nitride, the preset threshold being 0.75, 1, 1.5, or 2.
20. The memory of claim 11, the passivation layer comprising silicon nitride or phosphosilicate glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310400152.XA CN117096010A (en) | 2020-01-02 | 2020-01-02 | Memory manufacturing method and memory |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310400152.XA CN117096010A (en) | 2020-01-02 | 2020-01-02 | Memory manufacturing method and memory |
| CN202010002802.1A CN111162002B (en) | 2020-01-02 | 2020-01-02 | Memory manufacturing method and memory |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010002802.1A Division CN111162002B (en) | 2020-01-02 | 2020-01-02 | Memory manufacturing method and memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117096010A true CN117096010A (en) | 2023-11-21 |
Family
ID=70561308
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310400152.XA Pending CN117096010A (en) | 2020-01-02 | 2020-01-02 | Memory manufacturing method and memory |
| CN202010002802.1A Active CN111162002B (en) | 2020-01-02 | 2020-01-02 | Memory manufacturing method and memory |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010002802.1A Active CN111162002B (en) | 2020-01-02 | 2020-01-02 | Memory manufacturing method and memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN117096010A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112909007B (en) * | 2021-03-24 | 2022-05-10 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of manufacturing the same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5229311A (en) * | 1989-03-22 | 1993-07-20 | Intel Corporation | Method of reducing hot-electron degradation in semiconductor devices |
| JP4212299B2 (en) * | 2002-05-09 | 2009-01-21 | 株式会社東芝 | Nonvolatile semiconductor memory device |
| CN100517655C (en) * | 2006-12-08 | 2009-07-22 | 中芯国际集成电路制造(上海)有限公司 | SONOS flash memory and production method thereof |
| US10468413B2 (en) * | 2018-04-06 | 2019-11-05 | Sandisk Technologies Llc | Method for forming hydrogen-passivated semiconductor channels in a three-dimensional memory device |
| CN109473435B (en) * | 2018-11-21 | 2020-09-18 | 长江存储科技有限责任公司 | Semiconductor device and manufacturing method thereof |
-
2020
- 2020-01-02 CN CN202310400152.XA patent/CN117096010A/en active Pending
- 2020-01-02 CN CN202010002802.1A patent/CN111162002B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN111162002B (en) | 2023-05-09 |
| CN111162002A (en) | 2020-05-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100452440C (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
| CN100446182C (en) | A method of fabricating a composite substrate with improved electrical properties | |
| JPS61137367A (en) | Manufacture of semiconductor integrated circuit device | |
| JPS6245712B2 (en) | ||
| JP2002299612A (en) | Semiconductor device and method for manufacturing it | |
| JP4909552B2 (en) | Method for manufacturing nonvolatile semiconductor memory element having excellent charge retention characteristics | |
| JPS63132434A (en) | Semiconductor device and manufacture thereof | |
| CN111162002B (en) | Memory manufacturing method and memory | |
| CN111128721A (en) | Memory manufacturing method and memory | |
| JPH10209147A (en) | Manufacture of semiconductor device | |
| JP2014501045A (en) | Integrated circuit hydrogen passivation | |
| US7300862B2 (en) | Method for manufacturing semiconductor device | |
| JP3515351B2 (en) | Method for manufacturing semiconductor device | |
| JP2000216165A (en) | Manufacture of semiconductor device | |
| US7535047B2 (en) | Semiconductor device containing an ultra thin dielectric film or dielectric layer | |
| JPH1197683A (en) | Semiconductor device and manufacture thereof | |
| JP2914282B2 (en) | Method for manufacturing semiconductor device | |
| US7329589B2 (en) | Method for manufacturing silicon-on-insulator wafer | |
| KR100528446B1 (en) | Fabricating method of bit line contact in semiconductor device | |
| US20060134925A1 (en) | Method of forming a gate insulating layer of a semiconductor device using deuterium gas | |
| JP3840965B2 (en) | Manufacturing method of semiconductor device | |
| KR20120089147A (en) | Manufacturing method of semiconductor device | |
| JP4213250B2 (en) | Manufacturing method of semiconductor device | |
| JPH0712085B2 (en) | Method for manufacturing insulated gate field effect semiconductor device | |
| JP2573137B2 (en) | Method for manufacturing insulated gate field effect transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |