CN117081407A - Self-adaptive synchronous rectification circuit - Google Patents

Self-adaptive synchronous rectification circuit Download PDF

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Publication number
CN117081407A
CN117081407A CN202211458985.3A CN202211458985A CN117081407A CN 117081407 A CN117081407 A CN 117081407A CN 202211458985 A CN202211458985 A CN 202211458985A CN 117081407 A CN117081407 A CN 117081407A
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CN
China
Prior art keywords
npn triode
base
synchronous rectification
npn
nmos
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CN202211458985.3A
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Chinese (zh)
Inventor
夏月锦
瞿鹏
任杰
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Nanjing Huneng Electronic Technology Co ltd
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Nanjing Huneng Electronic Technology Co ltd
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Priority to CN202211458985.3A priority Critical patent/CN117081407A/en
Publication of CN117081407A publication Critical patent/CN117081407A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)

Abstract

The application relates to a self-adaptive synchronous rectification circuit, which belongs to the technical field of synchronous rectification, and comprises a first NMOS (N-channel metal oxide semiconductor) transistor Q1 and a control module, wherein the control module comprises a first resistor R1, a second resistor R2 and a first NPN triode T1, and the first NMOS transistor Q1 is connected in series between a load and a power supply to be rectified; one end of the first resistor R1 is connected with the working voltage Vcc, and the other end of the first resistor R1 is connected with the collector electrode of the first NPN triode T1; one end of the second resistor R2 is connected with the working voltage Vcc, and the other end of the second resistor R2 is connected with the base electrode of the first NPN triode T1; the emitter of the first NPN triode T1 is connected with the source of the first NMOS tube Q1, the base of the first NPN triode T1 is connected with the drain of the first NMOS tube Q1, and the collector of the first NPN triode T1 is connected with the grid of the first NMOS tube Q1; the first NMOS Q1 is configured to turn on when a forward voltage drop exists between the source and the drain, and turn off when a reverse voltage drop exists between the source and the drain. By adopting the application, the self-adaptive synchronous rectification can be realized based on a simple circuit structure.

Description

Self-adaptive synchronous rectification circuit
Technical Field
The application relates to the technical field of synchronous rectification, in particular to a self-adaptive synchronous rectification circuit.
Background
The rectifier circuit is a circuit capable of converting ac power into dc power, and may be generally disposed between an ac power source and an electronic device to convert ac power into dc power, and provide the dc power to the electronic device after filtering. The most basic rectifying circuit can utilize the unidirectional conductivity of the PN junction on the rectifying diode to realize the rectification of alternating current, when the PN junction has forward voltage, the PN junction is conducted, the current can smoothly pass, and when the PN junction is loaded with reverse voltage, the PN junction is cut off, and the current cannot pass.
The synchronous rectification circuit is a new rectification circuit based on the rectification circuit, and adopts a power tube with extremely low resistance in a conducting state to replace a rectification diode so as to reduce the electric energy loss generated during rectification, thereby improving the conversion efficiency and reducing the heating of a power supply. The power tube is a circuit component which needs external control, synchronous control is needed to be carried out on the power tube according to the switching time sequence of the rectified power supply in the rectification process, and if the control cannot be accurately synchronous, the synchronous rectification circuit is invalid, so that the rectification stability is poor.
Disclosure of Invention
In order to solve the problems that a synchronous rectification control circuit in the prior art is relatively complex and unreliable in stability, and a rectification effect cannot be well realized if a control logic is disordered, the embodiment of the application provides a self-adaptive synchronous rectification circuit, which comprises the following technical scheme:
the self-adaptive synchronous rectification circuit comprises a first NMOS tube Q1 and a control module, wherein the control module comprises a first resistor R1, a second resistor R2 and a first NPN triode T1, and the self-adaptive synchronous rectification circuit comprises the following components:
the drain electrode and the source electrode of the first NMOS tube Q1 are connected between the power input and the reference grounding end;
one end of the first resistor R1 is connected with the working voltage Vcc, and the other end of the first resistor R1 is connected with the collector electrode of the first NPN triode T1;
one end of the second resistor R2 is connected with the working voltage Vcc, and the other end of the second resistor R2 is connected with the base electrode of the first NPN triode T1;
the emitter of the first NPN triode T1 is connected with the source of the first NMOS tube Q1, the base of the first NPN triode T1 is connected with the drain of the first NMOS tube Q1, and the collector of the first NPN triode T1 is connected with the grid of the first NMOS tube Q1;
the first NMOS Q1 is configured to turn on when a forward voltage drop exists between the source and the drain, and turn off when a reverse voltage drop exists between the source and the drain.
In one possible implementation, the higher the source voltage of the first NMOS transistor Q1, the smaller the voltage difference Vbe between the base and the emitter of the first NPN transistor T1, the smaller the current Ic of the collector of the first NPN transistor T1, and the larger the gate voltage of the first NMOS transistor Q1.
In a possible implementation manner, the control module further includes a first diode D1, where one end of the first diode D1 is connected to the base of the first NPN triode T1, and the other end is connected to the drain of the first NMOS tube Q1.
In a possible embodiment, the conduction voltage drop of the first diode D1 is equal to the conduction voltage drop between the base and the emitter of the first NPN transistor T1.
In a possible implementation manner, the control module further includes a second NPN triode T2, an emitter and a base of the second NPN triode T2 are connected to the base of the first NPN triode T1, and a collector of the second NPN triode T2 is connected to the drain of the first NMOS tube Q1.
In a possible embodiment, the conduction voltage drop between the base and the collector of the second NPN triode T2 is equal to the conduction voltage drop between the base and the emitter of the first NPN triode T1.
In a possible implementation manner, the adaptive synchronous rectification circuit further includes a signal amplification module, an input end of the signal amplification module is connected to a collector of the first NPN triode T1, and an output end of the signal amplification module is connected to a gate of the first NMOS tube Q1.
In a possible embodiment, the signal amplifying module includes a third NPN transistor T3 and a fourth PNP transistor T4, wherein:
the collector of the third NPN triode T3 is connected with the working voltage Vcc, the emitter of the third NPN triode T3 is connected with the emitter of the fourth PNP triode T4, the collector of the fourth PNP triode T4 is connected with the source of the first NMOS tube Q1, and the base of the third NPN triode T3 is connected with the base of the fourth PNP triode T4;
the base of the third NPN triode T3 is an input end of the signal amplifying module, and the emitter of the third NPN triode T3 is an output end of the signal amplifying module.
In summary, the application has the following beneficial effects:
by adopting the technical scheme, the first resistor R1, the second resistor R2 and the first NPN triode T1 form a control module of the first NMOS tube Q1, and the control module and the first NMOS tube Q1 form a self-adaptive synchronous rectification circuit. In this way, when there is a forward voltage drop between the source and the drain, the gate of the first NMOS transistor Q1 is loaded with a high level, the first NMOS transistor Q1 is turned on, and when there is a reverse voltage drop between the source and the drain, the gate of the first NMOS transistor Q1 is loaded with a low level, and the first NMOS transistor Q1 is turned off, so that adaptive synchronous rectification can be implemented based on the above-mentioned simple circuit structure, without setting a complex control circuit and control logic for the first NMOS transistor Q1.
Drawings
FIG. 1 is a schematic diagram of an adaptive synchronous rectification circuit according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an adaptive synchronous rectification circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an adaptive synchronous rectification circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an adaptive synchronous rectification circuit according to an embodiment of the present application;
FIG. 5 is a schematic diagram of an adaptive synchronous rectification circuit according to an embodiment of the present application;
reference numerals illustrate: 1. a control module; 2. and a signal amplifying module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings 1 to 5 and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In the prior art, an MOS tube is adopted as a rectifying device in the synchronous rectifier, the internal resistance of a general MOS tube is very small, the conduction voltage drop of the MOS tube is far smaller than the forward conduction voltage drop of a common Schottky diode under the condition of the same current flowing, and the loss power of the MOS tube is far smaller than that of the diode, so that the efficiency of synchronous rectification can be higher. However, the MOS tube needs a driving circuit, and a control circuit needs to be additionally added to the MOS tube in the synchronous rectification circuit, so that the on-off state of the MOS tube can be synchronous with the power supply to be rectified, the control circuit for synchronous rectification is relatively complex, the stability is unreliable, and if the control logic is chaotic, the rectification effect cannot be well realized.
Aiming at the problems in the prior art, the embodiment of the application provides a self-adaptive synchronous rectification circuit which can be used for realizing the self-adaptive synchronous rectification function without setting a complex control circuit. Referring to fig. 1, the adaptive synchronous rectification circuit includes a first NMOS Q1 and a control module 1, where the first NMOS Q1 is used as a synchronous rectification switch, and a drain electrode and a source electrode of the first NMOS Q1 are connected between a power input and a reference ground terminal, and the control module 1 is a control side of the first NMOS Q1 and is configured to provide a control voltage to a gate electrode of the first NMOS Q1, so as to implement on and off of the first NMOS Q1.
The control module 1 may include a first resistor R1, a second resistor R2, and a first NPN triode T1, where one end of the first resistor R1 is connected to a working voltage Vcc, the other end of the first resistor R1 is connected to a collector c of the first NPN triode T1, one end of the second resistor R2 is connected to the working voltage Vcc, and the other end of the second resistor R2 is connected to a base b of the first NPN triode T1.
The emitter e of the first NPN triode T1 is connected with the source s of the first NMOS tube Q1, the base b of the first NPN triode T1 is connected with the drain d of the first NMOS tube Q1, and the collector c of the first NPN triode T1 is connected with the grid g of the first NMOS tube Q1.
Thus, when a forward voltage drop is applied between the source s and the drain d of the first NMOS transistor Q1, that is, vs is greater than Vd, there is a high level at the gate of the first NMOS transistor Q1, the first NMOS transistor Q1 is turned on, and when a reverse voltage drop is applied between the source s and the drain d of the first NMOS transistor Q1, that is, vd is greater than Vs, a low level is applied at the gate of the first NMOS transistor Q1, and the first NMOS transistor Q1 is turned off.
Specifically, as the source voltage of the first NMOS transistor Q1 is higher, the voltage difference Vbe between the base and the emitter of the first NPN transistor T1 is smaller, and as the conduction characteristic of the transistor is smaller, the current Ic at the collector of the first NPN transistor T1 is smaller, and the gate voltage of the corresponding first NMOS transistor Q1 is larger, so that the first NMOS transistor Q1 tends to be turned on more.
Further, as shown in fig. 2, the control module 1 may further include a first diode D1, where one end of the first diode D1 is connected to the base of the first NPN triode T1, and the other end is connected to the drain of the first NMOS tube Q1.
It can be understood that, the first diode D1 is added in the control module 1, and the conduction voltage drop of the first diode D1 can be set equal to the conduction voltage drop between the base and the emitter of the first NPN triode T1 at the same time, so that the conduction voltage drops of the base and the emitter of the first NPN triode T1 cancel each other, thereby reducing the influence of the conduction voltage drop between the base and the emitter of the first NPN triode T1 on the synchronous rectification process.
In another embodiment, as shown in fig. 3, a triode may be used to replace the function of the first diode D1 in fig. 2, specifically, the control module 1 further includes a second NPN triode T2, an emitter and a base of the second NPN triode T2 are connected with the base of the first NPN triode T1, and a collector of the second NPN triode T2 is connected with the drain of the first NMOS transistor Q1. In this way, because the second NPN triode T2 is adopted, on one hand, when the drain voltage of the first NMOS transistor Q1 is greater than Vcc, the voltage-withstanding performance between the collector c and the base b of the second NPN triode T2 is higher, and not easy to conduct reversely, on the other hand, because the base and the emitter of the first NPN triode T1 and the base and the collector of the second NPN triode T2 are both single PN junctions, the two NPN triodes can be packaged in the same package, the voltage drops at the two places can offset each other, and the temperature drift effects are identical, so that the influence of the conduction voltage drop between the base and the emitter of the first NPN triode T1 on the synchronous rectification process can be reduced.
Further, if the conduction voltage drops between the base and the emitter of the first NPN triode T1 and between the base and the collector of the second NPN triode T2 are not uniform, the resistance values of the first resistor R1 and the second resistor R2 may be adjusted until the conduction voltage drops of the PN junctions between the two NPN triodes are uniform. Specifically, if the resistance of the second resistor R2 is smaller than that of the first resistor R1, the current Ic at the collector of the first NPN transistor T1 is larger, and thus the voltage difference Vbe between the base and the emitter of the first NPN transistor T1 is larger.
Optionally, as shown in fig. 4, the adaptive synchronous rectification circuit further includes a signal amplification module 2, an input end of the signal amplification module 2 is connected to a collector of the first NPN triode T1, an output end of the signal amplification module 2 is connected to a gate of the first NMOS transistor Q1, and the signal amplification module 2 may be configured to amplify a voltage at the collector of the first NPN triode T1.
Further, as shown in fig. 5, the signal amplifying module 2 may be a class ab amplifier, where the signal amplifying module 2 includes a third NPN triode T3 and a fourth PNP triode T4, and the specific structure thereof is as follows: the collector of the third NPN triode T3 is connected with the working voltage Vcc, the emitter of the third NPN triode T3 is connected with the emitter of the fourth PNP triode T4, the collector of the fourth PNP triode T4 is connected with the source of the first NMOS tube Q1, and the base of the third NPN triode T3 is connected with the base of the fourth PNP triode T4; the base electrode of the third NPN triode T3 is the input end of the signal amplifying module 2, and the emitter electrode of the third NPN triode T3 is the output end of the signal amplifying module 2.
By adopting the technical scheme, the first resistor R1, the second resistor R2 and the first NPN triode T1 form the control module 1 of the first NMOS tube Q1, and the control module 1 and the first NMOS tube Q1 form the self-adaptive synchronous rectification circuit. In this way, when there is a forward voltage drop between the source and the drain, the gate of the first NMOS transistor Q1 is loaded with a high level, the first NMOS transistor Q1 is turned on, and when there is a reverse voltage drop between the source and the drain, the gate of the first NMOS transistor Q1 is loaded with a low level, and the first NMOS transistor Q1 is turned off, so that adaptive synchronous rectification can be implemented based on the above-mentioned simple circuit structure, without setting a complex control circuit and control logic for the first NMOS transistor Q1.
The foregoing description of the preferred embodiments of the application is not intended to limit the scope of the application in any way, including the abstract and drawings, in which case any feature disclosed in this specification (including abstract and drawings) may be replaced by alternative features serving the same, equivalent purpose, unless expressly stated otherwise. That is, each feature is one example only of a generic series of equivalent or similar features, unless expressly stated otherwise.

Claims (8)

1. The utility model provides a self-adaptation synchronous rectification circuit, its characterized in that, self-adaptation synchronous rectification circuit includes first NMOS pipe Q1 and control module, control module includes first resistance R1, second resistance R2 and first NPN triode T1, wherein:
the drain electrode and the source electrode of the first NMOS tube Q1 are connected between the power input and the reference grounding end;
one end of the first resistor R1 is connected with the working voltage Vcc, and the other end of the first resistor R1 is connected with the collector electrode of the first NPN triode T1;
one end of the second resistor R2 is connected with the working voltage Vcc, and the other end of the second resistor R2 is connected with the base electrode of the first NPN triode T1;
the emitter of the first NPN triode T1 is connected with the source of the first NMOS tube Q1, the base of the first NPN triode T1 is connected with the drain of the first NMOS tube Q1, and the collector of the first NPN triode T1 is connected with the grid of the first NMOS tube Q1;
the first NMOS Q1 is configured to turn on when a forward voltage drop exists between the source and the drain, and turn off when a reverse voltage drop exists between the source and the drain.
2. The adaptive synchronous rectification circuit according to claim 1, wherein the higher the source voltage of the first NMOS transistor Q1, the smaller the voltage difference Vbe between the base and the emitter of the first NPN transistor T1, the smaller the current Ic of the collector of the first NPN transistor T1, and the larger the gate voltage of the first NMOS transistor Q1.
3. The adaptive synchronous rectification circuit according to claim 1, wherein said control module further comprises a first diode D1, one end of said first diode D1 is connected to a base of said first NPN transistor T1, and the other end is connected to a drain of said first NMOS transistor Q1.
4. The adaptive synchronous rectification circuit of claim 3, wherein a conduction voltage drop of said first diode D1 is equal to a conduction voltage drop between a base and an emitter of said first NPN transistor T1.
5. The adaptive synchronous rectification circuit according to claim 1, wherein said control module further comprises a second NPN triode T2, an emitter and a base of said second NPN triode T2 are connected to a base of said first NPN triode T1, and a collector of said second NPN triode T2 is connected to a drain of said first NMOS transistor Q1.
6. The adaptive synchronous rectification circuit according to claim 1, wherein a conduction voltage drop between a base and a collector of said second NPN transistor T2 is equal to a conduction voltage drop between a base and an emitter of said first NPN transistor T1.
7. The adaptive synchronous rectification circuit according to claim 1, further comprising a signal amplification module, wherein an input end of the signal amplification module is connected to a collector of the first NPN triode T1, and an output end of the signal amplification module is connected to a gate of the first NMOS tube Q1.
8. The adaptive synchronous rectification circuit of claim 1, wherein said signal amplification module comprises a third NPN transistor T3 and a fourth PNP transistor T4, wherein:
the collector of the third NPN triode T3 is connected with the working voltage Vcc, the emitter of the third NPN triode T3 is connected with the emitter of the fourth PNP triode T4, the collector of the fourth PNP triode T4 is connected with the source of the first NMOS tube Q1, and the base of the third NPN triode T3 is connected with the base of the fourth PNP triode T4;
the base of the third NPN triode T3 is an input end of the signal amplifying module, and the emitter of the third NPN triode T3 is an output end of the signal amplifying module.
CN202211458985.3A 2022-11-21 2022-11-21 Self-adaptive synchronous rectification circuit Pending CN117081407A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211458985.3A CN117081407A (en) 2022-11-21 2022-11-21 Self-adaptive synchronous rectification circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211458985.3A CN117081407A (en) 2022-11-21 2022-11-21 Self-adaptive synchronous rectification circuit

Publications (1)

Publication Number Publication Date
CN117081407A true CN117081407A (en) 2023-11-17

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211458985.3A Pending CN117081407A (en) 2022-11-21 2022-11-21 Self-adaptive synchronous rectification circuit

Country Status (1)

Country Link
CN (1) CN117081407A (en)

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