CN117080204A - 功率半导体模块装置和用于制造功率半导体模块装置的方法 - Google Patents

功率半导体模块装置和用于制造功率半导体模块装置的方法 Download PDF

Info

Publication number
CN117080204A
CN117080204A CN202310545316.8A CN202310545316A CN117080204A CN 117080204 A CN117080204 A CN 117080204A CN 202310545316 A CN202310545316 A CN 202310545316A CN 117080204 A CN117080204 A CN 117080204A
Authority
CN
China
Prior art keywords
substrate
magnetic field
circuit board
printed circuit
power semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310545316.8A
Other languages
English (en)
Inventor
A·阿伦斯
J·德博克
张玺
D·施皮策
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN117080204A publication Critical patent/CN117080204A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/04Housings; Supporting members; Arrangements of terminals
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R15/00Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
    • G01R15/14Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks
    • G01R15/20Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices, i.e. measuring a magnetic field via the interaction between a current and a magnetic field, e.g. magneto resistive or Hall effect devices
    • G01R15/207Constructional details independent of the type of device used
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2818Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52Mounting semiconductor bodies in containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K5/00Casings, cabinets or drawers for electric apparatus
    • H05K5/02Details
    • H05K5/0217Mechanical details of casings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45014Ribbon connectors, e.g. rectangular cross-section
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62Protection against overvoltage, e.g. fuses, shunts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/08Magnetic details
    • H05K2201/083Magnetic materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/10151Sensor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Structure Of Printed Boards (AREA)
  • Inverter Devices (AREA)
  • Measuring Instrument Details And Bridges, And Automatic Balancing Devices (AREA)

Abstract

本公开涉及功率半导体模块装置和用于制造功率半导体模块装置的方法。功率半导体模块装置包括:外壳(7);衬底(10),其包括衬底层(11)和第一金属化层(111),第一金属化层(111)沉积在衬底层(11)的第一侧上并且布置在外壳(7)内或者形成外壳(7)的底部;布置在外壳(7)内的印刷电路板(81),其在垂直方向上位于衬底(10)上方并与衬底(10)平行;布置在印刷电路板(81)上和衬底(10)上的多个导电部件;至少部分地填充外壳(7)的内部,从而覆盖衬底(10)的包封剂(5);被配置为检测磁场的强度的磁场传感器(900);以及被配置为基于由磁场传感器(900)检测到的磁场的强度确定流经导电部件(950)的电流的评估单元。

Description

功率半导体模块装置和用于制造功率半导体模块装置的方法
技术领域
本公开涉及功率半导体模块装置(power semiconductor module arrangement)并且涉及用于制造功率半导体模块装置的方法。
背景技术
功率半导体模块装置往往包括布置在外壳中的至少一个半导体衬底。包括多个可控半导体元件(例如,处于半桥配置当中的两个IGBT)的半导体装置被布置在所述至少一个衬底中的每者上。每一衬底通常包括衬底层(例如,陶瓷层)、沉积在衬底层的第一侧上的第一金属化层以及沉积在衬底层的第二侧上的第二金属化层。例如,可控半导体元件安装在第一金属化层上。第二金属化层可以任选附接至基板(base plate)。
一些功率半导体模块装置还包括被布置为远离并且平行于衬底的印刷电路板。该印刷电路板也可以布置在该外壳内。多个不同的电部件或导电部件(例如,半导体元件、端子元件、连接元件等)可以布置在衬底上和/或印刷电路板上。对于一些应用而言,监测功率半导体模块装置中的一个或多个电流可以是有利的,或者甚至要求监测功率半导体模块装置中的一个或多个电流。相应的电流测量装置往往是大型的,产生显著的热量并且具有高昂的实现成本。
需要功率半导体模块装置中的用于克服上述缺陷的电流测量装置。
发明内容
一种功率半导体模块装置包括:外壳;衬底,其包括衬底层和第一金属化层,第一金属化层沉积在衬底层的第一侧上并且布置在外壳内或者形成外壳的底部;布置在外壳内的印刷电路板,其在垂直方向上位于衬底上方并与衬底平行;布置在印刷电路板上和衬底上的多个导电部件;包封剂,其至少部分地填充外壳的内部,从而覆盖衬底;以及被配置为检测磁场的强度的磁场传感器,其中,要么磁场传感器在衬底上布置于由流经布置在印刷电路板上的导电部件中的一者的电流所引起的磁场的范围内,要么磁场传感器在印刷电路板上布置于由流经布置在衬底上的导电部件中的一者的电流所引起的磁场的范围内,磁场传感器与相应导电部件电绝缘,并且功率半导体模块装置进一步包括评估单元(evaluation means),其被配置为基于由磁场传感器检测到的磁场的强度确定流经所述导电部件的电流。
一种方法包括:将其上布置了多个电子或导电部件的衬底布置在外壳中或者布置成外壳的底部,其中,该外壳包括侧壁;将其上布置了多个电子或导电部件的印刷电路板布置在该外壳中,印刷电路板在垂直方向上位于所述衬底上方并且与所述衬底平行;以及形成至少部分地填充该外壳的内部,从而覆盖该衬底的包封剂,其中,要么将磁场传感器在该衬底上布置于由流经布置在该印刷电路板上的导电部件中的一者的电流所引起的磁场的范围内,要么将磁场传感器在该印刷电路板上布置于由流经布置在该衬底上的导电部件中的一者的电流所引起的磁场的范围内,磁场传感器与相应导电部件电绝缘,并且该方法进一步包括将评估单元布置在该衬底上或者该印刷电路板上,该评估单元被配置为基于由磁场传感器检测到的磁场的强度确定流经所述导电部件的电流。
参考以下附图和描述,本发明可以得到更好的理解。附图中的部件未必是按比例绘制的,相反将重点放在示出本发明的原理。此外,在附图中,同样的附图标记在不同的附图当中表示相对应的部分。
附图说明
图1是功率半导体模块装置的截面图。
图2是根据一个示例的功率半导体模块装置的截面图。
图3是根据另一示例的功率半导体模块装置的截面图。
图4是根据另一示例的功率半导体模块装置的截面图。
图5是根据图3的示例的功率半导体模块装置的顶视图。
图6是根据图4的示例的功率半导体模块装置的顶视图。
图7是根据又一示例的功率半导体模块装置的顶视图。
图8是根据又一示例的功率半导体模块装置的截面图。
图9示意性地示出了根据一个示例的电流测量装置的金属托架的三维图。
图10示意性地示出了根据另一示例的电流测量装置的截面图。
图11示意性地示出了根据一个示例的电流测量装置的金属托架的顶视图。
图12示意性地示出了根据另一示例的电流测量装置的金属托架的顶视图。
具体实施方式
在下文的详细描述当中将参考附图。附图示出了可以实践本发明的特定示例。应当理解,可以将针对各种示例描述的特征和原理相互结合,除非另行具体指示。在说明书和权利要求中,将某些元件命名为“第一元件”、“第二元件”、“第三元件”等不应被理解为用作枚举。相反,这样的命名只是为了标明不同的“元件”。也就是说,例如,“第三元件”的存在不要求“第一元件”和“第二元件”的存在。本文所描述的电气线路或电连接可以是单个导电元件或者可以包括串联和/或并联连接的至少两个个体导电元件。电气线路和电连接可以包括金属和/或半导体材料,并且可以是永久性导电的(即,非可开关的)。本文所描述的半导体主体可以由(掺杂)半导体材料制成并且可以是半导体芯片或者包括在半导体芯片中。半导体主体具有电连接焊盘,并且包括至少一个具有电极的半导体元件。
参考图1,其示意性地示出了功率半导体模块装置100的截面图。功率半导体模块装置100包括外壳7和衬底10。衬底10包括电介质绝缘层11、附接至电介质绝缘层11的(结构化)第一金属化层111以及附接至电介质绝缘层11的(结构化)第二金属化层112。电介质绝缘层11设置在第一和第二金属化层111、112之间。
第一和第二金属化层111、112中的每者都可以由下述材料之一构成或包括下述材料之一:铜;铜合金;铝;铝合金;在功率半导体模块装置操作期间保持为固体的任何其他金属或合金。衬底10可以是陶瓷衬底,即,其中的电介质绝缘层11是陶瓷的衬底,例如,薄陶瓷层。陶瓷可以由下述材料之一构成或包括下述材料之一:氧化铝;氮化铝;氧化锆;氮化硅;氮化硼或任何其他电介质陶瓷。例如,电介质绝缘层11可以由下述材料之一构成或者包括下述材料之一:Al2O3、AlN、SiC、BeO或Si3N4。举例而言,衬底10可以例如是直接铜接合(DCB)衬底、直接铝接合(DAB)衬底或者活性金属钎焊(AMB)衬底。此外,衬底10可以是绝缘金属衬底(IMS)。例如,绝缘金属衬底一般包括含有诸如环氧树脂或聚酰亚胺之类的(填充)材料的电介质绝缘层11。例如,可以采用陶瓷颗粒填充电介质绝缘层11的材料。这样的颗粒可以包括例如SiO2、Al2O3、AlN或BN,并且可以具有处于大约1μm和大约50μm之间的直径。衬底10还可以是具有非陶瓷电介质绝缘层11的常规印刷电路板(PCB)。例如,非陶瓷电介质绝缘层11可以由固化树脂构成或者可以包括固化树脂。
衬底10被布置于外壳7中。在图1中所示的示例中,衬底10形成了外壳7的地表面(ground surface),而外壳7本身则仅包括侧壁以及帽或盖。然而,这只是示例。还有可能衬底10布置在形成了外壳7的地表面的基板上,或者外壳7进一步包括地表面和衬底10,并且任选地基板布置在外壳7内。在一些功率半导体模块装置100中,在单个基板12上或者在外壳7的地表面上布置不止一个衬底10。
可以在所述至少一个衬底10上布置一个或多个半导体主体20。布置在所述至少一个衬底10上的半导体主体20中的每者可以包括二极管、IGBT(绝缘栅双极型晶体管)、MOSFET(金属氧化物半导体场效应晶体管)、JFET(结型场效应晶体管)、HEMT(高电子迁移率晶体管)和/或任何其他适当半导体元件。
所述一个或多个半导体主体20可以在衬底10上形成半导体装置。在图1中,仅示例性地示出了两个半导体主体20。图1中的衬底10的第二金属化层112是连续层。在图1所示的示例中,第一金属化层111是结构化层。“结构化层”是指第一金属化层111不是连续层,而是包括处于该层的不同区段之间的凹陷部。在图1中示意性地示出了这样的凹陷部。这一示例中的第一金属化层111包括三个不同区段。然而,这只是示例。任何其他数量的区段都是可能的。可以将不同的半导体主体20安装至第一金属化层111的相同区段或不同区段。第一金属化层111的不同区段可以不具有任何电连接,或者可以使用电连接3(例如,接合引线)与一个或多个其他区段电连接。例如,为了略举几例,电连接3还可以包括接合带、连接板或导体轨。所述一个或多个半导体主体20可以通过导电连接层60电及机械连接至衬底10。例如,这样的导电连接层60可以是焊料层、导电粘合剂层或者烧结金属粉末(例如,烧结银粉末)层。
根据其他示例,第二金属化层112也可能是结构化层。还可能将第二金属化层112完全省去。通常还可能的是,第一金属化层111例如是连续层。
图1中所示的功率半导体模块装置100进一步包括端子元件4。端子元件4的第一子集电连接至第一金属化层111,并且提供外壳7的内部和外部之间的电连接。端子元件4可以借助于第一端41电连接至第一金属化层111,同时端子元件4中的每者的第二端42从外壳7伸出。可以在端子元件4的相应第二端42处从外部电接触端子元件4。端子元件4的第一部分可以在垂直方向y上延伸穿过外壳7的内部。垂直方向y是垂直于衬底10的顶表面的方向,其中,衬底10的顶表面是在上面安装至少一个半导体主体20的表面。然而,图1所示的端子元件4只是示例。可以通过任何其他方式实施端子元件4,并且可以将端子元件4布置在外壳7内的任何位置。例如,可以将一个或多个端子元件4布置为进一步远离外壳7的侧壁。端子元件4还可以穿过外壳7的侧壁伸出而不是穿过盖伸出。例如,可以通过导电连接层(图1中未明确示出)将端子元件4的第一端41电及机械地连接至衬底10。例如,这样的导电连接层可以是焊料层、导电粘合剂层或者烧结金属粉末(例如,烧结银(Ag)粉末)层。端子元件4的第一端41也可以例如经由一个或多个电连接3电耦接至衬底10。例如,端子元件4的第二端42可以连接至被布置在外壳7外的印刷电路板(图1中未示出外部印刷电路板)。
功率半导体模块装置100进一步包括内部印刷电路板81。印刷电路板81耦接至端子元件4的第二子集并且布置在外壳7内。端子元件4的第二子集可以包括完全布置在外壳7内的较短端子元件。然而,端子元件4的第三子集可以从衬底10穿过印刷电路板81中的贯穿孔延伸到外壳7的外部,针对图1中的端子元件4中的一个端子元件4示例性地示出了这一点。
根据未具体示出的另一示例,一个或多个端子元件4可以凭借其第一端41机械及电耦接至印刷电路板81,而它们的第二端42则延伸到外壳7的外部。例如,通过将印刷电路板81布置在外壳7的内部,可以以紧凑和节约空间的方式实施功率半导体模块装置100。这是因为通常布置在衬底10上或者外部印刷电路板(布置在外壳7的外部的印刷电路板)上的多个部件的至少一个子集可以布置在内部印刷电路板81上而非衬底10或外部印刷电路板上。也就是说,一些(或全部)部件可以布置在外壳7内的印刷电路板81上,而其他部件(或没有部件)布置在(任选的)外部印刷电路板上。因此,与仅包括衬底10或者包括衬底10和位于外壳7外部的外部印刷电路板而不包括位于外壳7内部的印刷电路板81的装置相比,可以降低衬底10和/或外部印刷电路板的尺寸。
功率半导体模块装置100进一步包括包封剂5。例如,包封剂5可以由硅酮(silicone)凝胶构成或者可以包括硅酮凝胶,或者可以是刚性模制化合物。包封剂5可以至少部分地填充外壳7的内部,从而覆盖布置于衬底10上的部件和电连接。为了对外壳7内的印刷电路板81和布置在印刷电路板81上的部件进行保护以使其免受某些环境条件和机械损坏的影响,印刷电路板81任选地也可以被包封剂5覆盖。端子元件4可以部分地嵌入在包封剂5中。然而,至少第一子集和第三子集的第二端42未被包封剂5覆盖,而是从包封剂5穿过外壳7伸出到外壳7外部。包封剂5被配置为保护功率半导体模块100的部件和电连接,特别是保护布置于外壳7内部的衬底10上的部件,以使其免受某些环境条件和机械损坏的影响。
对于一些应用而言,监测功率半导体模块装置100中的一个或多个电流可以是有利的,或者甚至要求监测功率半导体模块装置100中的一个或多个电流。因此,图2中所示的功率半导体模块装置100进一步包括磁场传感器900。磁场传感器900被配置为检测磁场的强度。在图2所示的示例中,磁场传感器900在印刷电路板81上布置于由流经导电部件910的电流所引起的磁场的范围内,其中,导电部件910布置在衬底10上。通过这种方式,可以以无接触方式监测通过导电部件910的电流。磁场传感器900与相应导电部件910电流绝缘。通过将磁场传感器900布置在与导电部件910相距所定义距离d1处并且进一步借助于填充磁场传感器900和导电部件910之间的所产生区域的包封剂5来建立电流隔离(galvanicisolation)。
在图2所示的示例中,磁场传感器900布置在印刷电路板81的面朝衬底10的一侧上。通过这种方式,流经导电部件的电流所引起的磁场不受布置在磁场传感器900和导电部件910之间的任何部件(例如,印刷电路板81)的影响。然而,这不是强制性的。一般还有可能将磁场传感器900布置在印刷电路板81的背对着衬底10的一侧上。如果磁场足够强,那么它仍然能够被可靠地检测到。
功率半导体模块装置100进一步包括评估单元,该评估单元被配置为基于由磁场传感器900检测到的磁场的强度来确定流经导电部件910的电流。例如,这样的评估单元可以要么包含在磁场传感器900本身中,要么可以布置在印刷电路板81上或者衬底10上。
尽管在图2所示的示例中磁场传感器900布置在印刷电路板81上并且导电部件910布置在衬底10上,也有可能例如将磁场传感器900在衬底10上布置于由流经布置在印刷电路板81上的导电部件910的电流所引起的磁场的范围内。相同的一般原理适用于这两种情况。
在图2所示的示例中,导电部件910是专用部件,其不具有除了传导引起将由磁场传感器900检测的磁场的电流之外的任何其他功能。下文将更详细地描述这样的专用导电部件的示例。然而,还有可能采用由于其他原因而已经存在于功率半导体模块装置100中的导电部件来达到测量功率半导体模块装置100中的电流的目的。任何在功率半导体模块装置100的使用期间实际传导电流的导电部件均引起能够借助于磁场传感器900检测的磁场。
作为对上文的总结并且参考图8,导电部件950可以要么包括专用导电部件910,要么包括导电部件,例如,举例而言,端子元件4、接合线3、接合带、连接板、导体轨、衬底10的第一金属化层111的区段或者印刷电路板81上形成的导电通路,其中所述导电部件在功率半导体模块装置100的使用期间实际传导电流,并且引起能够借助于磁场传感器900检测到的磁场。流经导电部件的电流所引起的磁场由布置在该磁场的范围内的磁场传感器900检测。磁场传感器900与相应导电部件950借助于它们之间的距离和包封剂5进行电绝缘。
现在参考图3,所述导电部件可以包括如上文已经结合图1所描述的一个或多个端子元件4。在图3所示的示例中,所述一个或多个端子元件4是从衬底10穿过外壳7的内部延伸到外壳7的外部的第一子集的端子元件。在图3所示的示例中,所述一个或多个端子元件4在水平方向x上越过印刷电路板81延伸。也就是说,所述一个或多个端子元件4不与印刷电路板81直接接触。然而,这只是示例。一般还有可能的是,所述一个或多个端子元件4是如上文已经结合图1所描述的第二或第三子集的端子元件。
图3所示示例中的磁场传感器900布置在印刷电路板81上并且布置在流经所述一个或多个端子元件4的电流IS所引起的磁场内。也就是说,磁场传感器900可以被布置为接近印刷电路板81的被布置为紧密靠近所述一个或多个端子元件4的边缘。在这一语境下,紧密靠近是指在所述一个或多个端子元件4与所述磁场传感器900之间提供足够的电隔离,与此同时仍然允许流经所述一个或多个端子元件4的电流IS所引起的磁场能够被磁场传感器900感测到的任何距离。磁场传感器900可以例如包括能够检测磁场的TMR传感器或霍尔传感器。之后,可以借助于相应的评估单元基于所检测到的磁场的强度确定通过所述一个或多个端子元件4的电流IS
在图5的示意性顶视图中进一步示出了图3的装置。在图5的示例中,借助于围绕端子元件4延伸的虚线示意性地示出了由流经所述一个或多个端子元件4(在图5的示例中,针对每一磁场传感器900有三个端子元件)的电流IS所引起的磁场。
根据在图4的截面图和图6的顶视图中示意性地示出的另一个示例,磁场传感器900可以耦接至环绕所述一个或多个端子元件4的磁芯902。磁芯902可以包括具有高磁导率的磁性材料,例如,诸如铁或铁氧体之类的铁磁材料。通过这种方式,例如,流经所述一个或多个端子元件4的电流IS所引起的磁场集中在磁芯902中并且可以得到增强。磁芯902可以包括空气隙,磁场传感器900布置在该空气隙中。这还允许确定由通过端子元件4的电流IS所引起的磁场的强度。具体而言,由磁芯902对磁场进行集中,并将磁场引导至该空气隙,可以在空气隙处由磁场传感器900可靠地检测该磁场。
根据在图7的顶视图中示意性地示出的又一示例,所述一个或多个端子元件4穿过印刷电路板81中的孔812延伸。磁场传感器900布置在印刷电路板81上并且耦合至形成于印刷电路板81上的线圈或芯904。例如,线圈或芯904可以是借助于形成在印刷电路板81上的导电通路形成的。线圈或芯904包围形成于印刷电路板81中的孔812(围绕孔812延伸)。这还允许确定由通过端子元件4的交变电流IS所引起的磁场的强度。通过端子元件4的交变电流IS引起可变磁场,该可变磁场又在线圈或芯904中感生出电流。这一感生出的电流可以由磁场传感器900确定,并且允许确定通过端子元件4的电流IS
现在将参考图9更详细地描述不具有除了传导引起将由磁场传感器900检测的磁场的电流之外的任何其他功能的专用导电部件910的示例。图9示意性地示出了没有磁场传感器900的导电部件910(图9的左侧)和具有磁场传感器900的导电部件910(图9的右侧)的三维图。衬底10和印刷电路板81未在图9中明确示出。这一示例中的导电部件910包括托架(bracket)。该托架可以由导电材料(例如,举例而言,金属)形成。托架910包括两个接触区域9102,这两个接触区域9102中的每者被配置为电及机械耦接至衬底10或印刷电路板81。连接件9104在两个接触区域9102之间延伸并对它们进行连接。连接件9104形成了被布置为远离衬底10或印刷电路板81的拱形物(arc)或桥。接触区域9102可以耦接至例如衬底10的第一金属化层111或者耦接至形成在印刷电路板81上的导体轨,使得电流可以从接触区域9102中的第一接触区域通过连接件9104流至接触区域9102中的第二接触区域。连接件9104可以具有基本上平行于衬底10和印刷电路板81的区段。这允许将磁场传感器900置于与连接件9104相距所需距离d1处,从而能够检测由流经托架910的电流引起的磁场。
印刷电路板81通常被布置在与衬底10相距特定距离处。这样做可以具有不同原因。例如,可能要求布置在衬底10上的不同部件被布置在与印刷电路板81相距特定距离处,以提供足够的电绝缘。因此,被安装至印刷电路板81的磁场传感器900可以被布置为相对远离衬底10。因此,流经例如衬底的第一金属层111的区段的电流可以不引起强到足以被磁场传感器900检测到的磁场。由于连接件9104形成了拱形物或桥,因而它在相距衬底10的特定距离处延伸,并且被布置为比衬底10(或金属化层111)本身更接近磁场传感器900。因此,流经连接件9104的电流所引起的磁场可以强到足以被磁场传感器900检测到。因此,连接件9104降低了与磁场传感器900的距离。因此,可以选择托架910的尺寸,从而匹配功率半导体模块装置100的总体尺寸。在图10的截面图中进一步示出了这一点。同样的内容适用于当将托架910安装至印刷电路板81并且将磁场传感器900安装至衬底10时的情况。
现在参考图11和图12,连接件9104可以具有在水平方向z上的第一宽度w1。可以在至少一个区段914中将这一第一宽度w1局部降低至小于第一宽度w1的第二宽度w2。在图11所示的示例中,连接件9104包括两个凹陷部912。这些凹陷部912从相反侧延伸到连接件9104中,并且被布置为相互偏移。通过这种方式,在两个不同区段914中将第一宽度w1局部降低至第二宽度w2。因此,连接件9104一般具有S形状。流经连接件9104的电流必须流经该S形连接件的中间区段,该中间区段在另一水平方向x上具有第三宽度w3,该第三宽度w3甚至可以比第二宽度w2更小。通过这种方式,在这些具有降低的宽度的区段中局部增大了连接件9104的电阻,从而增强了流经连接件9104的电流所引起的磁场。然而,在托架910的其余区段中,所产生的磁场相对较低。因此,该磁场集中在接近磁场传感器900的位置上,在该位置处,该磁场被检测。然而,功率半导体模块装置100的其他部件不受流经托架910的电流所引起的磁场的影响。
在图12所示的示例中,产生了相同的效果。在这一示例中,两个凹陷部912被布置为不相对于彼此偏移。因此,连接件9104的第一宽度w1仅在一个区段914中被局部降低,从而具有小于第一宽度w1的第四宽度w4。在这一示例中,连接件一般具有H形状。
然而,图11和图12所示的形状只是示例。上文已经描述的托架910可以具有任何其他形状,该形状将产生强到足以被磁场传感器900检测到的磁场。
如从上文可以看出的,可以通过非常简单并且节省空间的方式来实施包括导电部件950和磁场传感器900的装置。甚至有可能采用在功率半导体模块装置100中已经出于其他原因而存在的部件来充当导电部件950。导电部件950和磁场传感器900之间的电流隔离是由它们之间的距离和已经出于其他原因而存在于功率半导体模块装置100中的包封剂5提供的。也就是说,可以在无需任何额外成本的情况下提供电流隔离。此外,在上文描述的装置中不需要体积大且成本高的分路器件(shunt)来检测功率半导体模块装置100中的电流。

Claims (12)

1.一种功率半导体模块装置,包括:
外壳(7);
衬底(10),其包括衬底层(11)和第一金属化层(111),所述第一金属化层(111)沉积在所述衬底层(11)的第一侧上,并且布置在所述外壳(7)内或者形成所述外壳(7)的底部;
布置在所述外壳(7)内的印刷电路板(81),其在垂直方向上位于所述衬底(10)上方并与所述衬底(10)平行;
布置在所述印刷电路板(81)上和所述衬底(10)上的多个导电部件;
包封剂(5),其至少部分地填充所述外壳(7)的内部,从而覆盖所述衬底(10);以及
被配置为检测磁场的强度的磁场传感器(900),其中
要么所述磁场传感器(900)在所述衬底(10)上布置于由流经布置在所述印刷电路板(81)上的所述导电部件(950)中的一者的电流所引起的磁场的范围内,
要么所述磁场传感器(900)在所述印刷电路板(81)上布置于由流经布置在所述衬底(10)上的所述导电部件(950)中的一者的电流所引起的磁场的范围内,
所述磁场传感器(900)与相应的所述导电部件(950)电绝缘,并且
所述功率半导体模块装置进一步包括评估单元,其被配置为基于由所述磁场传感器(900)检测到的所述磁场的强度来确定流经所述导电部件(950)的电流。
2.根据权利要求1所述的功率半导体模块装置,其中,所述导电部件(950)包括托架(910)。
3.根据权利要求2所述的功率半导体模块装置,其中,所述托架(910)包括:
两个接触区域(9102),所述两个接触区域(9102)中的每者电及机械耦接至所述衬底(10)或者所述印刷电路板(81),以及
连接件(9104),所述连接件(9104)在所述两个接触区域(9102)之间延伸并将所述两个接触区域(9102)进行连接,并且形成远离所述衬底(10)或所述印刷电路板(81)布置的拱形物或桥。
4.根据权利要求3所述的功率半导体模块装置,其中,所述连接件(9104)具有在至少一个区段(914)中局部降低的沿水平方向(z)的第一宽度(w1)。
5.根据前述权利要求中的任何一项所述的功率半导体模块装置,其中,所述磁场传感器(900)包括霍尔元件。
6.根据权利要求1所述的功率半导体模块装置,其中,所述导电部件(950)是接合线(3)、接合带、所述衬底(10)的所述第一金属化层(111)的区段或者形成于所述印刷电路板(81)上的导电通路。
7.根据权利要求1所述的功率半导体模块装置,其中,所述导电部件(950)包括一个或多个端子元件(4),所述端子元件从所述衬底(10)延伸到所述外壳(7)的外部并且被配置为提供往来于所述功率半导体模块装置的控制信号。
8.根据权利要求7所述的功率半导体模块装置,其中,所述磁场传感器(900)布置在所述印刷电路板(81)上并且耦合至形成于所述印刷电路板(81)上的线圈或芯(904)。
9.根据权利要求8所述的功率半导体模块装置,其中,所述线圈或芯(904)包围形成于所述印刷电路板(81)中的孔(812),并且其中,所述一个或多个端子元件(4)从所述衬底(10)穿过形成于所述印刷电路板(81)中的所述孔(812)延伸到所述外壳(7)的外部。
10.根据权利要求7所述的功率半导体模块装置,进一步包括环绕所述一个或多个端子元件(4)的磁芯(902)。
11.根据权利要求10所述的功率半导体模块装置,其中,所述磁芯(902)包括空气隙,并且所述磁场传感器(900)布置在所述空气隙内。
12.一种方法,包括:
将其上布置了多个电子或导电部件的衬底(10)布置在外壳(7)中或者布置成外壳(7)的底部,其中,所述外壳(7)包括侧壁;
将其上布置了多个电子或导电部件的印刷电路板(81)布置在所述外壳(7)中,所述印刷电路板(81)在垂直方向上位于所述衬底(10)上方并且与所述衬底(10)平行;以及
形成包封剂(5),所述包封剂(5)至少部分地填充所述外壳(7)的内部,从而覆盖所述衬底(10),其中
要么将磁场传感器(900)在所述衬底(10)上布置于由流经布置在所述印刷电路板(81)上的所述导电部件(950)中的一者的电流所引起的磁场的范围内,
要么将磁场传感器(900)在所述印刷电路板(81)上布置于由流经布置在所述衬底(10)上的所述导电部件(950)中的一者的电流所引起的磁场的范围内,
所述磁场传感器(900)与相应的所述导电部件(950)电绝缘,并且
所述方法进一步包括将评估单元布置在所述衬底(10)上或者所述印刷电路板(81)上,所述评估单元被配置为基于由所述磁场传感器(900)检测到的所述磁场的强度来确定流经所述导电部件(950)的电流。
CN202310545316.8A 2022-05-16 2023-05-15 功率半导体模块装置和用于制造功率半导体模块装置的方法 Pending CN117080204A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP22173416.3A EP4280277A1 (en) 2022-05-16 2022-05-16 Power semiconductor module arrangement and method for producing a power semiconductor module arrangement
EP22173416.3 2022-05-16

Publications (1)

Publication Number Publication Date
CN117080204A true CN117080204A (zh) 2023-11-17

Family

ID=81654905

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310545316.8A Pending CN117080204A (zh) 2022-05-16 2023-05-15 功率半导体模块装置和用于制造功率半导体模块装置的方法

Country Status (3)

Country Link
US (1) US20230369187A1 (zh)
EP (1) EP4280277A1 (zh)
CN (1) CN117080204A (zh)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6819095B1 (en) * 1999-09-16 2004-11-16 International Rectifier Corporation Power semiconductor device assembly with integrated current sensing and control
JP2003009508A (ja) * 2001-06-19 2003-01-10 Mitsubishi Electric Corp 電力用半導体装置
JP2003315373A (ja) * 2002-04-18 2003-11-06 Toshiba Corp 電流検出装置及び半導体装置
US9678173B2 (en) * 2013-05-03 2017-06-13 Infineon Technologies Ag Power module with integrated current sensor
US20230048878A1 (en) * 2020-01-30 2023-02-16 Hitachi Energy Switzerland Ag Power Semiconductor Module with Accessible Metal Clips

Also Published As

Publication number Publication date
EP4280277A1 (en) 2023-11-22
US20230369187A1 (en) 2023-11-16

Similar Documents

Publication Publication Date Title
US11895930B2 (en) Current sensor package with continuous insulation
US9370113B2 (en) Power semiconductor module with current sensor
US9529013B2 (en) Current sensor
US9564423B2 (en) Power package with integrated magnetic field sensor
US9852928B2 (en) Semiconductor packages and modules with integrated ferrite material
JP3453115B2 (ja) 電流センシングを行うパワーアセンブリ
US9231118B2 (en) Chip package with isolated pin, isolated pad or isolated chip carrier and method of making the same
JP6256819B2 (ja) 電流センサ及び電流測定装置
US9564578B2 (en) Semiconductor package with integrated magnetic field sensor
US10168391B2 (en) Multi-functional interconnect module and carrier with multi-functional interconnect module attached thereto
CN111089995A (zh) 绝缘电流传感器
JP6415467B2 (ja) 配線基板、および半導体モジュール
EP3926679A1 (en) Power semiconductor module arrangement comprising a temperature sensor
US11942449B2 (en) Semiconductor arrangement and method for producing the same
CN112309994B (zh) 半导体模块装置
CN117080204A (zh) 功率半导体模块装置和用于制造功率半导体模块装置的方法
US10515879B2 (en) Package with component connected at carrier level
EP3863045A1 (en) Power semiconductor module arrangement and method for producing the same
CN102403294A (zh) 半导体器件
US20240145362A1 (en) Power Semiconductor Module Arrangement
CN111443230B (zh) 具有可布线模制引线框的电流传感器设备
EP4084062A1 (en) Power semiconductor module arrangement
JPH01286344A (ja) 電子部品搭載用基板
CN116507018A (zh) 印刷电路板、包括印刷电路板的功率半导体模块布置结构及其组装方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication