CN117080072A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN117080072A
CN117080072A CN202210505380.9A CN202210505380A CN117080072A CN 117080072 A CN117080072 A CN 117080072A CN 202210505380 A CN202210505380 A CN 202210505380A CN 117080072 A CN117080072 A CN 117080072A
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region
edge
forming
layer
semiconductor structure
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汪刘建
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate comprises a first region and a second region, and the second region comprises a first edge region and a middle region; forming a main trench in the second region; etching the first edge region by adopting a first etching process to form a first edge groove; forming an epitaxial layer in the main groove and the first edge groove, wherein the material of the epitaxial layer is different from that of the substrate; and adopting a patterning process to enable the first region of the substrate to form a plurality of mutually separated first fin parts, and enabling the epitaxial layer to form a plurality of mutually separated second fin parts. By forming the first edge groove in the first edge region, the fillet span of the bottom of the main groove can be effectively reduced, and the fillet of the bottom of the main groove is smaller. Therefore, after the patterning process, the material doped with the epitaxial layer in part of the first fin part is reduced, and meanwhile, the problem that the germanium-silicon material in part of the second fin part is less can be reduced, so that the performance of the finally formed semiconductor structure is affected.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the development of semiconductor technology, the feature size of devices in integrated circuits is becoming smaller. However, as the feature size of devices becomes smaller, the length of the channel region between the source and drain becomes shorter. When the length of the channel region is reduced to a certain value, short channel effects are generated, and the performance of the device is affected by the existence of the short channel effects, so that further reduction of the feature size of the device in the integrated circuit is prevented.
In order to overcome the short channel effect in the prior art and promote the development of semiconductor technology, by changing the channel material into a germanium-silicon (SiGe) material, the performance of the device can be greatly improved by taking the germanium-silicon material as the material of the channel region because the germanium-silicon material has high hole mobility which is 6-25 times that of the silicon (Si) material.
However, the prior art transistor with germanium-silicon material channel still has a number of problems.
Disclosure of Invention
The invention solves the technical problem of providing a semiconductor structure and a forming method thereof so as to improve the performance of the finally formed semiconductor structure.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate comprising a first region and a second region adjacent to each other, the second region comprising a first edge region and a middle region, and the first edge region being adjacent to the first region; forming a main trench in the second region; etching the first edge area exposed by the main groove by adopting a first etching process, and forming a first edge groove in the first edge area, wherein the first edge groove is exposed by the main groove; forming an epitaxial layer in the main groove and the first edge groove, wherein the material of the epitaxial layer is different from that of the substrate; and carrying out a patterning process on the first region of the substrate and the epitaxial layer, so that a plurality of first fins which are mutually separated are formed in the first region of the substrate, and a plurality of second fins which are mutually separated are formed in the epitaxial layer.
Optionally, the substrate further includes: a third region, the second region being located between the first region and the third region; the second zone further comprises: a second edge region, the intermediate region being located between the first edge region and the second edge region, and the second edge region being contiguous with the third region.
Optionally, in the process of etching the first edge area exposed by the main trench by adopting a first etching process, the method further includes: and etching the second edge region exposed by the main groove, and forming a second edge groove in the second edge region, wherein the second edge groove is exposed by the main groove.
Optionally, the epitaxial layer is further formed in the second edge trench.
Optionally, the process parameters of the first etching process include: adopts a plasma etching process, and the main etching gas is CL 2 The method comprises the steps of carrying out a first treatment on the surface of the Bias voltage is 300V-1000V; the air pressure in the etching cavity is 1-10 mtorr.
Optionally, the method for forming the main trench in the second region includes: forming an initial mask layer on a substrate; forming a patterning layer on the initial mask layer, wherein an opening exposing part of the initial mask layer is formed in the patterning layer; etching the initial mask layer by using the patterned layer as a mask and adopting a second etching process until the top surface of the substrate is exposed, forming a mask layer and a mask opening positioned in the mask layer, wherein the mask opening exposes the top surface of a second region of the substrate, and an included angle between the side wall of the mask opening and the surface of the substrate is a preset included angle; and etching the second region by taking the mask layer as a mask, and forming the main groove in the second region.
Optionally, the preset included angle is: 90-95 deg..
Optionally, the process parameters of the second etching process include: with a plasma etching process, the main etching gas includes: fluorine-containing etching gas SF 6 、CF 4 、CH 2 F 2 The method comprises the steps of carrying out a first treatment on the surface of the Gas concentration ratio SF 6 ：CF 4 ：CH 2 F 2 Equal to 1:1:1 to 1:10:20; the auxiliary etching gas includes: o (O) 2 、N 2 According to the dissociation degree under different conditions, the ratio of carbon particles, fluorine particles and oxygen particles is 1:1:1-3:6:1; bias voltage is 50V-1000V; the air pressure in the etching cavity is 1-10 mtorr.
Optionally, the patterned layer is a single-layer structure or a multi-layer structure.
Optionally, when the patterned layer is a multi-layer structure, the patterned layer includes: an amorphous carbon layer, a dielectric anti-reflective layer on the amorphous carbon layer, and a photoresist layer on the dielectric anti-reflective layer.
Optionally, an epitaxial growth process is used to form the epitaxial layer in the main trench.
Optionally, the material of the substrate includes: silicon; the material of the epitaxial layer comprises: germanium silicon.
Optionally, the first fin portion is used for forming an NMOS transistor; the second fin portion is used for forming a PMOS transistor.
Correspondingly, the technical scheme of the invention also provides a semiconductor structure, which comprises the following steps: a substrate comprising a first region and a second region adjacent to each other, the second region comprising a first edge region and a middle region, and the first edge region being adjacent to the first region; a main trench located within the second region; a first edge trench in the first edge region, the main trench exposing the first edge trench; and the epitaxial layer is positioned in the main groove and the first edge groove, and the material of the epitaxial layer is different from that of the substrate.
Optionally, the substrate further includes: a third region, the second region being located between the first region and the third region; the second zone further comprises: a second edge region, the intermediate region being located between the first edge region and the second edge region, and the second edge region being contiguous with the third region.
Optionally, the method further comprises: and a second edge groove in the second edge region, wherein the main groove exposes the second edge groove.
Optionally, the epitaxial layer is further located in the second edge trench.
Optionally, the material of the substrate includes: silicon; the material of the epitaxial layer comprises: germanium silicon.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the forming method of the technical scheme, the first edge groove is formed in the first edge area, and the main groove exposes out of the first edge groove, so that the fillet span of the bottom of the main groove can be effectively reduced, and the fillet of the bottom of the main groove is smaller. Therefore, after patterning, the material doped with the epitaxial layer in part of the first fin part is reduced, and meanwhile, the problem that part of the germanium-silicon material in the second fin part is less can be reduced, so that the performance of the finally formed semiconductor structure is affected.
Further, the process parameters of the first etching process include: adopts a plasma etching process, and the main etching gas is CL 2 The method comprises the steps of carrying out a first treatment on the surface of the Bias voltage is 300V-1000V; the air pressure in the etching cavity is 1-10 mtorr. Due to CL 2 The gas has few byproducts, and the bottom fillets of the main grooves are relatively straight without byproduct accumulation. Since a part of the source of the rounded corners is the accumulation protection of byproducts at the bottom of the side walls. At this time, a larger bias voltage is applied to the plasma, so that the acceleration of ions in the plasma is increased, and the bombardment energy is improved. The bombardment is concentrated at the bottom of the main trench sidewall due to the blocking of the main trench sidewall compared to the intermediate region position, thereby forming a first edge trench in the first edge region.
Further, the process parameters of the second etching process include: with a plasma etching process, the main etching gas includes: fluorine-containing etching gas SF 6 、CF 4 、CH 2 F 2 The method comprises the steps of carrying out a first treatment on the surface of the Gas concentration ratio SF 6 ：CF 4 ：CH 2 F 2 Equal to 1:1:1 to 1:10:20; the auxiliary etching gas includes: o (O) 2 、N 2 According to the dissociation degree under different conditions, the ratio of carbon particles, fluorine particles and oxygen particles is 1:1:1-3:6:1; bias voltage is 50V-1000V; the air pressure in the etching cavity is 1-10 mtorr. By adjusting the ratio of fluorine and oxygen free radicals in the second etching process, the etching selectivity is improved, the consumption of the initial mask layer is reduced, and simultaneously, the etching byproducts are deposited on the side wall to increase the side wall protectionThe bombardment of the plasma on the side wall of the initial mask layer is weakened, the etching rate of the side wall of the initial mask layer is reduced, the vertical side wall is further obtained, and the roughness is improved. By protecting the mask layer sidewall, which is relatively vertical, irregular elastic collisions (compared with inclined and hollow sidewalls) of ions and free radicals on the mask layer sidewall are reduced in the subsequent etching process. The ejected particles still have relatively high energy and randomly strike the bottom of the subsequently formed main trench and form a pit. Therefore, ejection is uniformly distributed on the side wall of the mask layer, which is vertical and well protected, and the micro pits at the bottom of the main groove are well controlled.
According to the technical scheme, the structure comprises the first edge groove positioned in the first edge area, the main groove exposes the first edge groove, and the fillet span of the bottom of the main groove can be effectively reduced through the first edge groove, so that the fillet of the bottom of the main groove is smaller. Therefore, after patterning, the material doped with the epitaxial layer in part of the first fin part is reduced, and meanwhile, the problem that part of the germanium-silicon material in the second fin part is less can be reduced, so that the performance of the finally formed semiconductor structure is affected.
Drawings
FIGS. 1-2 are schematic views of steps of a method for forming a semiconductor structure;
fig. 3 to 9 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, there are still a number of problems with prior art sige channel transistors. The following will make a detailed description with reference to the accompanying drawings.
Fig. 1-2 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes a first region I and a second region II adjacent to each other; forming a mask layer 101 on the substrate 100, the mask layer 101 exposing a top surface of the second region II; etching the second region II by using the mask layer 101 as a mask, and forming a trench (not labeled) in the second region II; an epitaxial layer 102 is formed in the trench by an epitaxial growth process, and the material of the epitaxial layer 102 is different from the material of the substrate 100.
Referring to fig. 2, a patterning process is performed on the first region I of the substrate 100 and the epitaxial layer 102, so that a plurality of first fins 103 are formed in the first region I of the substrate 100, and a plurality of second fins 104 are formed in the epitaxial layer 102.
In this embodiment, the material of the substrate 100 is silicon, and the material of the epitaxial layer 102 is germanium-silicon, so that the material of the corresponding first fin 103 is silicon, and the material of the second fin 104 is germanium-silicon. The first fin 103 is then used as a channel region of the formed NMOS transistor, and the second fin 104 is used as a channel region of the formed PMOS transistor, so that the channel region of the germanium-silicon material can effectively improve the mobility of holes, thereby improving the performance of the finally formed semiconductor structure.
In this embodiment, because the depth-to-width ratio of the trench is small, in the process of etching to form the trench, the problem of lateral etching is more prominent along the direction perpendicular to the sidewall of the trench, so that a fillet structure with a larger span appears at the bottom of the formed trench. And when the span dimension d2 of the rounded corner structure is larger than the preset spacing dimension d1, after the patterning process, a part of the first fin 103 is doped with a germanium-silicon material, and a part of the second fin 104 is less in germanium-silicon material, so that the performance of the finally formed semiconductor structure is affected.
On the basis, the invention provides a semiconductor structure and a forming method thereof.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 3 to 9 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 3, a substrate 200 is provided, the substrate 200 includes a first region I and a second region II adjacent to each other, the second region II includes a first edge region A1 and a middle region B1, and the first edge region A1 is adjacent to the first region I.
In this embodiment, the substrate 200 further includes: a third zone III, the second zone II being located between the first zone I and the third zone III; the second zone II further comprises: a second edge region A2, the intermediate region B1 being located between the first and second edge regions A1, A2, and the second edge region A2 being contiguous with the third region III.
In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium.
After providing the substrate 200, further comprising: a main trench is formed in the second region II. For specific processes, please refer to fig. 4 to fig. 6.
Referring to fig. 4, an initial mask layer 201 is formed on a substrate 200; a patterned layer 202 is formed on the initial mask layer 201, and an opening exposing a portion of the initial mask layer 201 is formed in the patterned layer 202.
In this embodiment, the initial mask layer includes: a first silicon oxide layer, a silicon nitride layer on the silicon oxide layer, and a second silicon oxide layer on the silicon nitride layer.
The patterned layer 202 is a single-layer structure or a multi-layer structure. In this embodiment, the patterned layer 202 is a sandwich multi-layer structure, and specifically includes: an amorphous carbon layer, a dielectric anti-reflective layer on the amorphous carbon layer, and a photoresist layer (not shown) on the dielectric anti-reflective layer.
In this embodiment, the dielectric anti-reflection layer is made of silicon oxycarbide. In other embodiments, the dielectric anti-reflective layer may also be made of silicon oxynitride.
Referring to fig. 5, the patterned layer 202 is used as a mask, a second etching process is used to etch the initial mask layer 201 until the top surface of the substrate 200 is exposed, a mask layer 203 and a mask opening 204 located in the mask layer 203 are formed, the mask opening 204 exposes the top surface of the second region II of the substrate 200, and an included angle α between a sidewall of the mask opening 204 and the surface of the substrate 200 is a preset included angle.
In this embodiment, the preset included angle is: 90-95 deg..
In this embodiment, the process parameters of the second etching process include: with a plasma etching process, the main etching gas includes: fluorine-containing etching gas SF 6 、CF 4 、CH 2 F 2 The method comprises the steps of carrying out a first treatment on the surface of the Gas concentration ratio SF 6 ：CF 4 ：CH 2 F 2 Equal to 1:1:1 to 1:10:20; the auxiliary etching gas includes: o (O) 2 、N 2 According to the dissociation degree under different conditions, the ratio of carbon particles, fluorine particles and oxygen particles is 1:1:1-3:6:1; bias voltage is 50V-1000V; the air pressure in the etching cavity is 1-10 mtorr. By adjusting the ratio of fluorine and oxygen radicals in the second etching process, the etching selectivity is improved, the consumption of the initial mask layer 201 is reduced, meanwhile, the side wall protection is added to the side wall deposited by etching byproducts, the bombardment of plasma on the side wall of the initial mask layer 201 is weakened, the etching rate of the side wall of the initial mask layer 201 is reduced, the vertical side wall is further obtained, and the roughness is improved. By protecting the sidewalls of the mask layer 203 from being more vertical, irregular elastic collisions (as compared to sloped and recessed sidewalls) of ions and radicals on the sidewalls of the mask layer 203 are reduced during subsequent etching. The ejected particles still have relatively high energy and randomly strike the bottom of the subsequently formed main trench and form a pit. Therefore, the vertical and well-protected ejection occurs on the side wall of the mask layer 203, and the micro pits at the bottom of the main trench are well controlled.
Referring to fig. 6, the second region II is etched using the mask layer 203 as a mask, and the main trench 205 is formed in the second region II.
In this embodiment, during the etching process of forming the main trench 205, by-products are formed or the exposed silicon material is oxidized to form an oxide layer, so that the by-products and the oxide layer need to be cleaned during the etching process to ensure that the etching is performed smoothly.
In this embodiment, the process of etching the second region II uses a wet etching process.
Referring to fig. 7, a first etching process is used to etch the first edge region A1 exposed by the main trench 205, a first edge trench 206 is formed in the first edge region A1, and the main trench 205 exposes the first edge trench 206.
In this embodiment, by forming the first edge trench 206 in the first edge region A1 and exposing the first edge trench 206 by the main trench 205, the fillet span of the bottom of the main trench 205 can be effectively reduced, so that the bottom fillet of the main trench 205 is smaller. Therefore, after the subsequent patterning process, the material doped with the epitaxial layer in part of the first fin part is reduced, and meanwhile, the problem that the germanium-silicon material in part of the second fin part is less can be reduced, so that the performance of the finally formed semiconductor structure is affected.
In this embodiment, the process parameters of the first etching process include: adopts a plasma etching process, and the main etching gas is CL 2 The method comprises the steps of carrying out a first treatment on the surface of the Bias voltage is 300V-1000V; the air pressure in the etching cavity is 1-10 mtorr. Due to CL 2 The gas has little by-product and the bottom rounded corners of the main trench 205 are relatively straight without by-product build-up. Since a part of the source of the rounded corners is the accumulation protection of byproducts at the bottom of the side walls. At this time, a larger bias voltage is applied to the plasma, so that the acceleration of ions in the plasma is increased, and the bombardment energy is improved. Compared to the middle region B1 position, the bombardment is concentrated at the bottom of the main trench 205 sidewall due to the blocking of the main trench 205 sidewall, thereby forming a first edge trench 206 in the first edge region A1.
In this embodiment, in the process of etching the first edge area A1 exposed by the main trench 205 by using the first etching process, the method further includes: the second edge region A2 exposed by the main trench 205 is etched, a second edge trench 207 is formed in the second edge region A2, and the main trench 205 exposes the second edge trench 207.
Referring to fig. 8, an epitaxial layer 208 is formed in the main trench 205 and the first edge trench 206, and the material of the epitaxial layer 208 is different from that of the substrate 200.
In this embodiment, the epitaxial layer 208 is formed in the main trench 205 by an epitaxial growth process.
In this embodiment, the material of the epitaxial layer 208 is silicon germanium.
In this embodiment, the epitaxial layer 208 is also formed within the second edge trench 207.
Referring to fig. 9, a patterning process is performed on the first region I of the substrate 200 and the epitaxial layer 208, so that the first region I of the substrate 200 forms a plurality of first fins 209 that are separated from each other, and the epitaxial layer 208 forms a plurality of second fins 210 that are separated from each other.
Note that in this embodiment, the mask layer 203 is removed before patterning; the epitaxial layer 208 is planarized until the top surface of the substrate 200 is exposed.
In this embodiment, in the process of forming the first fin 209 and the second fin 210, the method further includes: a patterning process is performed on the third region III of the substrate 200, so that a plurality of third fins 211 are formed in the third region III of the substrate 200.
In this embodiment, the first fin 209 is used to form an NMOS transistor; the second fin 210 is used to form a PMOS transistor. Because the material of the second fin 210 is germanium-silicon, the mobility of holes can be effectively improved by using the second fin 210 as the channel region of the formed PMOS transistor, so as to improve the performance of the finally formed semiconductor structure.
Accordingly, in an embodiment of the present invention, there is further provided a semiconductor structure, please continue to refer to fig. 9, including: a substrate 200, the substrate 200 comprising a first region I and a second region II adjacent to each other, the second region II comprising a first edge region A1 and a middle region B1, and the first edge region A1 being adjacent to the first region I; a main trench 205 located within the second region II; a first edge trench 206 located in the first edge region A1, the main trench 205 exposing the first edge trench 206; an epitaxial layer 208 is located within the main trench 205 and the first edge trench 206, the material of the epitaxial layer 208 being different from the material of the substrate 200.
In this embodiment, the first edge groove 206 can effectively reduce the fillet span of the bottom of the main groove 205, so that the bottom of the main groove 205 is smaller in fillet. Therefore, after the patterning process, the material doped with the epitaxial layer 208 in part of the first fin 209 is reduced, and meanwhile, the problem that the germanium-silicon material in part of the second fin 210 is less can be reduced, so that the performance of the finally formed semiconductor structure is affected.
In this embodiment, the substrate 200 further includes: a third zone III, the second zone II being located between the first zone I and the third zone III; the second zone II further comprises: a second edge region A2, the intermediate region B1 being located between the first and second edge regions A1, A2, and the second edge region A2 being contiguous with the third region III.
In this embodiment, further comprising: and a second edge groove 207 located in the second edge region A2, the main groove 205 exposing the second edge groove 207.
In this embodiment, the epitaxial layer 208 is also located within the second edge trench 207.
In this embodiment, the material of the substrate 200 is silicon; the material of the epitaxial layer 208 is germanium silicon.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising a first region and a second region adjacent to each other, the second region comprising a first edge region and a middle region, and the first edge region being adjacent to the first region;
forming a main trench in the second region;
etching the first edge area exposed by the main groove by adopting a first etching process, and forming a first edge groove in the first edge area, wherein the first edge groove is exposed by the main groove;
forming an epitaxial layer in the main groove and the first edge groove, wherein the material of the epitaxial layer is different from that of the substrate;
and carrying out a patterning process on the first region of the substrate and the epitaxial layer, so that a plurality of first fins which are mutually separated are formed in the first region of the substrate, and a plurality of second fins which are mutually separated are formed in the epitaxial layer.
2. The method of forming a semiconductor structure of claim 1, wherein the substrate further comprises: a third region, the second region being located between the first region and the third region; the second zone further comprises: a second edge region, the intermediate region being located between the first edge region and the second edge region, and the second edge region being contiguous with the third region.
3. The method of forming a semiconductor structure of claim 2, further comprising, during etching the first edge region exposed by the main trench using a first etching process: and etching the second edge region exposed by the main groove, and forming a second edge groove in the second edge region, wherein the second edge groove is exposed by the main groove.
4. The method of forming a semiconductor structure of claim 3, wherein the epitaxial layer is further formed within the second edge trench.
5. The method of forming a semiconductor structure of claim 1, wherein the process parameters of the first etching process comprise: adopts a plasma etching process, and the main etching gas is CL 2 The method comprises the steps of carrying out a first treatment on the surface of the Bias voltage is 300V-1000V; the air pressure in the etching cavity is 1-10 mtorr.
6. The method of forming a semiconductor structure of claim 1, wherein forming a main trench in the second region comprises: forming an initial mask layer on a substrate; forming a patterning layer on the initial mask layer, wherein an opening exposing part of the initial mask layer is formed in the patterning layer; etching the initial mask layer by using the patterned layer as a mask and adopting a second etching process until the top surface of the substrate is exposed, forming a mask layer and a mask opening positioned in the mask layer, wherein the mask opening exposes the top surface of a second region of the substrate, and an included angle between the side wall of the mask opening and the surface of the substrate is a preset included angle; and etching the second region by taking the mask layer as a mask, and forming the main groove in the second region.
7. The method of forming a semiconductor structure as claimed in claim 6, wherein the predetermined included angle is: 90-95 deg..
8. The method of forming a semiconductor structure of claim 6, wherein the process parameters of the second etching process comprise: with a plasma etching process, the main etching gas includes: fluorine-containing etching gas SF 6 、CF 4 、CH 2 F 2 The method comprises the steps of carrying out a first treatment on the surface of the Gas concentration ratio SF 6 ：CF 4 ：CH 2 F 2 Equal to 1:1:1 to 1:10:20; the auxiliary etching gas includes: o (O) 2 、N 2 According to the dissociation degree under different conditions, the carbon particles, fluorine particles and oxygen particlesThe ratio of the seeds is 1:1:1-3:6:1; bias voltage is 50V-1000V; the air pressure in the etching cavity is 1-10 mtorr.
9. The method of forming a semiconductor structure of claim 6, wherein the patterned layer is a single layer structure or a multi-layer structure.
10. The method of forming a semiconductor structure of claim 9, wherein when the patterned layer is a multi-layered structure, the patterned layer comprises: an amorphous carbon layer, a dielectric anti-reflective layer on the amorphous carbon layer, and a photoresist layer on the dielectric anti-reflective layer.
11. The method of forming a semiconductor structure of claim 1, wherein the epitaxial layer is formed within the main trench using an epitaxial growth process.
12. The method of forming a semiconductor structure of claim 1, wherein the material of the substrate comprises: silicon; the material of the epitaxial layer comprises: germanium silicon.
13. The method of forming a semiconductor structure of claim 1, wherein the first fin is used to form an NMOS transistor; the second fin portion is used for forming a PMOS transistor.
14. A semiconductor structure, comprising:
a substrate comprising a first region and a second region adjacent to each other, the second region comprising a first edge region and a middle region, and the first edge region being adjacent to the first region;
a main trench located within the second region;
a first edge trench in the first edge region, the main trench exposing the first edge trench;
and the epitaxial layer is positioned in the main groove and the first edge groove, and the material of the epitaxial layer is different from that of the substrate.
15. The semiconductor structure of claim 14, wherein the substrate further comprises: a third region, the second region being located between the first region and the third region; the second zone further comprises: a second edge region, the intermediate region being located between the first edge region and the second edge region, and the second edge region being contiguous with the third region.
16. The semiconductor structure of claim 15, further comprising: and a second edge groove in the second edge region, wherein the main groove exposes the second edge groove.
17. The semiconductor structure of claim 16, wherein the epitaxial layer is further located within the second edge trench.
18. The semiconductor structure of claim 14, wherein the material of the substrate comprises: silicon; the material of the epitaxial layer comprises: germanium silicon.
CN202210505380.9A 2022-05-10 2022-05-10 Semiconductor structure and forming method thereof Pending CN117080072A (en)

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