CN117012720A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN117012720A
CN117012720A CN202210468638.2A CN202210468638A CN117012720A CN 117012720 A CN117012720 A CN 117012720A CN 202210468638 A CN202210468638 A CN 202210468638A CN 117012720 A CN117012720 A CN 117012720A
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China
Prior art keywords
layer
edge
forming
region
trench
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CN202210468638.2A
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Chinese (zh)
Inventor
汪刘建
姜长城
王彦
张海洋
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210468638.2A priority Critical patent/CN117012720A/en
Publication of CN117012720A publication Critical patent/CN117012720A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first region and a second region, and the second region comprises a first edge region and a middle region; forming a first edge trench in the first edge region, the first edge trench having a first aspect ratio; filling a first edge layer in the first edge groove; forming an intermediate trench in the intermediate region; removing the first edge layer to form an epitaxial groove, wherein the epitaxial groove has a second depth-to-width ratio, and the first depth-to-width ratio is larger than the second depth-to-width ratio; an epitaxial layer is formed within the epitaxial trench. Because the first depth-to-width ratio of the first edge groove is higher, the fillet span of the bottom of the first edge groove is smaller, and the fillet of the bottom of the epitaxial groove is smaller. Therefore, after the patterning process, the material doped with the epitaxial layer in part of the first fin part is reduced, and meanwhile, the problem that the silicon germanium material in part of the second fin part is less can be reduced, so that the performance of the finally formed semiconductor structure is affected.

Description

Method for forming semiconductor structure
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a method for forming a semiconductor structure.
Background
With the development of semiconductor technology, the feature size of devices in integrated circuits is becoming smaller. However, as the feature size of devices becomes smaller, the length of the channel region between the source and drain becomes shorter. When the length of the channel region is reduced to a certain value, short channel effects are generated, and the performance of the device is affected by the existence of the short channel effects, so that further reduction of the feature size of the device in the integrated circuit is prevented.
In order to overcome the short channel effect in the prior art and promote the development of semiconductor technology, by changing the channel material into a germanium-silicon (SiGe) material, the performance of the device can be greatly improved by taking the germanium-silicon material as the material of the channel region because the germanium-silicon material has high hole mobility which is 6-25 times that of the silicon (Si) material.
However, the prior art silicon germanium channel transistors still have a number of problems.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor structure, which can effectively improve the performance of the finally formed semiconductor structure.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate comprising a first region and a second region adjacent to each other, the second region comprising a first edge region and a middle region, and the first edge region being adjacent to the first region; forming a first edge trench within the first edge region, the first edge trench having a first aspect ratio; filling a first edge layer in the first edge groove, wherein the material of the first edge layer is different from that of the substrate; forming an intermediate trench in the intermediate region, the intermediate trench exposing the first edge layer sidewall; removing the first edge layer to form an epitaxial groove, wherein the epitaxial groove comprises the first edge groove and the middle groove, the epitaxial groove has a second depth-to-width ratio, and the first depth-to-width ratio is larger than the second depth-to-width ratio; forming an epitaxial layer in the epitaxial groove, wherein the material of the epitaxial layer is different from that of the substrate; and carrying out a patterning process on the first region of the substrate and the epitaxial layer, so that a plurality of first fins which are mutually separated are formed in the first region of the substrate, and a plurality of second fins which are mutually separated are formed in the epitaxial layer.
Optionally, the substrate further includes: a third region, the second region being located between the first region and the third region; the second zone further comprises: a second edge region, the intermediate region being located between the first edge region and the second edge region, and the second edge region being contiguous with the third region.
Optionally, in the process of forming the first edge groove, the method further includes: forming a second edge trench in the second edge region, wherein the second edge trench has a third aspect ratio, and the first aspect ratio is equal to the third aspect ratio.
Optionally, in the process of forming the first edge layer, the method further includes: and filling a second edge layer in the second edge groove, wherein the material of the first edge layer is the same as that of the second edge layer.
Optionally, the intermediate trench also exposes a sidewall of the second edge layer.
Optionally, in the process of removing the first edge layer, the method further includes: removing the second edge layer; the epitaxial trench further includes the second edge trench.
Optionally, the range of the second aspect ratio is: 0.05 to 0.40.
Optionally, the range of the first aspect ratio is: 1.5 to 6.0.
Optionally, the material of the first edge layer includes: and (3) silicon oxide.
Optionally, the method for forming the first edge groove in the first edge area includes: forming a mask layer on the substrate; forming a first photoresist layer on the mask layer, wherein the first photoresist layer exposes the top surface of the mask layer on the second region; forming a first sacrificial layer on the side wall of the first photoresist layer, wherein the first sacrificial layer covers the top surface of the mask layer on the first edge area, and the material of the first sacrificial layer is different from the material of the first photoresist layer and the mask layer; forming a second photoresist layer, wherein the second photoresist layer covers the top surface of the mask layer positioned on the middle area; and removing the first sacrificial layer, and etching the mask layer and the first edge region by taking the first photoresist layer and the second photoresist layer as masks to form the first edge groove.
Optionally, the material of the first sacrificial layer includes: silicon oxide; the mask layer comprises the following materials: silicon nitride.
Optionally, the method for forming the first sacrificial layer on the side wall of the first photoresist layer includes: forming a sacrificial material layer on a top surface of the mask layer, sidewalls of the first photoresist layer, and a top surface of the mask layer on the second region; and etching the sacrificial material layer until the top surfaces of the first photoresist layer and the mask layer are exposed, so as to form the first sacrificial layer.
Optionally, the forming process of the sacrificial material layer includes: atomic layer deposition process.
Optionally, an epitaxial growth process is used to form the epitaxial layer in the epitaxial trench.
Optionally, the material of the substrate includes: silicon; the material of the epitaxial layer comprises: silicon germanium.
Optionally, the first fin portion is used for forming an NMOS transistor; the second fin portion is used for forming a PMOS transistor.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the forming method of the technical scheme of the invention, the first depth-to-width ratio of the first edge groove is high, so that the fillet span of the bottom of the first edge groove is smaller. The epitaxial trench formed later comprises the first edge trench and the middle trench, and the rounded corner at the bottom of the epitaxial trench is the rounded corner at the bottom of the first edge trench, so that the rounded corner at the bottom of the epitaxial trench is smaller. Therefore, after patterning, the material doped with the epitaxial layer in part of the first fin portion is reduced, and meanwhile, the problem that the material doped with the epitaxial layer in part of the second fin portion is less can be solved, so that the performance of the finally formed semiconductor structure is affected.
Further, the materials of the first edge layer and the substrate are different, so that etching damage to the first edge layer in the subsequent process of etching and removing part of the second region is reduced.
Further, the method for forming the first edge groove in the first edge area comprises the following steps: forming a mask layer on the substrate; forming a first photoresist layer on the mask layer, wherein the first photoresist layer exposes the top surface of the mask layer on the second region; forming a first sacrificial layer on the side wall of the first photoresist layer, wherein the first sacrificial layer covers the top surface of the mask layer on the first edge area, and the material of the first sacrificial layer is different from the material of the first photoresist layer and the mask layer; forming a second photoresist layer, wherein the second photoresist layer covers the top surface of the mask layer positioned on the middle area; and removing the first sacrificial layer, and etching the mask layer and the first edge region by taking the first photoresist layer and the second photoresist layer as masks to form the first edge groove. Because the material of the first sacrificial layer is different from the material of the first photoresist layer and the mask layer, the first sacrificial layer can be removed by adopting a self-alignment process, and the first sacrificial layer is prevented from being removed by adopting a photomask process, so that the production cost is reduced, and the processing efficiency is improved.
Drawings
FIGS. 1-2 are schematic views of steps of a method for forming a semiconductor structure;
fig. 3 to 12 are schematic views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As described in the background, there are still a number of problems with prior art sige material channel transistors. The following will make a detailed description with reference to the accompanying drawings.
Fig. 1-2 are schematic views illustrating the steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes a first region I and a second region II adjacent to each other; forming a mask layer 101 on the substrate 100, the mask layer 101 exposing a top surface of the second region II; etching the second region II by using the mask layer 101 as a mask, and forming a trench (not labeled) in the second region II; an epitaxial layer 102 is formed in the trench by an epitaxial growth process, and the material of the epitaxial layer 102 is different from the material of the substrate 100.
Referring to fig. 2, a patterning process is performed on the first region I of the substrate 100 and the epitaxial layer 102, so that a plurality of first fins 103 are formed in the first region I of the substrate 100, and a plurality of second fins 104 are formed in the epitaxial layer 102.
In this embodiment, the material of the substrate 100 is silicon, and the material of the epitaxial layer 102 is silicon germanium, so that the material of the corresponding first fin 103 is silicon, and the material of the second fin 104 is silicon germanium. The first fin 103 is then used as a channel region of the formed NMOS transistor, and the second fin 104 is used as a channel region of the formed PMOS transistor, so that the channel region of the sige material can effectively improve the mobility of holes, thereby improving the performance of the finally formed semiconductor structure.
In this embodiment, because the depth-to-width ratio of the trench is small, in the process of etching to form the trench, the problem of lateral etching is more prominent along the direction perpendicular to the sidewall of the trench, so that a fillet structure with a larger span appears at the bottom of the formed trench. And when the span dimension d2 of the rounded corner structure is larger than the preset spacing dimension d1, after the patterning process, a part of the first fin 103 is doped with silicon germanium material, and a part of the second fin 104 is doped with less silicon germanium material, so that the performance of the finally formed semiconductor structure is affected.
On the basis, the invention provides a method for forming a semiconductor structure, and the first depth-to-width ratio of the first edge groove is higher, so that the fillet span of the bottom of the first edge groove is smaller. The epitaxial trench formed later comprises the first edge trench and the middle trench, and the rounded corner at the bottom of the epitaxial trench is the rounded corner at the bottom of the first edge trench, so that the rounded corner at the bottom of the epitaxial trench is smaller. Therefore, after patterning, the material doped with the epitaxial layer in part of the first fin part is reduced, and meanwhile, the problem that part of the silicon germanium material in the second fin part is less can be reduced, so that the performance of the finally formed semiconductor structure is affected.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 3 to 12 are schematic views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 3, a substrate 200 is provided, the substrate includes a first region I and a second region II adjacent to each other, the second region II includes a first edge region A1 and a middle region B1, and the first edge region A1 is adjacent to the first region I.
In this embodiment, the substrate 200 further includes: a third zone III, the second zone II being located between the first zone I and the third zone III; the second zone II further comprises: a second edge region A2, the intermediate region B1 being located between the first and second edge regions A1, A2, and the second edge region A2 being contiguous with the third region III.
In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium.
After providing the substrate 200, further comprising: forming a first edge groove in the first edge area A1; and forming a second edge groove in the second edge area A2 in the process of forming the first edge groove. For a specific process, please refer to fig. 4 to fig. 7.
Referring to fig. 4, a mask layer 201 is formed on the substrate 200; a first photoresist layer 202 is formed on the mask layer 201, the first photoresist layer 202 exposing a top surface of the mask layer 201 on the second region II.
In this embodiment, the first photoresist layer 202 specifically covers the mask layer 201 located on the first region I and the third region III.
In this embodiment, the mask layer 201 is made of silicon nitride.
In this embodiment, the first photoresist layer 202 has a sandwich structure, and specifically includes: a first amorphous carbon layer, a first dielectric anti-reflective layer on the first amorphous carbon layer, and a first photoresist (not shown) on the first dielectric anti-reflective layer.
In this embodiment, the material of the first dielectric anti-reflection layer is silicon oxycarbide. In other embodiments, the material of the first dielectric anti-reflection layer may also be silicon oxynitride.
Referring to fig. 5, a first sacrificial layer 203 is formed on a sidewall of the first photoresist layer 202, the first sacrificial layer 203 covers a top surface of the mask layer 201 on the first edge region A1, and a material of the first sacrificial layer 203 is different from a material of the first photoresist layer 202 and the mask layer 201.
In this embodiment, in the process of forming the first sacrificial layer 203, further includes: a second sacrificial layer 204 is formed on the sidewall of the first photoresist layer 202, the second sacrificial layer 204 covers the top surface of the mask layer 201 on the second edge region A2, and the material of the second sacrificial layer 204 is different from the materials of the first photoresist layer 202 and the mask layer 201.
In this embodiment, the material of the first sacrificial layer 203 is silicon oxide; the material of the second sacrificial layer 204 is silicon oxide.
In this embodiment, the method for forming the first sacrificial layer 203 and the second sacrificial layer 204 on the sidewall of the first photoresist layer 202 includes: forming a sacrificial material layer (not shown) on a top surface of the mask layer 201, sidewalls and a top surface of the first photoresist layer 202 on the second region II; the sacrificial material layer is etched back until the top surfaces of the first photoresist layer 202 and the mask layer 201 are exposed, forming the first sacrificial layer 203 and the second sacrificial layer 204.
In this embodiment, the sacrificial material layer is formed by an atomic layer deposition process.
Referring to fig. 6, a second photoresist layer 205 is formed, and the second photoresist layer 205 covers the top surface of the mask layer 201 on the middle region B1.
In this embodiment, the method for forming the second photoresist layer 205 includes: forming a photoresist material layer (not shown) on the top surface of the mask layer 201 on the intermediate region B1 and the top surfaces of the first sacrificial layer 203, the second sacrificial layer 204 and the first photoresist layer 202; the photoresist material layer is planarized until the top surfaces of the first sacrificial layer 203 and the second sacrificial layer 204 are exposed, and the second photoresist layer 205 is formed.
In this embodiment, a heat treatment process is used for the planarization process of the photoresist material layer.
In this embodiment, the second photoresist layer 205 is also in a sandwich structure, and specifically includes: a second amorphous carbon layer, a second dielectric anti-reflective layer on the second amorphous carbon layer, and a second photoresist (not shown) on the second dielectric anti-reflective layer.
In this embodiment, the second dielectric anti-reflection layer is made of silicon oxycarbide. In other embodiments, the second dielectric anti-reflection layer may also be made of silicon oxynitride.
Referring to fig. 7, the first sacrificial layer 203 is removed, and the mask layer 201 and the first edge region A1 are etched with the first photoresist layer 202 and the second photoresist layer 205 as masks, so as to form the first edge trench 206.
In this embodiment, in the process of removing the first sacrificial layer 203, the method further includes: removing the second sacrificial layer 204; in forming the first edge trench 206, further comprising: the first photoresist layer 202 and the second photoresist layer 205 are used as masks to etch the mask layer 201 and the second edge area A2, thereby forming the second edge trench 207.
In this embodiment, since the material of the first sacrificial layer 203 is different from the material of the first photoresist layer 202 and the mask layer 201, the material of the second sacrificial layer 204 is different from the material of the first photoresist layer 202 and the mask layer 201. Therefore, the first sacrificial layer 203 and the second sacrificial layer 204 can be removed by a self-aligned process, so that the first sacrificial layer 203 and the second sacrificial layer 204 are prevented from being removed by a photomask process, thereby reducing the production cost and improving the processing efficiency.
In this embodiment, the first edge trench 206 has a first aspect ratio, the second edge trench 207 has a third aspect ratio, and the first aspect ratio and the third aspect ratio are equal.
In this embodiment, the range of the first aspect ratio is: 1.5 to 6.0; the range of the third aspect ratio is as follows: 1.5 to 6.0.
Referring to fig. 8, the first edge trench 206 is filled with a first edge layer 208, and the material of the first edge layer 208 is different from the material of the substrate 200.
In this embodiment, in the process of forming the first edge layer 208, the method further includes: a second edge layer 209 is filled in the second edge groove 207, and the material of the first edge layer 208 is the same as that of the second edge layer 209.
In this embodiment, the material of the first edge layer 208 is silicon oxide; the second edge layer 209 is made of silicon oxide. By the materials of the first edge layer 208 and the substrate 200 being different, the materials of the second edge layer 209 and the substrate 200 being different, the subsequent etching damage to the first edge layer 208 and the second edge layer 209 in the process of etching and removing part of the second region II is reduced.
In this embodiment, the forming method of the first edge layer 208 and the second edge layer 209 includes: forming an edge material layer (not shown) on the first photoresist layer 202 and the second photoresist layer 205 within the first edge trench 206 and the second edge trench 207; the edge material layer is planarized until top surfaces of the first photoresist layer 202 and the second photoresist layer 205 are exposed, forming the first edge layer 208 and the second edge layer 209.
In this embodiment, since the top of the first photoresist layer 202 is the first photoresist, the top of the second photoresist layer 205 is the second photoresist, the materials of the first photoresist and the second photoresist are softer, and the planarization process is not suitable for the chemical mechanical polishing process. Therefore, the planarization process employs an etch-back process, and etching is stopped on the first photoresist and the second photoresist. By modulating the etching gas to a suitable selection ratio, it is ensured that only the edge material layer is etched without damaging the first photoresist and the second photoresist. The edge material layer located on the first photoresist and the second photoresist is removed due to steric hindrance, but the edge material layer in the first edge trench 206 and the second edge trench 207 remains because etching gas is difficult to enter the first edge trench 206 and the second edge trench 207 having high aspect ratio.
In other embodiments, the first photoresist and the first dielectric anti-reflective layer of the first photoresist layer may be removed to expose the harder first amorphous carbon layer, the second photoresist and the second dielectric anti-reflective layer of the second photoresist layer may be removed to expose the harder second amorphous carbon layer, and at this time, the planarization of the edge material layer may be performed by using a chemical mechanical polishing process.
Note that, in this embodiment, the first edge layer 208 extends onto the first edge trench 206; the second edge layer 209 extends onto the second edge trench 207.
Referring to fig. 9, an intermediate trench 210 is formed in the intermediate region B1, and the intermediate trench 210 exposes the sidewall of the first edge layer 208.
Note that, in this embodiment, before forming the intermediate trench 210, the method further includes: removing the second photoresist layer 205, the first and second edge layers 208 and 209 between the first and second photoresist layers 201 and 205, and the mask layer 201 on the intermediate region B1; after the intermediate trench 210 is formed, the first photoresist layer 202 is removed.
In this embodiment, the intermediate trench 210 also exposes a sidewall of the second edge layer 209.
Referring to fig. 10, after the intermediate trench 210 is formed, the first edge layer 208 is removed to form an epitaxial trench 211, and the epitaxial trench 211 includes the first edge trench 206 and the intermediate trench 210, and the epitaxial trench 211 has a second aspect ratio, and the first aspect ratio is greater than the second aspect ratio.
In this embodiment, in the process of removing the first edge layer 208, the method further includes: removing the second edge layer 209; the epitaxial trench 211 further includes the second edge trench 207.
In this embodiment, the second aspect ratio ranges from: 0.05 to 0.40.
Referring to fig. 11, an epitaxial layer 212 is formed in the epitaxial trench 211, and the material of the epitaxial layer 212 is different from that of the substrate 200.
In this embodiment, the epitaxial layer 212 is formed in the epitaxial trench 211 by an epitaxial growth process.
In this embodiment, the material of the epitaxial layer 212 is silicon germanium.
In this embodiment, the epitaxial layer 212 extends onto the epitaxial trench 211.
Referring to fig. 12, a patterning process is performed on the first region I of the substrate 200 and the epitaxial layer 212, so that a plurality of first fins 213 are formed in the first region I of the substrate 200, and a plurality of second fins 214 are formed in the epitaxial layer 212.
In this embodiment, since the first aspect ratio of the first edge trench 206 is high, the fillet span of the bottom of the first edge trench 206 is small. The epitaxial trench 211 formed later includes the first edge trench 206 and the intermediate trench 210, and the rounded corner at the bottom of the epitaxial trench 211 is the rounded corner at the bottom of the first edge trench 206, so that the rounded corner at the bottom of the epitaxial trench 211 is smaller. This ensures that after patterning, the material doped with the epitaxial layer 212 in part of the first fin 213 is reduced, and at the same time, the problem of less material doped with the epitaxial layer in part of the second fin 214 is reduced, thereby affecting the performance of the finally formed semiconductor structure.
In this embodiment, the mask layer 201 is removed before patterning; the epitaxial layer 212 is planarized until the top surface of the substrate 200 is exposed.
In this embodiment, in the process of forming the first fin 213 and the second fin 214, the method further includes: a patterning process is performed on the third region III of the substrate 200, so that a plurality of third fins 215 are formed in the third region III of the substrate 200, which are separated from each other.
In this embodiment, the first fin 213 is used to form an NMOS transistor; the second fin 214 is used to form a PMOS transistor. Because the second fin portion 214 is made of silicon germanium, the mobility of holes can be effectively improved by using the second fin portion 214 as a channel region of the formed PMOS transistor, so that the performance of the finally formed semiconductor structure can be improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising a first region and a second region adjacent to each other, the second region comprising a first edge region and a middle region, and the first edge region being adjacent to the first region;
forming a first edge trench within the first edge region, the first edge trench having a first aspect ratio;
filling a first edge layer in the first edge groove, wherein the material of the first edge layer is different from that of the substrate;
forming an intermediate trench in the intermediate region, the intermediate trench exposing the first edge layer sidewall;
removing the first edge layer to form an epitaxial groove, wherein the epitaxial groove comprises the first edge groove and the middle groove, the epitaxial groove has a second depth-to-width ratio, and the first depth-to-width ratio is larger than the second depth-to-width ratio;
forming an epitaxial layer in the epitaxial groove, wherein the material of the epitaxial layer is different from that of the substrate;
and carrying out a patterning process on the first region of the substrate and the epitaxial layer, so that a plurality of first fins which are mutually separated are formed in the first region of the substrate, and a plurality of second fins which are mutually separated are formed in the epitaxial layer.
2. The method of forming a semiconductor structure of claim 1, wherein the substrate further comprises: a third region, the second region being located between the first region and the third region; the second zone further comprises: a second edge region, the intermediate region being located between the first edge region and the second edge region, and the second edge region being contiguous with the third region.
3. The method of forming a semiconductor structure of claim 2, further comprising, during forming the first edge trench: forming a second edge trench in the second edge region, wherein the second edge trench has a third aspect ratio, and the first aspect ratio is equal to the third aspect ratio.
4. The method of forming a semiconductor structure of claim 3, further comprising, during forming the first edge layer: and filling a second edge layer in the second edge groove, wherein the material of the first edge layer is the same as that of the second edge layer.
5. The method of forming a semiconductor structure of claim 4, wherein said intermediate trench further exposes sidewalls of said second edge layer.
6. The method of forming a semiconductor structure of claim 5, wherein during removing the first edge layer, further comprising: removing the second edge layer; the epitaxial trench further includes the second edge trench.
7. The method of forming a semiconductor structure of claim 6, wherein the second aspect ratio ranges from: 0.05 to 0.40.
8. The method of forming a semiconductor structure of claim 1, wherein the first aspect ratio ranges from: 1.5 to 6.0.
9. The method of forming a semiconductor structure of claim 1, wherein the material of the first edge layer comprises: and (3) silicon oxide.
10. The method of forming a semiconductor structure of claim 1, wherein forming a first edge trench in the first edge region comprises: forming a mask layer on the substrate; forming a first photoresist layer on the mask layer, wherein the first photoresist layer exposes the top surface of the mask layer on the second region; forming a first sacrificial layer on the side wall of the first photoresist layer, wherein the first sacrificial layer covers the top surface of the mask layer on the first edge area, and the material of the first sacrificial layer is different from the material of the first photoresist layer and the mask layer; forming a second photoresist layer, wherein the second photoresist layer covers the top surface of the mask layer positioned on the middle area; and removing the first sacrificial layer, and etching the mask layer and the first edge region by taking the first photoresist layer and the second photoresist layer as masks to form the first edge groove.
11. The method of forming a semiconductor structure of claim 10, wherein the material of the first sacrificial layer comprises: silicon oxide; the mask layer comprises the following materials: silicon nitride.
12. The method of forming a semiconductor structure of claim 10, wherein forming a first sacrificial layer on sidewalls of the first photoresist layer comprises: forming a sacrificial material layer on a top surface of the mask layer, sidewalls of the first photoresist layer, and a top surface of the mask layer on the second region; and etching the sacrificial material layer until the top surfaces of the first photoresist layer and the mask layer are exposed, so as to form the first sacrificial layer.
13. The method of forming a semiconductor structure of claim 12, wherein the process of forming the layer of sacrificial material comprises: atomic layer deposition process.
14. The method of forming a semiconductor structure of claim 1, wherein the epitaxial layer is formed within the epitaxial trench using an epitaxial growth process.
15. The method of forming a semiconductor structure of claim 1, wherein the material of the substrate comprises: silicon; the material of the epitaxial layer comprises: silicon germanium.
16. The method of forming a semiconductor structure of claim 1, wherein the first fin is used to form an NMOS transistor; the second fin portion is used for forming a PMOS transistor.
CN202210468638.2A 2022-04-29 2022-04-29 Method for forming semiconductor structure Pending CN117012720A (en)

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