CN114792628A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114792628A
CN114792628A CN202110106482.9A CN202110106482A CN114792628A CN 114792628 A CN114792628 A CN 114792628A CN 202110106482 A CN202110106482 A CN 202110106482A CN 114792628 A CN114792628 A CN 114792628A
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Prior art keywords
layer
forming
material layer
gate
side wall
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CN202110106482.9A
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孙鹏
林先军
金懿
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110106482.9A priority Critical patent/CN114792628A/en
Publication of CN114792628A publication Critical patent/CN114792628A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66606—Lateral single gate silicon transistors with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

A method of forming a semiconductor structure, comprising: providing a substrate; forming a plurality of initial pseudo gate structures on a substrate, wherein each initial gate structure comprises a first pseudo gate layer, a first mask layer and a second pseudo gate layer; forming a side wall material layer on the side wall and the top surface of the initial pseudo gate structure; forming a dielectric material layer on a substrate; and performing first planarization treatment on the dielectric material layer and the side wall material layer until the top surface of the second pseudo gate layer is exposed, wherein the grinding rate of the first planarization treatment on the second pseudo gate layer is less than the grinding rates of the dielectric material layer and the side wall material layer. Through the scheme, the first planarization treatment can be guaranteed to be stopped on the surface of the second pseudo gate layer, a smooth treatment interface is provided, and meanwhile, the uniformity of the height of the initial side wall is effectively improved. And the top surface of the formed initial dielectric layer is higher than that of the first pseudo gate layer, so that the problem of short circuit of the subsequent adjacent gate structures can be effectively avoided, and the performance of the formed semiconductor structure is improved.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
With the reduction of technical nodes, the traditional gate dielectric layer is continuously thinned, the leakage amount of a transistor is increased, and the problems of power consumption waste of a semiconductor device and the like are caused. To solve the above problems, the prior art provides a solution to replace the polysilicon gate with a metal gate. Wherein, the gate last process is a main process for forming the metal gate.
However, in the gate last process, the metal material of the metal gate deteriorates the isolation performance of the dielectric layer in the semiconductor structure, thereby affecting the performance of the semiconductor structure.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for forming a semiconductor structure, which can effectively improve the uniformity of the heights of an initial side wall and a second pseudo gate layer, and the top surface of a formed initial dielectric layer is higher than that of a first pseudo gate layer, so that the problem of short circuit of a subsequent adjacent gate structure can be effectively avoided, and the performance of the formed semiconductor structure is improved.
In order to solve the above problem, the present invention further provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of mutually-separated initial pseudo gate structures on the substrate, wherein each initial gate structure comprises a first pseudo gate layer, a first mask layer positioned on the first pseudo gate layer and a second pseudo gate layer positioned on the first mask layer; forming a side wall material layer on the side wall and the top surface of the initial pseudo gate structure; forming a dielectric material layer on the substrate, wherein the dielectric material layer covers the side wall of the side wall material layer; and performing first planarization treatment on the medium material layer and the side wall material layer until the top surface of the second pseudo gate layer is exposed to form an initial medium layer and an initial side wall, wherein the grinding rate of the first planarization treatment on the second pseudo gate layer is smaller than the grinding rates of the medium material layer and the side wall material layer, and the grinding rates of the first planarization treatment on the medium material layer and the side wall material layer are within a preset grinding rate range.
Optionally, after the first planarization treatment, the method further includes: removing the second pseudo gate layer and the initial side wall positioned on the side wall of the second pseudo gate layer to form a side wall; performing second planarization treatment on the initial dielectric layer until the top surface of the first mask layer is exposed to form a dielectric layer, wherein the grinding rate of the second planarization treatment on the initial dielectric layer is greater than that of the first mask layer; after the dielectric layer is formed, the first mask layer and the side wall of the first mask layer are removed, a first opening is formed in the dielectric layer, and the first opening exposes the top surface of the first pseudo-gate layer.
Optionally, after removing the first mask layer, the method further includes: removing the first pseudo gate layer, and forming a second opening in the dielectric layer at the bottom of the first opening; and forming a gate structure in the second opening.
Optionally, the forming method of the gate structure includes: forming a grid material layer in the first opening, the second opening and the surface of the dielectric layer; and carrying out third planarization treatment on the grid material layer and the dielectric layer until the top surface of the side wall is exposed, and forming the grid structure.
Optionally, the third planarization process includes: and (5) carrying out a chemical mechanical polishing process.
Optionally, the initial pseudo gate structure further includes: the second mask layer is positioned on the second pseudo gate layer, and the first protective layer is positioned on the second mask layer.
Optionally, the method for forming the initial pseudo gate structure includes: forming a first dummy gate material layer on the substrate; forming a first dummy gate material layer on the first dummy gate material layer; forming a second dummy gate material layer on the first mask material layer; forming a second mask material layer on the second dummy gate material layer; forming a patterned first protective layer on part of the second mask material layer; and etching the first pseudo gate material layer, the first mask material layer, the second pseudo gate material layer and the second mask material layer by taking the first protection layer as a mask to form the initial pseudo gate structure.
Optionally, the forming process of the side wall material layer includes: and (3) an atomic layer deposition process.
Optionally, the material of the dielectric material layer includes: and (3) silicon oxide.
Optionally, the material of the side wall material layer includes: silicon nitride.
Optionally, the material of the first dummy gate layer includes: polycrystalline silicon; the material of the second dummy gate layer comprises: polycrystalline silicon.
Optionally, the material of the first mask layer includes: silicon nitride.
Optionally, the first planarization process includes: and (5) carrying out a chemical mechanical polishing process.
Optionally, the second planarization process includes: and (5) carrying out a chemical mechanical polishing process.
Optionally, after forming the dielectric layer and before removing the first mask layer, the method further includes: forming a patterning layer on the dielectric layer and the first mask layer, wherein the patterning layer exposes a part of the top surface of the first mask layer; etching the first mask layer and the first pseudo gate layer by taking the patterning layer as a mask, and forming an isolation opening in the dielectric layer; an isolation structure is formed within the isolation opening.
Optionally, the isolation structure includes: the top surface of the first isolation layer is flush with the top surface of the first pseudo gate layer, and the top surface of the second protection layer is flush with the top surface of the dielectric layer.
Optionally, the substrate includes: the initial pseudo-gate structure crosses the fin part and covers partial side wall and the top surface of the fin part.
Optionally, before forming the initial dummy gate structure, the method further includes: and forming a second isolation layer on the substrate, wherein the second isolation layer covers part of the side wall of the fin part, and the top surface of the second isolation layer is lower than that of the fin part.
Optionally, the forming method of the dielectric material layer includes: forming a medium material film on the substrate, wherein the medium material film covers the side wall material layer; and performing fourth planarization treatment on the dielectric material film until the surface of the side wall material layer is exposed to form the dielectric material layer.
Optionally, widths of the plurality of initial dummy gate structures are different, and distances between adjacent initial dummy gate structures are different.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the forming method of the technical scheme of the invention, the initial grid structure comprises a first pseudo grid layer, a first mask layer positioned on the first pseudo grid layer and a second pseudo grid layer positioned on the first mask layer. The grinding rate of the first planarization treatment on the second pseudo gate layer is smaller than that of the medium material layer and the side wall material layer, and the grinding rate of the first planarization treatment on the medium material layer and the side wall material layer is within a preset grinding rate range, so that the first planarization treatment can be stopped on the surface of the second pseudo gate layer, a smooth treatment interface is provided, and meanwhile, the uniformity of the height of the formed initial side wall is effectively improved.
In addition, the top surface of the formed initial dielectric layer is higher than the top surface of the first pseudo gate layer, so that the top surface of the subsequently formed dielectric layer is also higher than the top surface of the first pseudo gate layer, even if a gate material layer is remained on the surface of the dielectric layer in the subsequent gate structure forming process, the dielectric layer higher than the first pseudo gate layer can be removed in the subsequent gate structure forming process by flattening the gate material layer, and at the moment, the gate material layer on the surface of the dielectric layer can be removed together, so that the problem of short circuit of the adjacent gate structure is effectively avoided, and the performance of the finally formed semiconductor structure is improved.
Drawings
Fig. 1 to 2 are schematic structural views of a semiconductor structure;
FIGS. 3-4 are schematic structural diagrams of another semiconductor structure;
fig. 5 to 13 are schematic structural diagrams of steps of a semiconductor structure forming method according to an embodiment of the invention.
Detailed Description
As described in the background, the isolation performance of the dielectric layer formed in the prior art becomes poor, thereby affecting the performance of the semiconductor structure. The following detailed description will be made in conjunction with the accompanying drawings.
Fig. 1 to fig. 2 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, where the substrate 100 has a plurality of dummy gate structures 101 separated from each other, and the dummy gate structures 101 include a dummy gate layer, a mask layer located on the dummy gate layer, and sidewalls (not shown) located on the mask layer and sidewalls of the dummy gate layer; forming an initial dielectric layer (not shown) on the substrate 100 and the dummy gate structure 101; and flattening the initial dielectric layer until the top surface of the pseudo gate layer is exposed to form a dielectric layer 102.
Referring to fig. 2, the dummy gate layer is removed, a gate opening is formed in the dielectric layer 102, and a gate structure 103 is formed in the gate opening.
In this embodiment, the material of the initial dielectric layer includes: silicon oxide; the process for forming the initial dielectric layer comprises the following steps: a fluid chemical vapor deposition process; the mask layer is made of materials including: silicon nitride.
However, the semiconductor structure prepared by the above method has poor performance because:
in this embodiment, the initial dielectric layer is planarized by a chemical mechanical polishing process until the top surface of the dummy gate layer is exposed, thereby forming the dielectric layer 102. The mask layer is also removed during planarization of the initial dielectric layer. Since the mask layer and the initial dielectric layer are made of different materials, the polishing rate of the initial dielectric layer by the planarization is greater than that of the mask layer, and thus when the planarization is stopped on the surface of the dummy gate layer, a recess is formed on the dielectric layer 102 (as shown in a part a in fig. 1).
Due to the need to form the gate structure 103 in the gate opening subsequently, the method for forming the gate structure 103 includes: forming a gate material layer in the gate opening and on the dielectric layer 102; and flattening the grid material layer until the top surfaces of the side walls are exposed. When the gate material layer is planarized, the gate material layer is easily deposited at the recess of the dielectric layer 102, and because the gate material layer has conductivity, the deposited gate material layer is removed from the recess of the dielectric layer 102, which easily causes short circuit of the adjacent gate structure 103, thereby affecting the performance of the semiconductor structure.
In order to solve the above problems, another method for forming a semiconductor structure is proposed in the prior art, which will be described in detail below with reference to the accompanying drawings.
Fig. 3 to 4 are schematic structural diagrams of steps of another method for forming a semiconductor structure.
Referring to fig. 3, a substrate 200 is provided, where the substrate 200 has a plurality of mutually discrete dummy gate structures 201, where the dummy gate structures 201 include a dummy gate layer, a mask layer located on the dummy gate layer, sidewalls located on the mask layer and the dummy gate layer, and sidewalls (not shown) on the top surface of the mask layer; removing the side wall on the top surface of the mask layer; forming an initial dielectric layer on the substrate 200 and the dummy gate structure 201; planarizing the initial dielectric layer (not shown) until the top surface of the mask layer is exposed to form a dielectric layer 202; after the dielectric layer 202 is formed, the mask layer is removed.
Referring to fig. 4, the dummy gate layer is removed, a gate opening is formed in the dielectric layer 202, and a gate structure 203 is formed in the gate opening.
In this embodiment, the top surface of the formed dielectric layer 202 is higher than the top surface of the dummy gate layer, and even though the deposited gate material layer is also recessed in the dielectric layer 202 during the process of forming the gate structure 203, the dielectric layer 202 higher than the dummy gate layer is removed during subsequent planarization of the gate material layer, so that the recessed gate material layer is removed together, thereby avoiding the short circuit problem of the adjacent gate structure 203.
In this embodiment, the mask layers of the dummy gate structures 201 are located at the same level, and therefore, in order to level the surface of the dielectric layer 202 after planarization, the final planarization process needs to be stopped on the mask layers. Because the materials of the side wall and the mask layer are the same, and the side wall covers the mask layer, if the side wall on the top surface of the mask layer is not removed, the initial dielectric layer is planarized, and only the surface of the side wall can be stopped, but the surface of the mask layer cannot be stopped, so that the side wall on the top surface of the mask layer needs to be removed before planarization.
However, due to the difference in the distances between the adjacent dummy gate structures 201, the process of removing the sidewall on the top surface of the mask layer is not easy to control, and the problem of uneven height of the sidewall is likely to occur, for example, a part of the sidewall of the dummy gate structure is not removed at all, so that the subsequent process of removing the dummy gate layer cannot be performed; and removing excessive side walls of part of the pseudo gate structures, wherein the removed side walls are lower than the top surface of the pseudo gate layer, so that the isolation effect of the side walls is lost. Both of these problems affect the performance of the semiconductor structure.
On the basis, the invention provides a method for forming a semiconductor structure, wherein the initial grid structure comprises a first pseudo grid layer, a first mask layer and a second pseudo grid layer; forming a side wall material layer on the side wall and the top surface of the initial pseudo gate structure; forming a dielectric material layer on a substrate; and performing first planarization treatment on the dielectric material layer and the side wall material layer until the top surface of the second pseudo gate layer is exposed, wherein the grinding rate of the first planarization treatment on the second pseudo gate layer is less than that of the dielectric material layer and the side wall material layer. Through the scheme, the first planarization treatment can be guaranteed to stop on the surface of the second pseudo gate layer, a smooth treatment interface is provided, and meanwhile, the uniformity of the height of the initial side wall is effectively improved. And the top surface of the formed initial dielectric layer is higher than that of the first pseudo gate layer, so that the problem of short circuit of the subsequent adjacent gate structures can be effectively avoided, and the performance of the formed semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to fig. 13 are schematic structural views illustrating a forming process of a semiconductor structure according to an embodiment of the invention.
Referring to fig. 5, a substrate is provided.
In this embodiment, the substrate includes: a substrate 300 and a plurality of mutually discrete fins 301 on the substrate 300.
In this embodiment, the method for forming the substrate 300 and the fin portion 301 includes: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate, the patterned layer exposing a portion of the top surface of the initial substrate; and etching the initial substrate by taking the patterning layer as a mask to form the base 300 and the fin part 301.
In this embodiment, the substrate 300 is made of silicon; in other embodiments, the substrate may be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide
In this embodiment, the fin 301 is made of silicon; in other embodiments, the material of the fin portion may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.
Referring to fig. 6, a second isolation layer 302 is formed on the substrate, the second isolation layer 302 covers a portion of the sidewall of the fin 301, and a top surface of the second isolation layer 302 is lower than a top surface of the fin 301.
In this embodiment, the method for forming the second isolation layer 302 includes: forming an initial isolation layer (not shown) on the substrate; and etching to remove part of the initial isolation layer to form the second isolation layer 302, wherein the top surface of the second isolation layer 302 is lower than the top surface of the fin 301.
The second isolation layer 302 is made of an insulating material, and the insulating material includes silicon oxide or silicon oxynitride; in this embodiment, the material of the second isolation layer 302 is silicon oxide.
Referring to fig. 7, after forming the second isolation layer 302, a plurality of mutually separated initial dummy gate structures are formed on the substrate, where the initial gate structures include a first dummy gate layer 303, a first mask layer 304 on the first dummy gate layer 303, and a second dummy gate layer 305 on the first mask layer 304.
In this embodiment, the initial pseudo gate structure further includes: a second mask layer 306 on the second dummy gate layer 305, and a first protection layer 307 on the second mask layer 306.
In this embodiment, the method for forming the initial dummy gate structure includes: forming a first dummy gate material layer on the substrate; forming a first dummy gate material layer on the first dummy gate material layer; forming a second dummy gate material layer on the first mask material layer; forming a second mask material layer on the second dummy gate material layer; forming a patterned first protective layer on part of the second mask material layer; and etching the first dummy gate material layer, the first mask material layer, the second dummy gate material layer and the second mask material layer by using the first protection layer as a mask to form the initial dummy gate structure (not shown).
In this embodiment, the material of the first dummy gate layer 303 is polysilicon; the material of the second dummy gate layer 305 is polysilicon.
In this embodiment, the first mask layer 304 is made of silicon nitride.
In this embodiment, the widths of the plurality of initial dummy gate structures are different, and the distances between adjacent initial dummy gate structures are different.
Referring to fig. 8, a sidewall material layer 308 is formed on the sidewall and the top surface of the initial dummy gate structure.
In this embodiment, the forming process of the sidewall material layer 308 adopts an atomic layer deposition process.
In this embodiment, the material of the sidewall material layer 308 is silicon nitride.
Referring to fig. 9, after the sidewall spacer material layer 308 is formed, a dielectric material layer 309 is formed on the substrate, and the dielectric material layer 309 covers a sidewall of the sidewall spacer material layer 308.
In this embodiment, the method for forming the dielectric material layer 309 includes: forming a dielectric material film (not shown) on the substrate, wherein the dielectric material film covers the side wall material layer; and performing fourth planarization treatment on the dielectric material film until the surface of the side wall material layer 308 is exposed, so as to form the dielectric material layer 309.
In this embodiment, the material of the dielectric material layer 309 is silicon oxide.
Referring to fig. 10, a first planarization process is performed on the dielectric material layer 309 and the sidewall spacer material layer 308 until the top surface of the second pseudo gate layer 305 is exposed, so as to form an initial dielectric layer 310 and an initial sidewall spacer 311, a polishing rate of the first planarization process to the second pseudo gate layer 305 is less than a polishing rate to the dielectric material layer 309 and the sidewall spacer material layer 308, and a polishing rate of the first planarization process to the dielectric material layer 309 and the sidewall spacer material layer 308 is within a preset polishing rate range.
In this embodiment, the predetermined polishing range means that the polishing rates of the dielectric material layer 309 and the sidewall material layer 308 are substantially kept consistent by the first planarization treatment.
In this embodiment, the initial gate structure includes a first dummy gate layer 303, a first mask layer 304 on the first dummy gate layer 303, and a second dummy gate layer 305 on the first mask layer 304. The grinding rate of the first planarization treatment to the second dummy gate layer 305 is less than the grinding rate to the dielectric material layer 309 and the side wall material layer 308, and the grinding rate of the first planarization treatment to the dielectric material layer 309 and the side wall material layer 308 is within a preset grinding rate range, so that the first planarization treatment can be guaranteed to stop on the surface of the second dummy gate layer 305, a relatively flat treatment interface is provided, and meanwhile, the uniformity of the height of the formed initial side wall 311 is effectively improved.
In addition, the top surface of the formed initial dielectric layer 310 is higher than the top surface of the first dummy gate layer 303, so that the top surface of the subsequently formed dielectric layer is also higher than the top surface of the first dummy gate layer 303, even if a gate material layer is remained on the surface of the dielectric layer in the subsequent gate structure forming process, in the subsequent gate structure forming process by flattening the gate material layer, the dielectric layer higher than the first dummy gate layer 303 is removed, and at the moment, the gate material layer on the surface of the dielectric layer is removed together, thereby effectively avoiding the short circuit problem of the adjacent gate structure, and further improving the performance of the finally formed semiconductor structure.
In this embodiment, the first planarization process employs a chemical mechanical polishing process.
Referring to fig. 11, after the first planarization treatment, the second dummy gate layer 305 and the initial sidewall 311 on the sidewall of the second dummy gate layer 305 are removed to form a sidewall 312; performing second planarization treatment on the initial dielectric layer 310 until the top surface of the first mask layer 304 is exposed to form a dielectric layer 313, wherein the polishing rate of the second planarization treatment on the initial dielectric layer 310 is greater than that of the first mask layer 304.
In this embodiment, the initial dielectric layer 310 is subjected to a second planarization process until the top surface of the first mask layer 304 is exposed, and the dielectric layer 313 is formed, so that the top surface of the formed dielectric layer 313 is higher than the top surface of the first dummy gate layer 303, even if a gate material layer remains on the surface of the dielectric layer 313 in a subsequent gate structure forming process, the dielectric layer 313 higher than the first dummy gate layer 303 is removed in the subsequent gate structure forming process by planarizing the gate material layer, and at this time, the gate material layers on the surface of the dielectric layer 313 are removed together, thereby effectively avoiding a short circuit problem of adjacent gate structures, and further improving the performance of the finally formed semiconductor structure.
In this embodiment, the second planarization process employs a chemical mechanical polishing process.
Referring to fig. 12, after the dielectric layer 313 is formed, a patterning layer (not shown) is formed on the dielectric layer 313 and the first mask layer 304, and the patterning layer exposes a portion of the top surface of the first mask layer 304; etching the first mask layer 304 and the first dummy gate layer 303 by using the patterning layer as a mask, and forming an isolation opening (not marked) in the dielectric layer 313; an isolation structure 314 is formed within the isolation opening.
In the manufacturing process of the integrated circuit, a Gate Cut (Gate Cut) process is required to Cut off the strip-shaped Gate, and the Cut Gate corresponds to different transistors, so that the integration level of the transistors can be improved. In addition, when a plurality of gates are arranged in a line along the extending direction, the pitch in the butting direction between the gates that are disconnected after the gates are disconnected can be reduced with high accuracy by the gate disconnection. In this embodiment, the requirement of electrical design is satisfied by performing a cutting process on the initial dummy gate structure.
In this embodiment, the isolation structure 314 includes: the first dummy gate structure comprises a first isolation layer and a second protection layer (not marked) positioned on the first isolation layer, wherein the top surface of the first isolation layer is flush with the top surface of the first dummy gate layer 303, and the top surface of the second protection layer is flush with the top surface of the dielectric layer 313.
Referring to fig. 13, after the isolation structure 314 is formed, the first mask layer 304 and the spacers 312 on the sidewalls of the first mask layer 304 are removed, and a first opening (not labeled) is formed in the dielectric layer 313, where the first opening exposes the top surface of the first dummy gate layer 303; removing the first dummy gate layer 303, and forming a second opening (not labeled) in the dielectric layer 313 at the bottom of the first opening; a gate structure 315 is formed within the second opening.
In this embodiment, the method for forming the gate structure 215 includes: forming a gate material layer (not shown) in the first opening, the second opening and the surface of the dielectric layer 213; and performing third planarization treatment on the gate material layer and the dielectric layer 313 until the top surface of the side wall 312 is exposed, so as to form the gate structure 315.
In this embodiment, in the process of forming the gate structure 315 by performing the third planarization process on the gate material layer, the dielectric layer 313 higher than the first dummy gate layer 303 is removed, and at this time, the gate material layer on the surface of the dielectric layer 313 is also removed together, so that the problem of short circuit between adjacent gate structures 315 is effectively avoided, and the performance of the finally formed semiconductor structure is improved.
In this embodiment, the third planarization process employs a chemical mechanical polishing process.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a plurality of mutually-separated initial pseudo gate structures on the substrate, wherein each initial gate structure comprises a first pseudo gate layer, a first mask layer positioned on the first pseudo gate layer and a second pseudo gate layer positioned on the first mask layer;
forming side wall material layers on the side wall and the top surface of the initial pseudo gate structure;
forming a dielectric material layer on the substrate, wherein the dielectric material layer covers the side wall of the side wall material layer;
and performing first planarization treatment on the medium material layer and the side wall material layer until the top surface of the second pseudo gate layer is exposed to form an initial medium layer and an initial side wall, wherein the grinding rate of the first planarization treatment on the second pseudo gate layer is smaller than the grinding rates of the medium material layer and the side wall material layer, and the grinding rates of the first planarization treatment on the medium material layer and the side wall material layer are within a preset grinding rate range.
2. The method of forming a semiconductor structure of claim 1, further comprising, after said first planarization process: removing the second pseudo gate layer and the initial side wall positioned on the side wall of the second pseudo gate layer to form a side wall; performing second planarization treatment on the initial dielectric layer until the top surface of the first mask layer is exposed to form a dielectric layer, wherein the grinding rate of the second planarization treatment on the initial dielectric layer is greater than that of the first mask layer; after the dielectric layer is formed, the first mask layer and the side wall of the first mask layer are removed, a first opening is formed in the dielectric layer, and the first opening exposes the top surface of the first pseudo gate layer.
3. The method of forming a semiconductor structure according to claim 2, further comprising, after removing the first mask layer: removing the first pseudo gate layer, and forming a second opening in the dielectric layer at the bottom of the first opening; and forming a gate structure in the second opening.
4. The method of forming a semiconductor structure of claim 3, wherein the method of forming a gate structure comprises: forming a grid material layer in the first opening, the second opening and the surface of the dielectric layer; and carrying out third planarization treatment on the grid material layer and the dielectric layer until the top surface of the side wall is exposed to form the grid structure.
5. The method for forming a semiconductor structure according to claim 4, wherein the third planarization process comprises: and (5) carrying out a chemical mechanical polishing process.
6. The method of forming a semiconductor structure of claim 1, wherein the initial dummy gate structure further comprises: the second mask layer is positioned on the second pseudo gate layer, and the first protective layer is positioned on the second mask layer.
7. The method of forming a semiconductor structure of claim 6, wherein the method of forming the initial dummy gate structure comprises: forming a first dummy gate material layer on the substrate; forming a first dummy gate material layer on the first dummy gate material layer; forming a second dummy gate material layer on the first mask material layer; forming a second mask material layer on the second dummy gate material layer; forming a patterned first protective layer on part of the second mask material layer; and etching the first pseudo gate material layer, the first mask material layer, the second pseudo gate material layer and the second mask material layer by taking the first protection layer as a mask to form the initial pseudo gate structure.
8. The method for forming the semiconductor structure according to claim 1, wherein the forming process of the side wall material layer comprises: and (5) an atomic layer deposition process.
9. The method of forming a semiconductor structure of claim 1, wherein the material of the dielectric material layer comprises: silicon oxide.
10. The method of claim 1, wherein the material of the sidewall spacer material layer comprises: silicon nitride.
11. The method of forming a semiconductor structure of claim 1, wherein the material of the first dummy gate layer comprises: polycrystalline silicon; the material of the second dummy gate layer comprises: polycrystalline silicon.
12. The method of forming a semiconductor structure according to claim 1, wherein the material of the first mask layer comprises: silicon nitride.
13. The method of forming a semiconductor structure according to claim 1, wherein the first planarization process comprises: and (5) carrying out a chemical mechanical polishing process.
14. The method of forming a semiconductor structure according to claim 2, wherein the second planarization process comprises: and (5) carrying out a chemical mechanical polishing process.
15. The method of forming a semiconductor structure of claim 2, wherein after forming the dielectric layer and before removing the first mask layer, further comprising: forming a patterning layer on the dielectric layer and the first mask layer, wherein the patterning layer exposes a part of the top surface of the first mask layer; etching the first mask layer and the first pseudo gate layer by taking the patterning layer as a mask, and forming an isolation opening in the dielectric layer; an isolation structure is formed within the isolation opening.
16. The method of forming a semiconductor structure of claim 15, wherein the isolation structure comprises: the top surface of the first isolation layer is flush with the top surface of the first pseudo gate layer, and the top surface of the second protection layer is flush with the top surface of the dielectric layer.
17. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises: the initial pseudo-gate structure crosses the fin portion, and the initial pseudo-gate structure covers part of the side wall and the top surface of the fin portion.
18. The method of forming a semiconductor structure of claim 17, further comprising, prior to forming the initial dummy gate structure: and forming a second isolation layer on the substrate, wherein the second isolation layer covers part of the side wall of the fin part, and the top surface of the second isolation layer is lower than that of the fin part.
19. The method of forming a semiconductor structure of claim 1, wherein the method of forming the dielectric material layer comprises: forming a medium material film on the substrate, wherein the medium material film covers the side wall material layer; and performing fourth planarization treatment on the dielectric material film until the surface of the side wall material layer is exposed to form the dielectric material layer.
20. The method for forming a semiconductor structure according to claim 1, wherein widths of the plurality of initial dummy gate structures are different, and a pitch between adjacent initial dummy gate structures is different.
CN202110106482.9A 2021-01-26 2021-01-26 Method for forming semiconductor structure Pending CN114792628A (en)

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