CN117077612A

CN117077612A - Layout optimization method of 3D chip

Info

Publication number: CN117077612A
Application number: CN202311330945.5A
Authority: CN
Inventors: 王嘉诚; 张少仲
Original assignee: Zhongcheng Hualong Computer Technology Co Ltd
Current assignee: Zhongcheng Hualong Computer Technology Co Ltd
Priority date: 2023-10-16
Filing date: 2023-10-16
Publication date: 2023-11-17
Anticipated expiration: 2043-10-16
Also published as: CN117077612B

Abstract

The invention discloses a layout optimization method of a 3D chip, which belongs to the technical field of integrated circuits and comprises the following steps: establishing a space model in a 3D chip to be tested; testing the 3D chip under the condition of highest workload; monitoring the temperature of the space inside the 3D chip, and performing filtering, segmentation and morphological operation on the acquired temperature data in the 3D space; identifying hot spots in the space in the 3D chip and determining attribute information of the hot spots; determining whether layout optimization of the 3D chip is needed according to attribute information of all hot spots in the space in the 3D chip, if so, continuously executing signal transmission demand quantity of each device in the 3D chip to build a fluid model in the 3D chip; the layout of the internal devices is optimized based on the temperature distribution of the fluid model inside the 3D chip at time t 0. The invention effectively optimizes the layout of the 3D chip to improve the thermal management effect of the chip.

Description

Layout optimization method of 3D chip

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a layout optimization method of a 3D chip.

Background

With the development of chip technology, three-dimensional (3D) Integrated Circuits (ICs) have become an important technology trend, which can provide higher integration, shorter signal transmission distances, and higher performance. However, as integration increases, thermal management issues inside the chip become more prominent. Excessive temperatures not only degrade the performance of the chip, but may also cause failure or even damage to the chip. Therefore, how to effectively perform layout optimization of a 3D chip to improve the heat distribution inside thereof is an important issue in current chip designs.

Conventional chip layout optimization methods mainly include experience-based methods and simulation-based methods. The experience-based method is to arrange devices with higher temperature at the edge of the chip as much as possible according to the experience of the designer so as to facilitate heat dissipation. However, the effectiveness of this approach is often limited by the experience of the designer and cannot accommodate the ever changing chip design requirements. The simulation-based method is to predict the temperature distribution in the chip by simulating the working process of the chip, and then perform layout optimization according to the prediction result. However, this approach requires a significant amount of computational resources and the accuracy of the simulation results is often limited by the complexity of the model.

Therefore, a new layout optimization method of a 3D chip is urgently needed, which can effectively improve the heat distribution inside the chip, and at the same time, needs to make the calculation optimization process flexible and efficient.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides a layout optimization method of a 3D chip, which comprises the following steps:

step 1, establishing a space model in the internal space of a 3D chip to be tested;

step 2, testing the 3D chip under the condition of highest work load, wherein the test duration is t0;

step 3, monitoring the temperature of the internal space of the 3D chip, and performing filtering, segmentation and morphological operation on the acquired temperature data of the internal space of the 3D chip;

step 4, identifying a hot spot of the internal space of the 3D chip and determining attribute information of the hot spot, wherein the attribute information comprises the temperature, the position and the volume of the hot spot;

step 5, determining whether the layout optimization of the 3D chip is needed according to the attribute information of all hot spots in the internal space of the 3D chip, if so, continuing to execute the step 6;

step 6, establishing a fluid model for the internal space of the 3D chip based on the signal transmission demand of each device in the 3D chip;

and 7, optimizing the layout of the internal devices of the 3D chip based on the temperature distribution at the time t0 according to the fluid model of the internal space of the 3D chip.

Wherein, the conditions of the 3D chip under the highest workload include:

determining the device which reaches the maximum frequency first in all devices in the 3D chip;

when it is monitored that a certain device in the 3D chip has reached the limit of the highest operating frequency, the 3D chip is in a condition of highest operating load;

the 3D chip is kept in this state t0 for a period of time from the moment the highest workload condition is triggered.

The method for monitoring the temperature of the internal space of the 3D chip, and filtering, dividing and morphological operations on the acquired temperature data of the internal space of the 3D chip comprises the following steps:

the method comprises the steps of using an embedded temperature sensor to monitor the temperature, installing the embedded temperature sensor at a key position, and interpolating and smoothing the rest of the space to form temperature space data in a complete 3D chip space;

filtering the temperature space data to remove high frequency noise;

the temperature space is divided into different areas, and the area division is carried out according to the threshold value of the temperature;

morphological operations are performed to process the segmented regions, including removing the too small regions, filling voids, and smoothing boundaries.

And (3) identifying possible hot spots according to the temperature, the area and other attributes of each area determined in the step (3), wherein the area corresponding to the temperature interval larger than the preset temperature is determined as the hot spot area.

Determining whether layout optimization of the 3D chip is needed according to attribute information of all hot spots in the internal space of the 3D chip, including:

setting a temperature integration threshold I_threshold in a hot spot area and a highest temperature threshold T_threshold of the hot spot;

for each hot spot region, first calculating its volume V, then integrating the temperature within this volume as I;

dividing the hot spot area into N small volume elements, wherein the volume of each volume element is dV, the temperature is T, and the hot spot area comprises:

wherein i=1, 2, N;

if T > T_threshold exists in a certain hot spot area or I > I_threshold exists in the hot spot area, the layout of the chip is determined to be required to be optimized.

Wherein, establish the fluid model to the inner space of 3D chip based on the signal transmission demand of each device in the 3D chip, include:

the fluid model models the flow source in the heat conduction equation by adding a heat source term Q that represents a function of the heat generated at each location and point in time.

The method for determining the heat source item Q comprises the following steps:

provided that there are n heat sources, their positions are respectivelyThe heat estimates generated are respectivelyK is any position within the 3D chip, t is time, < >>Is the position vector of the heat source i;

is the position of the heat source iEstimated value of heat generated by k, will +.>The definition is as follows:

，

wherein,

integration ofFrom t=0 to the current time t;

is the heat source i in its position->A peak heat estimate per unit time generated;

is a coefficient related to the manufacturing material of the 3D chip;

is the width of the Gaussian distribution, k is the position vector,/->Is the position vector of heat source i, +.>Represents k andsquaring the Euclidean distance between the two;

the heat of all the heat source estimated values is added to obtain a heat source item Q (k, t) of the internal space of the 3D chip, wherein the heat source item Q (k, t) is as follows:wherein i=1, 2,..n,/,>represents the summation, n is the total number of heat sources.

Wherein Q (k, t) is substituted into a three-dimensional heat conduction equation representing that a plurality of heat sources generate heat quantity estimated values at different positions, resulting in:

，

wherein the estimated heat value is distributed as Q (k, T) in three-dimensional space, T is temperature, T is time,is a gradient operator which is used to determine the gradient,is density, c is specific heat capacity, u is heat conductivity,/>Indicating the divergence of the heat flow.

Wherein optimizing the layout of devices inside the 3D chip based on the temperature distribution of the fluid model inside the 3D chip at the time T0 comprises evaluating all the device layouts inside the 3D chip by using an optimization algorithm, wherein an objective function of the optimization algorithm comprises minimizing an average temperature t_avg (T0) of the temperature distribution T (x, y, z, T) of the 3D chip at the time T0, and adding a constraint condition that the highest temperature of each device point in T (x, y, z, T0) cannot exceed a maximum temperature t_max (T0) based on the negative influence of the wiring delay amount l_i on the optimization target.

Determining wiring delay L_i of each device under the initial layout and determining the position P_i of each device;

based on the initial layout of the 3D chip to be tested and at time T0, determining a temperature distribution T (x, y, z, T0) under the initial layout, and then calculating t_avg (T0) and a temperature t_i (T0) of each device;

taking T_avg (T0), L_i and T_i (T0) as inputs, solving the optimization problem with constraint by using a Lagrangian multiplier method and a gradient descent method to obtain a new layout P_i;

and updating the layout of all devices in the 3D chip according to the new P_i.

According to the invention, the heat distribution in the chip can be improved by optimizing the layout of the chip, and the risk of overheating is reduced, so that the working efficiency of the chip is improved. And by optimizing the layout of the chip, the heat distribution in the chip can be effectively managed, and the risk of overheating is reduced. In addition, the layout optimization method based on temperature monitoring and the fluid model, which is disclosed by the invention, is more flexible and efficient than the traditional method based on experience or simulation by using the fluid model to estimate and simulate heat.

Drawings

The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

fig. 1 is a flowchart illustrating a layout optimization method of a 3D chip according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two.

It should be understood that although the terms first, second, third, etc. may be used to describe … … in embodiments of the present invention, these … … should not be limited to these terms. These terms are only used to distinguish … …. For example, the first … … may also be referred to as the second … …, and similarly the second … … may also be referred to as the first … …, without departing from the scope of embodiments of the present invention.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such product or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a commodity or device comprising such element.

In the fields of high-performance computing, big data processing, AI and the like, 3D chips are widely used due to high integration and high performance. However, as the integration level of chips is higher and higher, the problem of thermal management inside the chips becomes more and more serious. Poor thermal management can affect the operating efficiency of the chip, and can also cause the chip to overheat or even damage.

Therefore, the layout optimization method of the 3D chip is provided to improve the heat distribution inside the 3D chip, the space model of the 3D chip is built, the internal temperature of the 3D chip under the highest working load condition is monitored, hot spots are identified, attribute information of the hot spots is determined, and then whether the layout optimization is needed is judged according to the information. And establishing a fluid model based on the signal transmission demand of each device in the chip, and optimizing the device layout in the chip according to the temperature distribution of the model.

As shown in fig. 1, a layout optimization method of a 3D chip includes the following steps:

In an embodiment, in the step 1, a space model is built inside the 3D chip to be tested, including

Defining the physical size and structure of a chip, including the overall size of the 3D chip, including the length, the width and the height, identifying all devices in the chip, determining the coordinate position of each device in the 3D chip, and determining the position coordinates of the center point of each device in the space model of the invention because the volume of each device relative to the 3D chip is small.

A three-dimensional grid is generated, and when the area within the grid contains chip devices, the grid points are considered to contain devices.

In one embodiment, for a condition that the 3D chip is at the highest workload, the condition is that a device that reaches the maximum frequency first in all devices in the 3D chip is determined, when a certain device in the 3D chip is monitored to have reached the limit of the highest operating frequency, the 3D chip is considered to be in the condition of the highest workload, and the 3D chip is kept in the state t0 for a period from the moment when the condition of the highest workload is triggered.

In one embodiment, the temperature of the space inside the 3D chip is monitored, and filtering, segmentation and morphological operations are performed on the acquired temperature data inside the 3D space.

The method comprises the steps of using an embedded temperature sensor to monitor the temperature, installing the embedded temperature sensor at a key position, and interpolating and smoothing the rest of the space to form temperature space data in a complete 3D chip space.

And filtering the temperature space data, wherein the filtering operation aims at removing noise, removing high-frequency noise and retaining the main characteristics of the data.

The temperature space is divided into different regions by dividing the temperature data according to a threshold value of the temperature, for example, the region of the different temperature sections may be divided into separate regions. Morphological operations are then performed to process the segmented regions, including removing too small regions, filling voids, smoothing boundaries.

In an embodiment, identifying a hot spot of a 3D on-chip space and determining attribute information of the hot spot, the attribute information including a temperature, a location, and a volume of the hot spot, includes:

and (3) identifying possible hot spots according to the temperature, the area and other attributes of each region determined in the step (3), wherein the region corresponding to the temperature interval larger than the preset temperature is determined as a hot spot region.

For each identified hot spot, attribute information such as its temperature, location, and volume needs to be acquired.

In one embodiment, for step 5, determining that layout optimization of the 3D chip is required according to the hot spot of the 3D chip space and determining attribute information of the hot spot includes:

a temperature integration threshold i_threshold within the hot spot area is set and a maximum temperature threshold t_threshold of the hot spot is set. These two thresholds may be set based on factors such as the operating environment of the chip, the effect of the heat sink, the operating stability of the device, etc.

For each hot spot region, its volume V is first calculated, and then within this volume the temperature is integrated, denoted I. Specifically, the hot spot area is divided into N small volume elements, the volume of each volume element is dV, and the temperature is T, and then there are:

，

if there is T > T_threshold within a certain hotspot or if there is I > I_threshold for a certain hotspot region, it is determined that optimization of the layout of the chip is required.

In one embodiment, the fluid model assumes that the flow source generates heat and that the data flow will bring about a flow of heat, similar to the flow of heat brought about by a high temperature fluid flow, simulating an increase in pressure (temperature) of the flow source due to data processing. Meanwhile, the set thermal interference increases with the increase of data flow and the decrease of component spacing, and the distance between analog flow sources (components) affects the heat propagation.

The flow source is modeled in the heat conduction equation by adding a heat source term Q that represents a function of the heat generated at each location and point in time. If the flow source only generates heat at location k0, then Q may be a function of a high value at k0 and a low value at other locations.

And a plurality of different heat sources are arranged in the 3D chip, and the heat quantity generated by each heat source at the position is different, but the material structure in the 3D chip is close, so that the heat diffusion effect of the different heat sources is the same. Provided that there are n heat sources, their positions are respectivelyThe heat produced is estimated to be +.>K is any position within the 3D chip, t is time, < >>Is the position vector of the heat source i.

Is an estimate of the heat generated by heat source i at position k, will +.>The definition is as follows:

，

wherein,

the integral is from t=0 to the current time t to represent the heat accumulation effect from the time beginning to the time t.

Is the heat source i in its position->The generated peak heat estimate value per unit time is specifically a heat estimate value per unit time generated by a heat source (device) i of the 3D chip under the full working load, and is used for optimizing the layout use of the 3D chip device.

Is a coefficient which determines the rate of heat diffusion, is related to the manufacturing materials of the 3D chip, and determines the coefficient +_ according to different manufacturing materials>For the same 3D chip, different heat sources (devices) can be added>The settings were the same.

Is the width of the Gaussian distribution, k is the position vector,/->Is the position vector of heat source i, +.>Represents k and->The square of the Euclidean distance between them, i.e.>Subscripts 1-3 correspond to three different dimensions of the three-dimensional space.

Then, the heat of all the heat source estimated values is added to obtain a heat source item Q (k, t) of the internal space of the 3D chip, wherein the heat source item Q (k, t) is as follows:

，

wherein the method comprises the steps of，i=1,2,...,n，Represents the summation, n is the total number of heat sources.

Finally, substituting Q (k, t) into a three-dimensional heat conduction equation to obtain:

，

the above three-dimensional heat conduction equation represents that a plurality of heat sources generate heat estimation values at different positions, the heat estimation values are distributed as Q (k, T) in three-dimensional space, T is temperature, T is time,is a gradient operator, < >>Is density, c is specific heat capacity, and u is thermal conductivity. />Indicating the divergence of the heat flow, i.e. the propagation of heat in space. Left side of the above three-dimensional heat conduction equation +.>The rate of change of heat per unit volume over time is shown, with the two items on the right showing heat conduction and generation, respectively. />Is a heat conduction term that indicates the distribution of heat inside an object by conduction. Where u is the thermal conductivity, which describes the thermal conductivity of the substance. />Is a temperature gradient that describes the change in temperature in space. />The heat flow, i.e. the flow of heat. />Then the divergence of the heat flow, i.e. the conduction of heat, Q (k, t) is the heat source term, and the two terms are added to give the rate of change of heat per unit volume over time. Wherein the heat transfer term describes the propagation of heat inside the object, the heat source term describes the generation of new heat, and the summation represents the total cause of the heat change inside the object.

And obtaining temperature distribution T (x, y, z, T) at different positions and at different times in the 3D chip by solving a three-dimensional heat conduction equation, and using the temperature distribution T to simulate and predict the heat distribution in the 3D chip.

In one embodiment, solving the partial differential equation PDE of the three-dimensional heat transfer equation based on finite difference method FDM, for a discrete three-dimensional spatial grid, one temperature value for each grid point, discretizing the heat transfer equation, and solving at each grid point, includes dividing the model space into a set of discrete grid points. At each grid point, the differential is replaced with a differential, converting the heat conduction equation into an algebraic equation. Solving the set of algebraic equations to obtain the temperature value at each grid point. And (3) repeating the steps along with the advancement of time to obtain the temperature distribution of each time step, namely obtaining the temperature distribution of the 3D chip at different positions and at different times.

Alternatively, the FDM solution of the PDE problem is performed by ANSYS simulation software.

In one embodiment, the determination is based on signal transmission requirements of devices within the 3D chip. Said->Is the heat source i in its position->A generated peak heat per unit time estimate comprising:

signal transmission requirement of deviceAnd device operating frequency->The relationship between them being by an exponential function, i.eFitting was performed to determine +.>And->Numerical value of>The sensitivity of the ith device to the change of signal transmission demand with frequency is embodied.

Power consumption of a deviceAnd frequency->And voltage->The relation of (2) is: />Wherein->Is a constant related to the physical characteristic capacitance of the ith device.

Thus, the estimated value of the heat generated by the ith device under the maximum load of the chip is setThe method comprises the following steps:

，

wherein,is the operating voltage of the ith device, +.>Is the operating frequency of the ith device, +.>、/>And->Is a constant for the ith device.

In one embodiment, according to the device with the highest frequency among all devices in the 3D chip, when the test detects that one device reaches its highest frequency, the frequency of other devices i is limited to the frequency of the current device i in the state of the 3D chipSaid->For the frequency of the device i of the 3D chip at maximum workload.

In one embodiment, assuming that the communication requirement between the device i and the other device j is c_ij, the signal transmission requirement s_i of the device i is calculated by the following formula:this formula is the sum of the communication requirements c_ij of all devices j directly connected to device i. Let us assume that the bi-directional communication demand is equally directional and that the value of C ij is determined based on the computational demand of the 3D chip in an application computing scenario.

In one embodiment, to determine the frequency of device i for a 3D chip in a full load stateBy monitoring the state of the 3D chip, when the 3D chip is used for special purposesDuring data processing in a fixed scene, a certain device in the chip reaches the maximum working frequency, at the moment, the 3D chip can be considered to reach a full-load working state, and the working frequency of the device i in the 3D chip at the moment is monitored and obtained>。

In one embodiment, in evaluating all device layouts within a 3D chip using an optimization algorithm, it is necessary to determine an objective function that includes minimizing an average temperature t_avg (T0) of a temperature distribution T (x, y, z, T) of the 3D chip at time T0 and negatively affecting an optimization objective based on a wire delay amount l_i. While adding the constraint that the maximum temperature of each device point within T (x, y, z, T0) cannot exceed the maximum temperature t_max (T0).

The objective function may be defined as the following optimization problem:

，

subjectto:T_i(t0)<=T_max(t0)foralli，

where F is our objective function, minimizing the sum of the average temperature T_avg (T0) at time T0 and the amount of wiring delay L_i.

Is a weight coefficient for balancing the effects of temperature and wire delay.

T_i (T0) is the temperature of each device i at time T0.

T_max (T0) is the maximum temperature allowed, and all t_i (T0) cannot exceed this value.

In one embodiment, assuming that the communication requirement between the device i and the other device j is c_ij, the wire length is d_ij, and the transmission speed of the signal on the wire is v, the wire delay l_i of the device i can be calculated by the following formula:

，

wherein,representing the summation of all devices j directly connected to device i. />Is the wiring delay per connection, which is equal to the communication demand c_ij times the wiring length d_ij, and then divided by the signal transmission speed v.

In one embodiment, solving the optimization problem using the Lagrangian multiplier method includes:

converting constrained optimization problem to unconstrained optimization problem by introducing Lagrangian multiplierAnd a lagrangian function L. For each constraint T_i (T0)<=t_max (T0), introducing a lagrangian multiplier +.>The Lagrangian function is then defined as follows:

，

the Lagrangian function L is the objective function F plus all constraints multiplied by the corresponding Lagrangian multiplier. At this time, t_max (T0) -t_i (T0) is converted into t_max (T0) -t_i (T0) in the lagrangian function because the constraint condition is equal to or less.

Solving the above-described unconstrained optimization problem includes setting the derivative of the lagrangian function L equal to 0. Specifically, the method comprises the steps of respectively aligning T_i (T0), L_i,Partial derivatives are calculated and then set equal to 0 to obtain a set of equations. The solution corresponding to the set of equations is the solution of the original constraint optimization problem.

Meanwhile, according to the KKT condition, the Lagrangian multiplierMust be greater than or equal to 0, and. Indicating if T_i (T0)<T_max (T0), then the corresponding +.>Must be equal to 0; if T_i (T0) =T_max (T0), then +.>And may be any non-negative number.

Since the optimization problem is nonlinear, the above equation is solved by using a gradient descent method or the like, including gradually optimizing the quality of the solution by iteration.

In one embodiment, an initial layout is determined, which may be an existing device layout for testing a 3D chip or a random layout within the 3D chip space, calculating a wiring delay amount l_i for each device and determining a device position p_i.

with t_avg (T0), l_i, and t_i (T0) as inputs, the solution is performed by using the lagrangian multiplier method and the gradient descent method. Solving the above-mentioned constrained optimization problem, a new lambda_i and a new layout P_i are obtained. And updating the layout of all devices in the 3D chip according to the new P_i.

If the difference between the new layout and the old layout T_avg (T0) is smaller than a certain preset threshold value or enough iteration steps are carried out, stopping iteration and outputting the current layout; otherwise, returning to the process after the temperature distribution is solved, and continuing iteration.

It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.

The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.

Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units involved in the embodiments of the present disclosure may be implemented by means of software, or may be implemented by means of hardware. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.

The foregoing description of the preferred embodiments of the present invention has been presented for purposes of clarity and understanding, and is not intended to limit the invention to the particular embodiments disclosed, but is intended to cover all modifications, alternatives, and improvements within the spirit and scope of the invention as outlined by the appended claims.

Claims

1. A layout optimization method of a 3D chip comprises the following steps:

2. The layout optimization method of 3D chips of claim 1, wherein the 3D chip at highest workload conditions comprises:

3. The layout optimization method of a 3D chip according to claim 1, wherein monitoring the temperature of the internal space of the 3D chip and filtering, dividing and morphological operations on the obtained temperature data of the internal space of the 3D chip, comprises:

filtering the temperature space data to remove high frequency noise;

4. The method for optimizing the layout of a 3D chip according to claim 1, wherein identifying possible hot spots for the temperature, the area, and other attributes of each region determined in step 3 includes determining a region corresponding to a temperature interval greater than a preset temperature as a hot spot region.

5. The layout optimization method of a 3D chip according to claim 1, wherein determining whether layout optimization of the 3D chip is required according to attribute information of all hot spots of an internal space of the 3D chip comprises:

wherein i=1, 2, N;

6. The layout optimization method of a 3D chip according to claim 1, wherein establishing a fluid model for an internal space of the 3D chip based on signal transmission requirements of devices in the 3D chip comprises:

7. The layout optimization method of 3D chips as defined in claim 6, wherein said method for determining heat source term Q comprises:

is the estimated heat value generated by heat source i at position k, will +.>The definition is as follows:

，

wherein,

integration ofFrom t=0 to the current time t;

is a coefficient related to the manufacturing material of the 3D chip;

is the width of the Gaussian distribution, k is the position vector,/->Is the position vector of heat source i, +.>Represents k and->Squaring the Euclidean distance between the two;

8. The layout optimization method of 3D chips of claim 6 wherein,

substituting Q (k, t) into a three-dimensional heat conduction equation representing that a plurality of heat sources produce heat estimates at different locations, resulting in:

，

wherein the estimated heat value is distributed as Q (k, T) in three-dimensional space, T is temperature, T is time,is a gradient operator, < >>Is density, c is specific heat capacity, u is heat conductivity,/>Indicating the divergence of the heat flow.

9. A method of optimizing the layout of a 3D chip according to claim 1, wherein optimizing the layout of devices within the 3D chip based on the temperature distribution of a fluid model within the 3D chip at time T0 comprises evaluating all device layouts within the 3D chip using an optimization algorithm whose objective function includes minimizing the average temperature t_avg (T0) of the temperature distribution T (x, y, z, T) of the 3D chip at time T0 and based on the negative effect of the wiring delay amount l_i on the optimization objective while adding a constraint that the maximum temperature of each device point within T (x, y, z, T0) cannot exceed the maximum temperature t_max (T0).

10. The layout optimization method of 3D chips of claim 9, wherein,

determining a wiring delay amount L_i of each device under the initial layout and determining a position P_i of each device;

and updating the layout of all devices in the 3D chip according to the new P_i.