CN117075836A - Anti-interference device for display signal, display and electronic equipment - Google Patents
Anti-interference device for display signal, display and electronic equipment Download PDFInfo
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Abstract
The application provides an anti-interference device for display signals, a display and electronic equipment, and relates to the technical field of display processing, wherein the anti-interference device is connected with an embedded display interface (EDP); the tamper resistant device is configured to: when the EDP signal is detected to have an interference signal, a low-level voltage is input to a hot plug detection HPD signal in the EDP signal, and when the EDP signal is detected to disappear, a zero voltage is input to the HPD signal, so that the HPD signal is changed from a low level to a high level, and a virtual hot plug action is generated. The anti-interference device has the advantages of no influence on EDP signals and good anti-interference effect on interference signals.
Description
Technical Field
The present application relates to the field of display processing technologies, and in particular, to an anti-interference device for displaying signals, a display, and an electronic device.
Background
In the current notebook computer, embedded Display PORT (EDP) signals are generally used for communication between a CPU of a motherboard and a timing controller (Timing controller, tcon) chip of a Display screen, so that the motherboard and the Display screen are connected by using an EDP screen line. Because the signal wiring is longer, the protection is very easy to be interfered when insufficient, and particularly when some anti-interference tests are performed, EDP signals are easy to be interfered, so that the phenomena of screen display, blocking and the like are caused.
Typical of the current interference test items is CPI (Cell Phone Interfere handset interference) test, which is also the test item that most often fails in display devices. The interference signal generated by the interference signal generator is modulated, amplified and coupled to a customized antenna, and interference is applied to the tested equipment (Equipment Under Test, EUT) through the antenna.
At present, the following two ways are generally adopted to realize interference resistance:
the first way is: adding small capacitance on the EDP screen line or common mode inductance filtering on the differential signal line; however, the capacitor or the inductor is harmful to the signal and is not suitable for the scene of high signal transmission rate;
the second way is: the EDP screen package conductive cloth or the differential wire uses a shielding coaxial cable; however, because thicker conductive cloths cannot be used and the lap joint between the rings is short, the shielding effect is not ideal, and the price of using shielded coaxial cables is too high.
Disclosure of Invention
In view of the above, the application provides an anti-interference device for displaying signals, a display and an electronic device, so as to solve the technical problems of signal damage, unsatisfactory shielding effect and high price in the existing anti-interference display technical scheme.
In one possible implementation, the anti-interference device is connected with an embedded display interface EDP; the tamper resistant device is configured to: when the EDP signal is detected to have an interference signal, a low-level voltage is input to a hot plug detection HPD signal in the EDP signal, and when the EDP signal is detected to disappear, a zero voltage is input to the HPD signal, so that the HPD signal is changed from a low level to a high level, and a virtual hot plug action is generated.
In one possible implementation, the embedded display interface EDP includes N pairs of differential signal terminals and one HPD pin;
the anti-interference device comprises N first anti-interference circuits; the first anti-interference circuit includes: a differential amplifying circuit and a first voltage comparator; wherein, a differential amplifying circuit is connected with a pair of differential signal terminals; the differential amplifying circuit outputs a voltage difference of the differential signal to the first voltage comparator; the first voltage comparator is connected with the HPD pin and inputs low-level voltage or zero voltage to the HPD pin.
In one possible implementation, the differential amplifying circuit includes an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor; the first resistor, the second resistor, the third resistor and the fourth resistor have the same resistance value; one end of the first resistor is connected with a first signal end of the differential signal end, and the other end of the first resistor is connected with a non-inverting input end of the operational amplifier; one end of the third resistor is connected between the first resistor and the non-inverting input end of the operational amplifier, and the other end of the third resistor is connected with the output end of the operational amplifier; one end of the second resistor is connected with a second signal end of the differential signal end, and the other end of the second resistor is connected with an inverted input end of the operational amplifier; one end of the fourth resistor is connected between the second resistor and the reverse input end of the operational amplifier, and the other end of the fourth resistor is grounded; the output end of the operational amplifier is connected with the non-inverting input end of the first voltage comparator.
In one possible implementation, the input voltage of the non-inverting input terminal of the first voltage comparator is a voltage difference of a differential signal; the input voltage of the reverse input end of the first voltage comparator is the maximum voltage which can be born by the EDP signal; when the input voltage of the non-inverting input end of the first voltage comparator is greater than or equal to the input voltage of the inverting input end, the output end of the first voltage comparator outputs the low-level voltage of the HPD signal to the HPD pin, otherwise, the output end of the first voltage comparator outputs zero voltage to the HPD pin.
In one possible implementation, the embedded display interface EDP further comprises a single-ended signal terminal;
the anti-interference device also comprises a second anti-interference circuit; the second anti-interference circuit comprises a second voltage comparator; the input voltage of the non-inverting input end of the second voltage comparator is the voltage of a single-ended signal end; the input voltage of the reverse input end of the voltage comparator is the maximum voltage of the EDP signal; when the input voltage of the non-inverting input end of the voltage comparator is larger than or equal to the input voltage of the inverting input end, the output end of the first voltage comparator outputs the low-level voltage of the HPD signal to the HPD pin, otherwise, the output end of the first voltage comparator outputs zero voltage to the hot HPD pin.
In one possible implementation, the interfering signal is a periodic signal.
In a second aspect, an embodiment of the present application provides a display, including: the anti-interference device comprises a time sequence controller Tcon chip and a display signal of the embodiment of the application; the time sequence controller Tcon chip comprises an embedded display interface EDP; the embedded display interface EDP is connected with the anti-interference device.
In a third aspect, an embodiment of the present application provides an electronic device, including a motherboard and a display of the embodiment of the present application; the main board is connected with an embedded display interface (EDP) of the display through an EDP signal line; the EDP signal line comprises a Main channel Main-Link and a hot plug detection HPD signal line; the Main channel Main-Link includes N differential signal line pairs.
In one possible implementation, the differential amplifying circuit of each first anti-interference circuit inputs a voltage difference of the differential signal to the non-inverting input terminal of the first voltage comparator; when the input voltage of the non-inverting input end of the first voltage comparator of any one of the first anti-interference circuits is larger than or equal to the input voltage of the inverting input end, the output end of the first voltage comparator outputs the low-level voltage of an HPD signal to the HPD pin, and when the input voltage of the non-inverting input end of the first voltage comparator is smaller than the input voltage of the inverting input end, zero voltage is input to the HPD pin; when the HPD signal is changed from low level to high level, the Main board is triggered to send display data to the Tcon chip again through the Main channel Main-Link.
In one possible implementation, when the input voltage of the non-inverting input terminal of the second voltage comparator of any one of the second anti-interference circuits is greater than or equal to the input voltage of the inverting input terminal, the output terminal of the second voltage comparator outputs the low-level voltage of the HPD signal to the HPD pin, and when the input voltage of the non-inverting input terminal of the second voltage comparator is less than the input voltage of the inverting input terminal, the zero voltage is input to the HPD pin; when the HPD signal is changed from low level to high level, the Main chip is triggered to send display data to the Tcon chip again through the Main channel Main-Link.
The anti-interference device has the advantages of no influence on EDP signals and good anti-interference effect on interference signals.
Drawings
FIG. 1 is a schematic diagram of an EDP interface connector according to an embodiment of the present application;
FIG. 2 is a schematic diagram of three states of an HDP signal according to an embodiment of the present application;
FIG. 3 is a schematic diagram showing a design route of signal anti-interference according to an embodiment of the present application;
FIG. 4 is a block diagram of an anti-interference device for displaying signals according to an embodiment of the present application;
FIG. 5 is a block diagram of a first anti-interference circuit according to an embodiment of the present application;
FIG. 6 is a block diagram of a second anti-tamper circuit according to an embodiment of the present application;
FIG. 7 is a block diagram of a display according to an embodiment of the present application;
fig. 8 is a block diagram of an electronic device according to an embodiment of the present application.
The attached drawings are identified:
r1: a first resistor; r2: a second resistor; r3: a third resistor; r4: a fourth resistor;
a: an operational amplifier; b: a first voltage comparator; c: and a second voltage comparator.
Detailed Description
Various aspects and features of the present application are described herein with reference to the accompanying drawings.
It should be understood that various modifications may be made to the embodiments of the application herein. Therefore, the above description should not be taken as limiting, but merely as exemplification of the embodiments. Other modifications within the scope and spirit of the application will occur to persons of ordinary skill in the art.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and, together with a general description of the application given above, and the detailed description of the embodiments given below, serve to explain the principles of the application.
These and other characteristics of the application will become apparent from the following description of a preferred form of embodiment, given as a non-limiting example, with reference to the accompanying drawings.
It is also to be understood that, although the application has been described with reference to some specific examples, those skilled in the art can certainly realize many other equivalent forms of the application.
The above and other aspects, features and advantages of the present application will become more apparent in light of the following detailed description when taken in conjunction with the accompanying drawings.
Specific embodiments of the present application will be described hereinafter with reference to the accompanying drawings; however, it is to be understood that the disclosed embodiments are merely exemplary of the application, which can be embodied in various forms. Well-known and/or repeated functions and constructions are not described in detail to avoid obscuring the application in unnecessary or unnecessary detail. Therefore, specific structural and functional details disclosed herein are not intended to be limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present application in virtually any appropriately detailed structure.
The specification may use the word "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," which may each refer to one or more of the same or different embodiments in accordance with the application.
First, the design idea of the embodiment of the present application will be briefly described.
In the current notebook computer, the main board CPU and the Tcon chip of the display screen are usually communicated by adopting EDP signals, so that the main board and the display screen are connected by using an EDP screen wire. EDP is a full digital interface based on the DisplayPort architecture and protocol, which can use simpler connectors and fewer pins to transmit high-resolution signals, as shown in FIG. 1, and the data transmission rate is far higher than LVDS (Low-Voltage Differential Signaling Low-voltage differential Signal), which is the important reason why the EDP interface replaces the LVDS interface. The EDP interface signal mainly comprises three parts of Main-Link, AUX CH and HPD. Main Link represents a Main channel for transmitting various types of video data and audio data; AUX CH represents an auxiliary channel for transmitting low bandwidth required data, as well as link management and device control signals; HPD represents a hot plug detect channel.
The Main-Link is composed of 1-4 pairs of data lines, and each pair of data lines is a pair of differential lines. For a liquid crystal display, the number of Main-Link data lines depends on the resolution and color number of the display. The signals transmitted in the channel include video pixel signals, video timing signals, video format signals, bit/pixel and color space signals and error correction signals of the video signals, and an ANXI8B/10B coding mode is adopted to improve the accuracy of data transmission. The data transmission adopts the AC coupling technology, and the sending end and the receiving end have different common mode voltages, so that the interface can be made smaller. ANSI8B/10B coding is to divide a group of continuous 8-bit data into two groups of data, one group of 3-bit data and one group of 5-bit data, and then code the two groups of 4-bit data and one group of 6-bit data. AUX CH is a bidirectional half duplex transmission channel, the signal adopts an alternating current coupling differential transmission mode, the signal adopts Manchestell coding, and the AUX CH has a transmission rate of lMbps and a transmission distance of 15 m. The delay time of each transmission task is less than 500 mu s. The HPD is a unidirectional channel for connection and disconnection of lines.
At present, the following two ways are generally adopted to realize the anti-interference of the EDP signal:
the first way is: adding small capacitance on the EDP screen line or common mode inductance filtering on the differential signal line; however, the capacitor or the inductor is harmful to the signal and is not suitable for the scene of high signal transmission rate;
the second way is: the EDP screen package conductive cloth or the differential wire uses a shielding coaxial cable; however, because thicker conductive cloths cannot be used and the lap joint between the rings is short, the shielding effect is not ideal, and the price of using shielded coaxial cables is too high.
As shown in fig. 2, the HPD signal in the EDP signal has three states:
normally, the HPD is a low voltage pulse signal and the time is less than hpd_timeout;
in the pulled-out state, the HPD becomes low and the time is longer than hpd_timeout, at which time the main chip waits for the HPD to become high. In this state the main chip enters a protection mode and detects the HPD signal state. A100K pull-down resistor on the HPD detects whether the pull-up is occurring.
In the inserted state, the main chip detects that the HPD signal is changed from the low level to the high level, and the main chip restarts transmitting the display data.
Aiming at the technical problems and the three states of the HPD signal, the design idea of the application is as follows: when the EDP signal is interfered, a virtual hot plug action of changing the HPD from low level to high level is manufactured, and the main chip (CPU on the main board) can be triggered to retransmit the display data, so that normal display is restored.
For this purpose, as shown in fig. 3, the present application proposes the following technical scheme: when an interference signal (e.g., CPI test signal) is coupled to the EDP signal and a coupling voltage is generated, an error in data transmission may occur when the voltage on the EDP signal is equal to or greater than the maximum voltage Vt that it can withstand, resulting in display anomalies. At this time, the designed anti-interference circuit gives a hot plug signal to the HPD signal in the EDP signal, so that the main chip considers that the hot plug signal has a hot plug action, and the main chip resends the EDP signal data, thereby achieving the purpose of restarting data transmission and enabling the display to be recovered to be normal. And when no interference signal exists, the anti-interference circuit does not influence the normal signal performance.
This solution can theoretically solve most of the interference problems, but is theoretically not solved for very special cases where the interference voltage approaches the threshold voltage infinitely but causes interference phenomena. However, this is rarely the case, since the CPI test signal energy is relatively high, the threshold voltage is substantially exceeded without other anti-tamper countermeasures such as masking.
The anti-interference device has the advantages of no influence on EDP signals, low price and good anti-interference effect on interference signals.
After the application scenario and the design idea of the embodiment of the present application are introduced, the technical solution provided by the embodiment of the present application is described below.
As shown in fig. 4, an embodiment of the present application provides an anti-interference device for displaying signals, where the anti-interference device is connected with an embedded display interface EDP; the tamper resistant device is configured to: when the EDP signal is detected to have an interference signal, a low-level voltage is input to a hot plug detection HPD signal in the EDP signal, and when the EDP signal is detected to disappear, a zero voltage is input to the HPD signal, so that the HPD signal is changed from a low level to a high level, and a virtual hot plug action is generated.
Illustratively, the EDP signals include 1-4 differential signal pairs for transmitting data, hot plug HPD signals, and others. When differential signals are transmitted, the signal receiving end compares the difference value of the two voltages to judge the logic state sent by the sending end. When the interference signal is strong, the voltage difference of the differential signal is larger than or equal to the maximum voltage which can be born by the EDP signal.
In one embodiment of the present application, the embedded display interface EDP includes N pairs of differential signal terminals and one HPD pin;
the anti-interference device comprises N first anti-interference circuits; the first anti-interference circuit includes: a differential amplifying circuit and a first voltage comparator; wherein, a differential amplifying circuit is connected with a pair of differential signal terminals; the differential amplifying circuit outputs a voltage difference of the differential signal to the first voltage comparator; the first voltage comparator is connected with the HPD pin and inputs low-level voltage or zero voltage to the HPD pin.
Specifically, as shown in fig. 5, the differential amplifying circuit includes an operational amplifier a, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; the resistances of the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are the same; one end of the first resistor R1 is connected with a first signal end of the differential signal end, and the other end of the first resistor R1 is connected with a non-inverting input end of the operational amplifier A; one end of the third resistor R3 is connected between the first resistor R1 and the non-inverting input end of the operational amplifier A, and the other end of the third resistor R3 is connected with the output end of the operational amplifier A; one end of the second resistor R2 is connected with a second signal end of the differential signal end, and the other end of the second resistor R2 is connected with an inverted input end of the operational amplifier A; one end of the fourth resistor R4 is connected between the second resistor R2 and the reverse input end of the operational amplifier A, and the other end of the fourth resistor R4 is grounded; the output end of the operational amplifier A is connected with the non-inverting input end of the first voltage comparator B.
Correspondingly, the input voltage of the non-inverting input end of the first voltage comparator B is the voltage difference of the differential signal; the input voltage of the reverse input end of the first voltage comparator B is the maximum voltage which can be born by the EDP signal; when the input voltage of the non-inverting input end of the first voltage comparator B is greater than or equal to the input voltage of the inverting input end, the output end of the first voltage comparator B outputs the low-level voltage of the HPD signal to the HPD pin, otherwise, the output end of the first voltage comparator outputs zero voltage to the hot HPD pin.
Illustratively, the differential signal has two voltages Vp and Vn, respectively, vp being input to the non-inverting input (+) of the operational amplifier a and Vn being input to the inverting input (-) of the operational amplifier a; the output terminal of the operational amplifier outputs a voltage difference vd=vp-Vn; the voltage difference Vd is input to the non-inverting input (+) of the voltage comparator B, and the inverting input (-) of the voltage comparator B is the maximum voltage Vt that the EDP signal can withstand. The VHPD is the HPD signal low level voltage, vout output onto the HPD pin.
When the differential signal is not disturbed or when the disturbance is small, vd is smaller than Vt, vout is output as vout=0v, and the HPD signal is not affected at this time. When the differential signal is disturbed to enable the coupling voltage to be larger than or equal to the maximum voltage which can be born by the differential signal, namely Vd is larger than or equal to Vt, and the output of Vout is-VHPD; at this time, the HPD signal is changed to a continuous low level. When the interference signal disappears, the output of Vout becomes 0V, so that the HPD has a low level to high level action, and the main chip detects a virtual hot plug action, and the display data is retransmitted to resume normal data transmission. It is intuitively seen by the user that the display is restored to the normal state from the abnormal state such as seizing, screen-splash, etc.
The input/output logic level of the anti-interference circuit is shown in table 1:
TABLE 1
In addition, some single-ended signals in the EDP signals do not need an operational amplifier A, only one voltage comparator is needed, and the single-ended signals are connected to the non-inverting input end of the voltage comparator.
In one embodiment of the present application, the embedded display interface EDP further comprises a single-ended signal terminal; the anti-interference device further comprises a second anti-interference circuit; the second anti-interference circuit comprises a second voltage comparator; the input voltage of the non-inverting input end of the second voltage comparator is the voltage of a single-ended signal end; the input voltage of the reverse input end of the voltage comparator is the maximum voltage which can be born by the EDP signal; when the input voltage of the non-inverting input end of the voltage comparator is larger than or equal to the input voltage of the inverting input end, the output end of the first voltage comparator outputs the low-level voltage of the HPD signal to the HPD pin, otherwise, the output end of the first voltage comparator outputs zero voltage to the hot HPD pin.
As shown in fig. 6, the second anti-interference circuit includes a second voltage comparator C, and an exemplary single-ended signal voltage Vp is input to a non-inverting input terminal (+) of the second voltage comparator C, and an inverting input terminal (-) of the second voltage comparator C is a maximum voltage Vt that can be sustained by the EDP signal. The VHPD is the HPD signal low level voltage, vout output onto the HPD pin.
When the single-ended signal is not disturbed or when the disturbance is small, vp is smaller than Vt, vout is output as vout=0v, and the HPD signal is not affected at this time. When the single-ended signal is interfered to enable the coupling voltage to be larger than or equal to the maximum voltage which can be born by the single-ended signal, namely Vp is larger than or equal to Vt, and the output of Vout is-VHPD; at this time, the HPD signal is changed to a continuous low level. When the interference signal disappears, the output of Vout becomes 0V, so that the HPD has a low level to high level action, and the main chip detects a virtual hot plug action, and the display data is retransmitted to resume normal data transmission. It is intuitively seen by the user that the display is restored to the normal state from the abnormal state such as seizing, screen-splash, etc.
The frequency point where the CPI test signal is most likely to fail is found to be around 900MHz from an actual test of the CPI test signal, and then its period t=1.1 ns. The reaction time of a common voltage comparator is tens of ns, and the requirements cannot be met. At present, a plurality of high-speed comparators have reaction time of Ps level and can meet the requirements. Such as integrated chip HMC974LC3C, model number MAX40025A/MAX40025C/MAX40026 or faster. The performance requirements of a general comparator can also be met by adding a delay circuit. For other interfering signals, such as ESD interference, the half wavelength is tens of ns, and a general comparator is used, and still other interfering signals may have longer duration. The embodiment controls the signal with the reset function through the circuit design, and achieves the anti-interference purpose by restarting the data transmission.
As can be seen from the design of the anti-interference circuit, each differential signal in the EDP signals needs an anti-interference circuit, which can be high in cost, but the anti-interference circuit can reduce other anti-interference cost, such as conductive cloth of the EDP shielding wire, coaxial wires used by the EDP signals and the like. In order to reduce cost, an anti-interference circuit can be added for signals which are easy to cause problems in EDP signals, or a plurality of anti-interference circuits are integrated in one chip as much as possible, so that space and cost are further reduced.
In addition, the interference signal is a periodic signal, for example, the CPI interference signal is a periodic signal with a period of ns level, when the interference signal is at a high level and more than or equal to Vt, vout outputs a low voltage signal, when the interference voltage is at a low level, its value is less than Vt, and the output is at a high level, so that the HPD can complete the operation from the low level to the high level in one period of the interference signal. Or when the interference signal is short and suddenly disappears, the Vout also outputs a high level, so that the HPD finishes the action from the low level to the high level. If the interference signal duration is too short, it can be matched by a delay circuit.
Based on the same inventive concept, an embodiment of the present application provides a display including: the anti-interference device comprises a time sequence controller Tcon chip and a display signal of the embodiment of the application; the time sequence controller Tcon chip comprises an embedded display interface EDP; the embedded display interface EDP is connected with the anti-interference device.
The display may be a vehicle-mounted display device or a television, or may be a display of a mobile phone, a tablet computer, a notebook computer, or a computer, which is not particularly limited in the embodiment of the present application, and it is clear that the display receives display data through an EDP interface. The display of the embodiment has the same technical effect as the anti-interference device, namely has the advantages of no influence on EDP signals and good anti-interference effect on interference signals.
Based on the same inventive concept, as shown in fig. 7, an embodiment of the present application provides an electronic device, including a main board and a display of the embodiment of the present application; the main board is connected with an embedded display interface (EDP) of the display through an EDP signal line; the EDP signal line comprises a Main channel Main-Link and a hot plug detection HPD signal line; the Main channel Main-Link includes N differential signal line pairs.
The differential amplifying circuit of each first anti-interference circuit inputs the voltage difference of the differential signals to the non-inverting input end of the first voltage comparator; when the input voltage of the non-inverting input end of the first voltage comparator of any one of the first anti-interference circuits is larger than or equal to the input voltage of the inverting input end, the output end of the first voltage comparator outputs the low-level voltage of an HPD signal to the HPD pin, and when the input voltage of the non-inverting input end of the first voltage comparator is smaller than the input voltage of the inverting input end, zero voltage is input to the HPD pin; when the HPD signal is changed from low level to high level, the Main chip is triggered to send display data to the Tcon chip again through the Main channel Main-Link.
When the input voltage of the non-inverting input end of the second voltage comparator of any one second anti-interference circuit is larger than or equal to the input voltage of the inverting input end, the output end of the second voltage comparator outputs the low-level voltage of the HPD signal to the HPD pin, and when the input voltage of the non-inverting input end of the second voltage comparator is smaller than the input voltage of the inverting input end, zero voltage is input to the HPD pin; when the HPD signal is changed from low level to high level, the Main chip is triggered to send display data to the Tcon chip again through the Main channel Main-Link.
The electronic device shown in fig. 8 is merely a schematic illustration, and the display device may be an electronic device having a display function such as a mobile phone, a tablet computer, a notebook computer, a computer, or the like; the embodiment of the present application is not particularly limited. It is clear that the main chip of the electronic device transmits display data to the display via the EDP interface, and the display receives display data via the EDP interface.
The electronic equipment of the embodiment of the application has the same technical effects as the anti-interference device of the embodiment, namely the advantages of no influence on EDP signals and good anti-interference effect on interference signals.
Furthermore, although illustrative embodiments are described herein, the scope includes any and all embodiments having equivalent elements, modifications, omissions, combinations (e.g., of schemes across various embodiments), adaptations or alterations based on the present disclosure. Elements in the claims will be construed broadly based on the language used in the claims and not limited to examples described in the specification or during the lifetime of the application. Furthermore, the steps of the disclosed methods may be modified in any manner, including by reordering steps or inserting or deleting steps. It is intended, therefore, that the description be regarded as examples only, with a true scope being indicated by the following claims and their full range of equivalents.
The above description is intended to be illustrative and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used by those of ordinary skill in the art after reading the above description. Moreover, in the foregoing detailed description, various features may be grouped together to simplify the present disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Thus, the following claims are incorporated into the detailed description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that these embodiments may be combined with one another in various combinations or permutations. The scope of the application should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims (10)
1. An anti-interference device for display signals is characterized in that the anti-interference device is connected with an embedded display interface EDP; the tamper resistant device is configured to: when the EDP signal is detected to have an interference signal, a low-level voltage is input to a hot plug detection HPD signal in the EDP signal, and when the EDP signal is detected to disappear, a zero voltage is input to the HPD signal, so that the HPD signal is changed from a low level to a high level, and a virtual hot plug action is generated.
2. The display signal immunity device of claim 1, wherein the embedded display interface EDP comprises N pairs of differential signal terminals and one HPD pin;
the anti-interference device comprises N first anti-interference circuits; the first anti-interference circuit includes: a differential amplifying circuit and a first voltage comparator; wherein, a differential amplifying circuit is connected with a pair of differential signal terminals; the differential amplifying circuit outputs a voltage difference of the differential signal to the first voltage comparator; the first voltage comparator is connected with the HPD pin and inputs low-level voltage or zero voltage to the HPD pin.
3. The tamper resistant device of claim 2, wherein the differential amplification circuit comprises an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor; the first resistor, the second resistor, the third resistor and the fourth resistor have the same resistance value; one end of the first resistor is connected with a first signal end of the differential signal end, and the other end of the first resistor is connected with a non-inverting input end of the operational amplifier; one end of the third resistor is connected between the first resistor and the non-inverting input end of the operational amplifier, and the other end of the third resistor is connected with the output end of the operational amplifier; one end of the second resistor is connected with a second signal end of the differential signal end, and the other end of the second resistor is connected with an inverted input end of the operational amplifier; one end of the fourth resistor is connected between the second resistor and the reverse input end of the operational amplifier, and the other end of the fourth resistor is grounded; the output end of the operational amplifier is connected with the non-inverting input end of the first voltage comparator.
4. The anti-interference device for display signals according to claim 3, wherein the input voltage of the non-inverting input terminal of the first voltage comparator is a voltage difference of the differential signal; the input voltage of the reverse input end of the first voltage comparator is the maximum voltage which can be born by the EDP signal; when the input voltage of the non-inverting input end of the first voltage comparator is larger than or equal to the input voltage of the inverting input end, the output end of the first voltage comparator outputs the low-level voltage of the HPD signal to the HPD pin, otherwise, the output end of the first voltage comparator outputs zero voltage to the hot HPD pin.
5. The tamper resistant display signal device of claim 2, wherein said embedded display interface EDP further comprises a single ended signal terminal; the anti-interference device also comprises a second anti-interference circuit; the second anti-interference circuit comprises a second voltage comparator; the input voltage of the non-inverting input end of the second voltage comparator is the voltage of a single-ended signal end; the input voltage of the reverse input end of the voltage comparator is the maximum voltage of the EDP signal; when the input voltage of the non-inverting input end of the voltage comparator is larger than or equal to the input voltage of the inverting input end, the output end of the first voltage comparator outputs the low-level voltage of the HPD signal to the HPD pin, otherwise, the output end of the first voltage comparator outputs zero voltage to the HPD pin.
6. The tamper-resistant device of a display signal of claim 1, wherein the tamper signal is a periodic signal.
7. A display, comprising: a timing controller Tcon chip and an anti-interference device for display signals according to any one of claims 1 to 6; the time sequence controller Tcon chip comprises an embedded display interface EDP; the embedded display interface EDP is connected with the anti-interference device.
8. An electronic device comprising a motherboard and the display of claim 7; the main board is connected with an embedded display interface (EDP) of the display through an EDP signal line; the EDP signal line comprises a Main channel Main-Link and a hot plug detection HPD signal line; the Main channel Main-Link includes N differential signal line pairs.
9. The electronic device of claim 8, wherein the differential amplification circuit of each first tamper resistant circuit inputs a voltage difference of the differential signal to the non-inverting input of the first voltage comparator; when the input voltage of the non-inverting input end of the first voltage comparator of any one of the first anti-interference circuits is larger than or equal to the input voltage of the inverting input end, the output end of the first voltage comparator outputs the low-level voltage of an HPD signal to the HPD pin, and when the input voltage of the non-inverting input end of the first voltage comparator is smaller than the input voltage of the inverting input end, zero voltage is input to the HPD pin; when the HPD signal is changed from low level to high level, the Main board is triggered to send display data to the Tcon chip again through the Main channel Main-Link.
10. The electronic device according to claim 8, wherein when an input voltage of the non-inverting input terminal of the second voltage comparator of any one of the second anti-interference circuits is equal to or higher than an input voltage of the inverting input terminal, an output terminal of the second voltage comparator outputs a low-level voltage of the HPD signal to the HPD pin, and when the input voltage of the non-inverting input terminal of the second voltage comparator is lower than the input voltage of the inverting input terminal, a zero voltage is input to the HPD pin; when the HPD signal is changed from low level to high level, the Main chip is triggered to send display data to the Tcon chip again through the Main channel Main-Link.
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