JP2019105845A - Display device and control method thereof - Google Patents

Abstract

To provide a display device capable of suppressing a disturbed display even when an amount of video signal exceeding a corresponding transmission band is received, and to provide a method for controlling the display device.SOLUTION: When a clock bit lock, a symbol lock, and a channel equalization are failed for a data stream received from an external device, the display image is changed from an image based on a data stream to a predetermined image.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a display device and a control method thereof.

  For example, a high resolution display device such as 4K2K (3840 pixels × 2160 pixels) and SHV (7680 pixels × 4320 pixels) includes a display interface for inputting a high resolution video signal from an external device. As a standard of a display interface corresponding to a high resolution video signal, for example, DisplayPort (registered trademark, hereinafter DP), HDMI (registered trademark), etc. are given.

  According to these standards, when a device (source device) for transmitting a video signal to a display device and the display device (sink device) are connected, information about the sink device is transmitted from the sink device to the source device as Extended Display Identification Data (EDID) It notifies with the data of). The EDID stores, for example, the model name of the sink device, the combination of the corresponding resolution and refresh rate, the bit depth, the pixel encoding method, and the like.

  By referring to the EDID, a source device such as a computer device can transmit an appropriate video signal according to the capability of the sink device. In the DP standard, a procedure called link training is performed between the source device and the sink device to determine the video data transmission rate, the number of transmission paths (lanes), and the like.

  However, due to a failure of the source device, a video signal that can not be received or displayed by the sink device may be transmitted. For example, a video signal having a resolution not supported by the sink device may be transmitted, or a video signal in an amount exceeding a transmission band determined by the determined transmission rate and the number of transmission paths may be transmitted. In this case, the sink device can not normally receive and display the video signal, and a disturbed video is displayed.

  As a response of the display device (sink device) when the received video signal can not be displayed normally, the content of the EDID is changed and transmitted to the source device (Patent Document 1), a black screen is displayed, or an error message is displayed. It is known to display (Patent Document 2).

JP, 2009-33446, A JP, 2012-226310, A

  However, for example, when a video signal whose amount exceeds the transmission band (transmission rate and the number of transmission paths) determined by link training is transmitted, the display can not be returned to normal unless the transmission band is reset. To re-set the transmission band, it is necessary to perform link training again, and even if the EDID is changed as in Patent Document 1, it is not possible to interrupt the disturbed display.

  Further, in the method of Patent Document 2, when the format (resolution and refresh rate) of the video signal does not correspond to the display device, displaying the black screen can interrupt the disturbed display. However, it is not possible to cope with the case where a video signal of a format compatible with the display device is transmitted in an amount exceeding the transmission band, and it is not possible to interrupt the disturbed display.

  The present invention has been made in view of the problems of the prior art as described above, and a display device capable of suppressing disordered display even when a video signal of an amount exceeding a compatible transmission band is received, and control thereof Intended to provide a method.

  The above-mentioned objects are: generation means for generating a clock from a data stream received from an external device, extraction means for extracting symbol data from a data stream at timing based on the clock, and output means for outputting a display image based on a data stream And detection means for detecting any failure of clock bit lock by the generation means, symbol lock by the extraction means, and channel equalization for a data stream received from an external device; And an instruction unit for instructing the output unit to change the display image into a predetermined image.

  According to the present invention, it is possible to provide a display device capable of suppressing disordered display and a control method thereof even when a video signal of an amount exceeding a compatible transmission band is received.

A block diagram showing an example of a functional configuration of a projector that is an example of a display device according to an embodiment of the present invention Flowchart of overall operation of the projector of FIG. 1 Diagram showing the relationship between symbols and data in the 8B10B encoding system Block diagram showing an example of functional configuration of the video input unit 110 of FIG. 1 Flowchart relating to video signal monitoring processing in the first embodiment Flowchart related to video signal monitoring processing in the modification of the first embodiment Flowchart relating to video signal monitoring processing in the second embodiment The figure which shows the example of the combination of the video format which the projector concerning embodiment concerns, and a transmission condition

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. Although a configuration in which the present invention is applied to a projector will be described below, the projector is only an example of a display device to which the present invention can be applied. The present invention is applicable to display devices in general that generates (recovers) a clock for data reception (sampling) from a video data stream. Here, a projector compliant with the DisplayPort standard will be described as an example of such a display device, but a display device compliant with another standard such as HDMI may be used.

● (first embodiment)
(Projector configuration)
FIG. 1 is a block diagram showing an example of the functional configuration of a liquid crystal projector (hereinafter simply referred to as a projector) 100 according to the present embodiment. The control unit 101 is, for example, one or more microprocessors. The control unit 101 loads the program stored in the internal memory 115 into the RAM 132 and executes the program to control the operation of each block of the projector 100, thereby realizing each function of the projector 100. The control unit 101 is connected to each block directly or by a bus 133, and can communicate with each block. The operation unit 102 is, for example, an input device such as a button, a switch, or a touch panel provided on a housing of the projector 100. The power supply unit 103 performs control for supplying a predetermined voltage generated by the power supply input unit 131 from a commercial power supply to each block of the projector 100.

  The liquid crystal unit 104 has, for example, one or three liquid crystal panels. In the present embodiment, the display resolution of the liquid crystal unit 104 is set to 3840 pixels × 2160 pixels. The liquid crystal drive unit 105 drives the liquid crystal panel of the liquid crystal unit 104 based on the image signal supplied from the image processing unit 116 to display an image on the liquid crystal panel.

  The liquid crystal unit 104 is illuminated by the light source 106, and the image displayed on the liquid crystal unit 104 is projected on a screen or the like by the projection optical system 107. A light source control unit 108 controls the light amount of the light source 106. Further, the projection optical system 107 includes a lens for adjusting the angle of view and a lens for adjusting the focus, and these lenses are driven by the optical system control unit 109 in accordance with an instruction from the control unit 101.

  The video input unit 110 is an interface through which the projector 100 (sink device) receives a video data stream from an external device (source device) such as a personal computer or a media player. In the present embodiment, the video input unit 110 has a connector and a circuit conforming to the DP standard. The video input unit 110 also implements a function of converting symbol data extracted from the 8B10B encoded video data stream into a signal that can be received by the image processing unit 116, a video data stream reception detection function, an 8B10B decoding function, and the like. The video signal and the image signal received by the video input unit 110 are supplied to the image processing unit 116.

  In the DP standard at the present time, main links of 0 to 3 lanes, an auxiliary channel (AUX-CH), and an HPD (Hot Plug Detect) are defined as signal lines. The DP standard encodes the video signal and control signal in the 8B10B encoding method and transmits it as a data stream, and there is no clock signal line. The sink device recovers (generates) a clock bit-locked to the video data stream using a clock recovery function, detects a symbol boundary correctly from the video data stream, and extracts symbol data (symbol lock). The auxiliary channel is used for EDID exchange between devices, link training, and the like.

  The EDID storage unit 111 is, for example, a non-volatile memory, and stores an EDID storing information on the projector 100. When the source device conforming to the DP standard is connected to the projector 100 through the video input unit 110, the EDID stored in the EDID storage unit 111 is acquired.

  The USB interface (I / F) 112 is an interface for communicating with an external device conforming to the USB standard. The external device may be a transmitter of video data or image data, an input device such as a pointing device or a keyboard, or a storage device.

  A card interface (I / F) 113 is an interface for reading and writing a semiconductor memory card. The communication unit 114 is a network interface for communicating with an external device by wired or wireless communication. The internal memory 115 stores programs executed by the control unit 101, various setting values, GUI data, and the like. The internal memory 115 may be a non-volatile memory, or may be a storage device such as a hard disk or an SSD.

  The file reproduction unit 121 has a viewer function of a document file of a predetermined format. For example, the file reproduction unit 121 opens a document file read from the memory card through the card interface 113, generates an image signal for display, and outputs the image signal to the image processing unit 116.

  The image processing unit 116 corrects the video signal received from the video input unit 110 or the file reproduction unit 121 so as to be a signal suitable for display on the liquid crystal unit 104. For example, the image processing unit 116 converts the resolution of the video signal according to the display resolution of the liquid crystal unit 104, doubles the number of frames of the input video signal for AC drive of the liquid crystal panel, and further displays the image by the liquid crystal panel. Apply a suitable correction.

  Note that AC driving of a liquid crystal panel is a driving method in which the direction of the voltage applied to the liquid crystal panel is switched and displayed by utilizing the property that the voltage applied to the liquid crystal panel can be displayed in either the forward or reverse direction. When the liquid crystal panel is AC driven, it is necessary to supply one video signal (frame) to the liquid crystal drive unit 105 for each direction of the voltage to be applied. Therefore, the image processing unit 116 doubles the number of frames of the video signal and generates a video signal for each direction of the voltage to be applied. The liquid crystal drive unit 105 drives the liquid crystal panel of the liquid crystal unit 104 based on the image signal supplied from the image processing unit 116 to display an image.

  The image processing unit 116 can also perform measurement and analysis on the video signal received through the video input unit 110. For example, the image processing unit 116 measures the timing of a synchronization signal and the like included in the video signal, and stores the timing in a storage device readable by the control unit 101, such as an internal register or a memory. The image processing unit 116 can also store gradation information of each pixel included in the video signal, for example, in an internal register.

  The image processing unit 116 can also apply geometric deformation processing such as trapezoidal distortion correction (keystone correction) processing to the video signal. The keystone correction may be automatically applied by the image processing unit 116 based on the inclination angle obtained by the inclination sensor 117, or may be applied according to an instruction through the operation of the operation unit 102. The timer 118 is used to detect the operation time of the projector 100 and each block. The thermometer 119 measures the temperature near the light source 106, the temperature near the liquid crystal unit 104, the outside air temperature, and the like, and notifies the control unit 101 of the temperature.

  The infrared receiving unit 122 receives an infrared ray from the remote control of the projector 100 or the like, converts it into an electric signal, and outputs the electric signal to the control unit 101. The infrared ray receiving unit 122 is installed at a plurality of places of the casing of the projector 100, for example, in front and back.

  The focus detection unit 123 detects the distance between the projector 100 and the projection surface (screen or the like) as a projection distance using, for example, infrared rays or ultrasonic waves. The imaging unit 124 images the direction of the projection plane (usually, the optical axis direction of the projection optical system 107). The screen photometry unit 125 measures the reflected light amount and the luminance of the projection surface. The display unit 128 is, for example, an LCD, and displays the status of the projector 100, a warning, a GUI, and the like according to the control of the display control unit 129. The battery 130 is a power supply used when the projector 100 is not connected to an external power supply. The cooling unit 120 is constituted of, for example, a heat sink and a fan, and emits heat inside the projector 100. The file reproduction unit 121 generates display image data from the file data based on an instruction from the control unit 101. The RAM 132 loads a program to be executed by the control unit 101, uses it as a work area during program execution, or uses it as a frame memory of image data to be projected.

(Operation of the projector)
Next, the operation of the projector 100 having the above-described configuration from when the power is turned on will be described.
When the control unit 101 detects an instruction to turn on the power through the operation unit 102, the control unit 101 instructs the power supply unit 103 to supply power to each block and puts each block in a standby state. Then, when power is supplied from the power supply unit 103 to each block, the control unit 101 instructs the light source control unit 108 to cause the light source 106 to emit light. Next, the control unit 101 instructs the optical system control unit 109 to adjust the projection optical system 107 based on, for example, the projection distance obtained by the focus detection unit 123 and the projection size obtained by the imaging unit 124. Do. The optical system control unit 109 drives the focus lens of the projection optical system 107 to perform control so that an image is formed at the projection distance. Further, the optical system control unit 109 drives the variable power lens of the projection optical system 107 to control the projection image to have a predetermined size.

  When the video signal input to the video input unit 110 is projected, the video signal is variously corrected and scaled by the image processing unit 116 so as to be an image suitable for display, and then the liquid crystal drive unit 105 is used as projected image data. It is input. The liquid crystal drive unit 105 causes the liquid crystal panel of the liquid crystal unit 104 to display projected image data. The image displayed on the liquid crystal panel of the liquid crystal unit 104 is irradiated with the light from the light source 106, and is projected on the projection plane by the projection optical system 107.

  During the projection operation, the control unit 101 monitors the measured value of the thermometer 119, for example, operates the cooling unit 120 when the measured value exceeds the predetermined value, and stops the operation of the cooling unit 120 when the measured value is less than the predetermined value. The light source 106 and the temperature inside the projector 100 are managed.

  When an instruction to turn off the power is detected through the operation unit 102, the control unit 101 instructs each block to perform termination processing. The control unit 101 sequentially instructs the power supply unit 103 to end the power supply to the block for which the end processing has been completed. The control unit 101 causes the cooling unit 120 to operate until the measurement value of the thermometer 119 becomes lower than or equal to a preset temperature, and then ends the power supply to the cooling unit 120.

(Image display operation of the projector)
Next, an operation from the connection of an external device to the video input unit 110 to the projection of the video signal will be further described using the flowchart shown in FIG.
In step S101, the control unit 101 detects that the external device is connected to the video input unit 110 by polling or interruption.
In step S102, the control unit 101 asserts the HPD signal by setting the voltage of the HPD (Hot Plug Detect) pin of the video input unit 110 to a prescribed value, and notifies the external device of the connection. In response to this, the EDID request is transmitted from the external device through the AUX-CH.

  In step S103, when the control unit 101 receives an EDID request from an external device on the AUX-CH through the video input unit 110, the control unit 101 reads out the EDID from the EDID storage unit 111. Then, the control unit 101 notifies the external device of the EDID through the video input unit 110 by AUX-CH. When the external device receives the EDID from the projector 100, the external device requests the value of the receiver capability field of Display Port Configuration Data (DPCD) through AUX-CH.

  The DPCD is data included in the video input unit 110, and can be accessed from an external device through the AUX-CH as a storage area (or register) having a specific address. The DPCD has a receiver capability field in which a transmission rate, the number of transmission lanes, and the like supported by the DP receiver are stored, and a link configuration field in which various setting values are stored. The DPCD also has a link / sink status field in which information about link training results and the current state of the display device (sink device) is stored.

  In step S104, when the control unit 101 receives a DPCD (receiver capability field) read request from the external device on the AUX-CH through the video input unit 110, the control unit 101 notifies the external device on the AUX-CH of the requested data through the video input unit 110. Do.

  DP standard Ver. In 1.3, a maximum of four transmission lanes (main links) can be used in combination of one lane, two lanes, or four lanes. Also, the transmission rate of each lane can be selected from 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, and 8.1 Gbps. The external device determines a combination of the number of transmission lanes and the transmission rate according to the capability of the projector 100 indicated by DPCD and EDID and the video format (resolution, frame rate, color depth, etc.) to be transmitted.

  Then, the external device writes necessary setting values in the link configuration field of the DPCD through the AUX-CH, and starts link training by transmitting a link training pattern on the main link. As described above, link training is a procedure for determining transmission conditions of a video data sequence between an external device and a display device.

  In S105, link training is performed between the control unit 101 (image input unit 110) and the external device. In link training, first, a training pattern for a clock recovery sequence is transmitted from an external device. In the video input unit 110, when the PLL for clock recovery is locked to the training pattern and bit lock of the recovered clock is successful, a specific bit of the link / sink status field of DPCD indicating that the clock recovery is successful is set. The external device refers to the DPCD and starts transmission of a training pattern for a channel equalization sequence when it can confirm that clock recovery has been successful for all lanes used.

  The video input unit 110 performs channel equalization, detection of symbol boundaries (symbol lock), alignment between lanes, and if successful, sets specific bits corresponding to individual items in the link / sync status field of the DPCD. The link / sink status field of the DPCD includes, for each lane, a bit indicating success or failure of clock recovery, channel equalization, symbol synchronization, or alignment between lanes.

Here, channel equalization in the channel equalization sequence is
(1) The external device transmits a training pattern for the channel equalization sequence adjusted in level according to the channel equalization parameters (voltage amplitude (Swing) and amplification degree (Pre-Emphasis) at the end of the clock recovery sequence. ,
(2) The video input unit 110 attempts clock recovery for the received training pattern,
(3) The video input unit 110 determines that the channel equalization has succeeded if the clock recovery succeeds,
Have the following procedure. If the clock recovery is not successful, the video input unit 110 may request an external device to increase the power supply amplitude (Voltage-Swing) and the amplification factor (Pre-Emphasis) through the link / sink link configuration field of the DPCD.

  In the DP standard, a video data stream transmitted from an external device (source device) to a display device (sink device) is composed of 8B10B encoded symbols. FIG. 5 shows a symbol data table of 8B10B encoding. The symbol data has a data code Dxx.1 corresponding to 8-bit data 00h to FFh in 8B10B encoding. It consists of y (xx is 0 to 31, y is 0 to 7) and 12 control codes K28.0 to K28.7, K23.7, K27.7, K29.7, K30.7. In the 8-bit data, the upper 5 bits are 5B6B encoded and the lower 3 bits are 3B4B encoded to be converted into 10-bit code data.

  As shown in the figure, two types of code data (RD−, RD +) of different polarities (running disparity) are assigned to the same symbol, and on the transmission side, the numbers 0 and 1 of the code string are equalized. Select one of them and output. The polarity of the code data to be output next is determined by the type of the code data output immediately before and its polarity. Also, control symbols are used to indicate data boundaries and idle states. For example, in the DP standard, K25.8 is inserted into the encoded data stream as a code (called a comma) indicating a data boundary, and is used for symbol boundary detection (symbol lock) on the receiving apparatus side.

  The external device reads the link / sink status field of the DPCD and determines the success or failure of link training. If the display device fails in any of clock recovery, channel equalization, symbol lock, and link alignment, the external device determines that link training has failed. In this case, the external device changes the transmission conditions (the transmission rate, the number of transmission lanes, and / or the channel equalization parameter) in accordance with the DP standard, and performs link training again.

  Therefore, in step S106, the control unit 101 determines whether relink training has been started from the external device. If it is determined that the relink training has been started, the process returns to step S105, and link training is performed again from clock recovery. On the other hand, when determining that link training is successful, the external device notifies the end of link training by writing a specific value to a specific address in the link configuration field of the DPCD. Then, after transmitting a predetermined idle pattern in which K25.8 symbols are included in a constant cycle, transmission of the video data stream is started. Therefore, if link training under another transmission condition is not started in S106, the video input unit 110 starts receiving the idle pattern and the video data stream from the external device in S108.

  When the control unit 101 detects the reception of the video data stream by polling or interruption in S109, the control unit 101 reads out the video format information from the video input unit 110. Specifically, the control unit 101 acquires attribute information (horizontal and vertical resolution, signal format, color depth and the like) of the video inserted in the blanking period of the video signal through the video input unit 110 and stores the information in the RAM 132.

  In step S110, the control unit 101 sets horizontal and vertical resolutions included in the read attribute information in the image processing unit 116. The image processing unit 116 reflects the resolution of the video in the subsequent image processing. For example, the image processing unit 116 uses the resolution of the image to calculate the magnification when scaling. Further, when generating the display image on which the OSD menu is superimposed, the image processing unit 116 can use the resolution of the image in order to prepare the OSD menu of the resolution in consideration of the scaling factor.

  In step S111, the control unit 101 executes a projection operation (control of the reception of a video data stream, clock recovery, symbol extraction, decoding, generation and display of a display image, an operation for an instruction through the operation unit 102, and the like).

  As described above, since data transmission in the DP standard does not use a clock signal line, it is necessary to restore (generate) a clock from a video data stream to be received in a display device. Therefore, the video input unit 110 has a clock recovery function of recovering a clock from data.

FIG. 4 is a block diagram schematically showing the configuration of the video input unit 110. As shown in FIG. In practice, the configuration shown in FIG. 4 is provided for each lane of the main link.
The data sampling unit 1101 samples the 8B10B encoded video data stream (rxDATA) received from the external device based on the clock (recCLK) restored by the clock recovery function and while separating at a symbol boundary. The data sampling unit 1101 outputs the sampled data (bit DATA) to the deserialization unit 1105.

  The CR (Clock Recovery) unit 1102 is a PLL (Phase Locked Loop) configured of a phase comparator, a VCO (Voltage-Controlled Oscillator), and the like. The CR unit 1102 also has a variable frequency divider, and can generate a signal obtained by multiplying the oscillation frequency of the VCO. The clock is restored (generated) by controlling the oscillation frequency of the VCO based on rxDATA from an external device and locking the PLL to the edge (rise and fall of the signal) of rxDATA. The CR unit 1102 supplies the recovered clock (recCLK) to the data sampling unit 1101 and the lock determination unit 1104. When the transmission rate of rxDATA changes, the PLL also follows and the frequency of recCLK also changes. However, when the transmission rate of rxDATA exceeds the PLL lock frequency range, the PLL is unlocked and can not be bit locked to rxDATA (clock recovery failure).

  For example, if rxDATA is transmitted at a transmission rate exceeding the band determined by link training, the PLL may unlock and clock recovery may fail. As a specific example, when transmitting a video signal having an effective resolution of 4096 pixels × 2160 pixels, a vertical frequency of 60 Hz, and a color depth of 8 bits / pixel, the transmission bandwidth including overhead by 8B10B encoding is 20.878 Gbps. This value is based on Coordinated Video Timings (CVT) 1.2 issued by Video Electronics Standards Association (VESA). For example, as a result of link training, it is assumed that it is determined that the external device uses four lanes with a transmission rate of 5.4 Gbps (bandwidth 21.6 Gbps). However, if the color depth of the video signal transmitted from the external device is 12 bits / pixel in practice, the required transmission band is 25.05 Gbps according to CVT 1.2, and the band determined by link training is Over. In this case, the PLL of the video input unit 110 can not follow and may unlock.

  The free-running oscillator 1103 is an oscillator that outputs a reference clock (refCLK) used to determine whether or not the PLL of the CR unit 1102 is locked (whether the recovered clock is bit synchronized with rxDATA). The free-running oscillator 1103 supplies a reference clock to the lock determination unit 1104.

  The lock determination unit 1104 is a counter that determines whether the PLL of the CR unit 1102 is in the lock state or the unlock state (success or failure of clock recovery) based on the restored clock from the CR unit 1102 and the reference clock from the free-running oscillator 1103. It is a circuit. When it is determined that the PLL is in the unlocked state (clock recovery failed), the lock determination unit 1104 outputs an UNLOCK signal to the register 1108. For example, when the recCLK / refCLK is different from a predetermined counter value (for example, a counter value at the time of link training), the lock determination unit 1104 determines that the lock state is an unlock state. Note that the output of the UNLOCK signal may be an operation of setting a bit (referred to as an UNLOCK bit) assigned to the UNLOCK signal in the register 1108 or an operation of clearing a bit indicating successful clock recovery.

  As described above, in the channel equalization sequence in link training, the register (bit indicating the result of channel equalization based on the success or failure of clock recovery attempted by the external device on the training pattern by the signal whose level is adjusted for channel equalization You need to set or clear). The lock determination unit 1104 sets or clears a bit in the register 1108, which indicates the result of the sequence, based on either the clock recovery in link training or the sequence of channel equalization.

  The deserialization unit 1105 converts serial data supplied from the data sampling unit 1101 into 10-bit parallel symbol data (symDATA). The deserialized symbol data is supplied to the 8B10B decoder 1110. The 8B10B decoder 1110 decodes 10-bit parallel symbol data into 8-bit video data and outputs the video data to the image processing unit 116.

  The symbol data table 1107 stores the symbol data table described with reference to FIG. The symbol data comparison unit 1106 checks whether symDATA output from the deserialization unit 1105 exists in the symbol data table 1107. If symDATA does not exist in the symbol data table 1107, it means that data can not be sampled at the correct timing (symbol lock has failed). Therefore, the symbol data comparison unit 1106 outputs the NOT_IN_TABLE signal to the register 1108. Alternatively, the symbol data comparison unit 1106 may set a bit (referred to as a NOT_IN_TABLE bit) of the register 1108 assigned to the NOT_IN_TABLE signal.

  Note that the output of the NOT_IN_TABLE signal may be an operation of clearing the bit indicating the symbol lock success in the register 1108. On the other hand, when symDATA exists in the symbol data table 1107, the symbol data comparison unit 1106 does not output the NOT_IN_TABLE signal because the symbol is correctly extracted from the received video data stream (symbol lock state).

  The register 1108 is a storage device (for example, a latch circuit) in which the determination result of the lock determination unit 1104 and the comparison result of the symbol data comparison unit 1106 are stored. Note that a part of DPCD (link / sync status field) may be used as the register 1108 for holding results such as clock recovery at the time of link training in the DP standard and symbol boundary detection. The link / sink status field of the DPCD is provided to confirm the status of the display device from an external device at the time of link training, and is not particularly used after the link training. Therefore, it can be used to hold the determination result of the lock determination unit 1104 and the comparison result of the symbol data comparison unit 1106.

  In this embodiment, even after link training is completed and reception of the video data stream is started, the lock determination unit 1104 and the symbol data comparison unit 1106 continuously determine whether clock recovery is successful or symbol lock is successful, and the register 1108 Reflect the judgment result. The control unit 101 refers to the register 1108 of the video input unit 110 and determines whether clock recovery from the video data stream (rxDATA) is successful (bit lock state or unlocked state) or symbol lock is successful (locked state or unlocked). I can know the lock state).

  When the transmission rate and the number of transmission lanes are determined by link training and reception of the video data stream is started, the video input unit 110 starts clock recovery and data sampling based on the recovered clock and the detected data boundary (S108 in FIG. 2). ). The lock determination unit 1104 and the symbol data comparison unit 1106 continuously and repeatedly execute the determination operation, and always reflect the determination result in the register 1108. The control unit 101 executes the monitoring operation shown in the flowchart of FIG. 3 while executing S109 and the subsequent steps of FIG.

  At S205, the control unit 101 reads the UNLOCK bit in the register 1108. Then, in step S206, the control unit 101 determines whether the read bit indicates a failure in clock recovery, and if it is determined that a failure is indicated, the process proceeds to step S207. If the UNLOCK bit of the register 1108 is set, the control unit 101 determines that clock recovery has failed. If the register 1108 is DPCD, the control unit 101 reads a bit indicating success or failure of clock recovery, and determines that the clock recovery has failed if the bit is cleared. If it is not determined that the read bit indicates that the clock recovery has failed, the control unit 101 returns the process to S205, for example, after a predetermined time. Also, because clock recovery is performed lane by lane, there is also an UNLOCK bit for each lane. If multiple lanes are used, the control unit 101 advances the process to step S207 if there is at least one lane for which clock recovery has failed.

  In step S207, the control unit 101 instructs the image processing unit 116 to mute the image. In response to the video mute instruction, the image processing unit 116 outputs a predetermined image (for example, an image of the same color on the entire surface) to the liquid crystal drive unit 105 instead of the image based on the received video data. This makes it possible to prevent the display of a disturbed image. Note that the image displayed at the time of video mute may include a message prompting confirmation or reconnection of the connection with an external device.

As described above, the control unit 101 periodically reads the UNLOCK bit of the register 1108, for example, to confirm the success or failure of the clock recovery, and when it is detected that the clock recovery has failed, the video mute is started. If it is detected that the clock recovery is successful, the video mute process is not performed.
The UNLOCK bit of the register 1108 is assumed to be reset when the control unit 101 reads it, so that the latest judgment result is always reflected.

  Here, although the control unit 101 instructs the image processing unit 116 to mute the video immediately upon detection of a failure in clock recovery, for example, when a failure in clock recovery is detected continuously for a plurality of predetermined times, a video is detected. You may make it instruct | indicate a mute. Furthermore, in addition to the instruction of video mute, the control unit 101 may notify the user that an illegal signal is being received, for example, through OSD (On Screen Display).

  Furthermore, since the configuration according to the DisplayPort standard has been described in the present embodiment, the received data is 8B10B encoded. However, the configuration of the present embodiment does not depend on a specific encoding method as long as a clock can be generated from received data. For example, it may be received data encoded by a clock embedding method such as 10B12B, 64B66B, 64B67B, 128B130B. Therefore, the interface standard with the external device is not limited to the DisplayPort standard.

  As described above, according to the present embodiment, the success or failure of clock recovery from video data stream data received from an external device is determined, and video mute is started when at least one failure of clock recovery is detected. . Therefore, even if clock recovery fails due to, for example, the transmission of data in a band exceeding the reception capability of the display device, the display device can cope with such a situation that a disturbed image is not displayed. In particular, a display device conforming to the Displayort standard is useful because a DPCD used for link training can be diverted as an area for storing information indicating success or failure of clock recovery.

(Modification)
Next, a modification of the first embodiment will be described. The first embodiment is configured to suppress a disordered display by detecting a failure of clock recovery during video data stream reception and switching a display image. However, when the failure of the symbol lock is detected by the symbol data comparison unit 1106 described above, the display image may be switched. If the clock recovery fails, of course, even if the clock recovery succeeds, the correct data can not be received unless the symbol lock is made, which may cause a disordered display. For example, symbol lock may fail due to the performance of the data sampling unit 1101 or the quality of the transmission path.

  Therefore, when the failure of the symbol lock is detected, switching the display screen can suppress the display disordered not only when the cause of the failure of the symbol lock is the failure of the clock recovery.

  FIG. 6 is a flowchart of a monitoring operation performed by the control unit 101 in parallel with image display after link training is completed and reception of a video data stream is started in this modification. As in FIG. 3 of the first embodiment, the control unit 101 executes in parallel with S109 and subsequent steps in FIG.

  Next, in step S305, the control unit 101 refers to the register 1108 to determine whether the symbol lock has succeeded. The control unit 101 reads the NOT_IN_TABLE bit of the register 1108. Then, if the NOT_IN_TABLE bit is set, the control unit 101 determines that the symbol lock has failed (symbol unlock state). If the register 1108 is DPCD, the control unit 101 reads a bit indicating the success or failure of symbol lock, and determines that the symbol is unlocked if the bit is cleared. If the control unit 101 determines that the symbol is unlocked, the process proceeds to step S307. If not determined, for example, the process returns to step S305 after a predetermined time.

  In step S307, the control unit 101 instructs the image processing unit 116 to mute the image. In response to the video mute instruction, the image processing unit 116 outputs a predetermined image (for example, an image of the same color on the entire surface) to the liquid crystal drive unit 105 instead of the image based on the received video data. This makes it possible to prevent the display of a disturbed image. Note that the image displayed at the time of video mute may include a message prompting confirmation or reconnection of the connection with an external device.

  As described above, for example, the control unit 101 periodically refers to the register 1108 to check the success or failure of the symbol lock, and does not perform the video mute processing if it is in the locked state, and performs the video mute processing if it is in the unlocked state. When the control unit 101 reads out the NOT_IN_TABLE bit of the register 1108, the held data is reset.

  Here, when the control unit 101 detects a symbol lock failure (unlock state), it immediately instructs the image processing unit 116 to mute the image, but for example, a predetermined multiple symbol failure failures are detected. At this time, an instruction to mute the image may be issued. Furthermore, in addition to the instruction of video mute, the control unit 101 may notify the user that an illegal signal is being received, for example, through OSD (On Screen Display).

  Although the symbol data to be compared is not limited here, for example, it is compared whether a predetermined code (for example, K28.5 comma code etc.) included in the video data stream to be received is included in symDATA. It is also good. Furthermore, the success or failure of the symbol lock may be determined from the change in the polarity of the running disparity of symDATA output from the deserialization unit 1105. For example, if the same polarity continues, the symbol data comparison unit 1106 may drift the recCLK. Therefore, when the same polarity continuation is detected, it may be determined that the symbol lock has failed. Alternatively, a bit indicating presence or absence of a running disparity error may be provided in the register 1108.

  The bit indicating the success or failure of the channel equalization processing defined in the DP standard can be used similarly to the bit indicating the success or failure of symbol locking.

  In this modification, the success or failure of symbol lock is determined by comparing sampled symbol data (symDATA) with defined symbol data, and if it is determined that symbol lock has failed, the video is muted. Also, when it is determined that channel equalization has failed, the video is muted. In the present modification, it is possible to detect the situation where the display is disturbed other than the failure of the clock recovery on the display device side and prevent the disturbed video from being displayed. Further, the display device conforming to the DisplayPort standard is useful because it is possible to divert the DPCD used for link training as a region for storing information indicating the success or failure of symbol lock or channel equalization.

Second Embodiment
Next, a second embodiment of the present invention will be described. In this embodiment, when clock recovery fails, the transmission condition is changed on the display device side and link training is performed to change the transmission condition corresponding to the transmission band of the video data stream from the external device. It features.

  Specifically, as shown by the dotted line in FIG. 2, when link training is completed and reception of the video data stream is started, the control unit 101 executes transmission condition application processing in S120. Details of the transmission condition application process will be described with reference to FIGS. 7 and 8.

  Here, sharing of EDID and link training have been completed, and the video format is 4096 pixels × 2160 pixels, 60 Hz vertical frequency, and 8 bits / pixel color depth. Further, it is assumed that the number of transmission lanes 4 and the transmission rate of 8.1 Gbps are determined by the external device as a result of link training. However, it is assumed that an external device has transmitted a video data stream at a transmission rate exceeding 8.1 Gbps per lane due to a malfunction.

  In step S401, the control unit 101 reads the UNLOCK bit of the register 1108. In step S402, the control unit 101 determines whether the clock recovery is successful. If it is determined that the clock recovery is successful (locked state), the control unit 101 maintains the initial conditions for link training (implemented in S105), and ends the transmission condition application processing.

  On the other hand, if it is determined that the clock recovery has failed (unlocked state), the control unit 101 temporarily suspends the projection process and advances the process to S403. Note that the video mute process may be performed at this point in time as shown as S403 '.

  In the process after S403, the control unit 101 executes control to change the transmission conditions such as the transmission rate and the number of transmission lanes for the external device based on the information that the projector 100 holds in the EDID storage unit 111 and the internal memory 115. .

  FIG. 5 shows a table showing video formats supported by the projector 100 for each transmission condition. The table holds a horizontal resolution 301, a vertical resolution 302, a frame rate 303, a bit depth 304, and a color format 305 (including a pixel encoding method). The table also includes the bandwidth 306 required to transmit each video format. Reference numerals 307 to 310 indicate the correspondence between the combination of the transmission rate per lane and the number of transmission rates and the video format, and indicate that .smallcircle. Corresponds to each other. Of the tables, items 301 to 305 are stored in the EDID storage unit 111 of the projector 100, and items 306 to 310 are stored in the internal memory 115, and the control unit 101 can read these pieces of information via the bus 133 is there.

  In step S403, the control unit 101 determines whether all the transmission conditions (conditions indicated by ○ in the table in FIG. 5) corresponding to the received video format have been tried, and it is determined that all the enforcement has been performed. For example, if it is not determined, the process proceeds to S404. For example, the control unit 101 can hold information representing the tried and done conditions in the RAM 132, and can make a determination by comparing with a table. Alternatively, the control unit 101 may hold information representing all the transmission conditions to be tried in the first trial in the RAM 132, and delete the information corresponding to the tried conditions. Information representing the transmission condition determined by the link training in S105 is not held in the RAM 132. In this case, if information representing the transmission condition remains in the RAM 132 in S403, the control unit 101 can determine that there is an untried transmission condition.

  In step S404, the control unit 101 selects one of the transmission conditions not yet tried other than the transmission condition determined by the link training in step S105, and executes the transmission condition changing process. The remaining transmission conditions corresponding to an effective resolution of 4096 pixels × 2160 pixels, a vertical frequency of 60 Hz and a color depth of 8 bits / pixel are only the combination of a transmission rate of 5.4 Gbps and the number of transmission lanes 4. The control unit 101 stores information representing this transmission condition in the RAM 132, and performs transmission condition change processing. Specifically, the control unit 101 changes the transmission condition by changing the values of the maximum transmission rate (MAX_LINK_RATE) and the maximum number of transmission lanes (MAX_LINK_COUNT) in the receiver capability field of DPCD according to the changed transmission condition. Do. In this example, the control unit 101 changes the maximum transmission rate from 8.1 Gbps to 5.4 Gbps without changing the maximum number of transmission lanes.

  In step S405, the control unit 101 performs a procedure (for example, notification using an HPD signal) re-executing link training defined in the DP standard, and urges the external device to perform link training again. Since the external device reads the receiver capability field of the DPCD and performs link training, link training in S405 is performed based on the post-change transmission condition.

  The external device reads the link / sink status field of the DPCD and determines the success or failure of link training. If it is determined that the link training has failed, the external device changes the transmission conditions according to the DP standard and performs link training again.

  Therefore, in step S406, the control unit 101 determines whether relink training has been started from the external device. If it is determined that the relink training has been started, the process returns to step S405 to execute the operation related to link training again. On the other hand, when determining that link training is successful, the external device notifies the end of link training by writing a specific value to a specific address in the link configuration field of the DPCD.

  If the link training is successful, the control unit 101 receives the idle pattern and the subsequent video data stream at S408, returns the process to S401, and determines whether the clock recovery is successful. If it is confirmed in S402 that the clock recovery is successful, the control unit 101 ends the processing (if the video is muted, this is also ended), and the processing after S109 in FIG. 2 is resumed.

  After that, when an instruction to turn off the power of the projector 100 is issued or the cable connecting the external device is disconnected and the connection with the external device is disconnected, the control unit 101 operates in the DPCD receiver capability field. Restore the maximum transmission rate and the maximum number of transmission lanes.

  Next, processing in the case where it is determined in step S403 that all conditions have been tried will be described. As described above, in the present embodiment, link training is forcibly performed from the display device, and the transmission capability of the display device is lowered to notify the external device that the transmission conditions for reducing the bandwidth are determined by the link training. Do. As a result, each time a failure such as clock recovery is detected in S401, link training is repeated so that a transmission condition of a band smaller than the current transmission condition is determined. However, it is also conceivable that normal reception can not be performed even under a transmission condition in which the required bandwidth is the minimum among the transmission conditions corresponding to the video format.

  In such a case, the control unit 101 changes the EDID in the EDID storage unit 111 in S409. Specifically, it is changed so as to notify a video format (for example, the effective resolution becomes low, the color depth becomes small, etc.) in which the transmission band becomes smaller than the present as the video format to which the display device corresponds. The control unit 101 rewrites an area (Detailed Timing Descriptor) in which timing information is included, which is included in the EDID, to a value corresponding to a video format to be tried next. Alternatively, the control unit 101 may change the video format information using a DisplayID format defined by VESA as an extended block of EDID.

  In the example of the present embodiment, S409 is executed under normal conditions even when the required bandwidth is the lowest among the transmission conditions corresponding to the video format of 4096 effective resolution × 2160 pixels, vertical frequency 60 Hz, color depth 8 bits / pixel When it was not possible to receive Therefore, the control unit 101 changes, for example, the effective resolution described in the EDID to 3840 pixels × 2160 pixels.

  When the rewriting is completed, in step S410, the control unit 101 reasserts the HDP signal to urge the external device to share the EDID again. After the EDID is shared, the control unit 101 reads out the receiver capability field of the DPCD in response to the request from the external device, and notifies the external device via AUX-CH through the video input unit 110. Here, the content of the receiver capability field of DPCD is the transmission condition tried for the video format of 4096 pixels × 2160 pixels (in this case, the maximum transmission rate is 5.4 Gbps, the maximum number of transmission lanes is 4) before reducing the effective resolution. is there. Therefore, before executing at least the reassertion of the HPD signal, the control unit 101 restores the original transmission conditions (maximum transmission rate: 8.1 Gbps, maximum number of transmission lanes: 4).

  Thereafter, link training is performed in S405, and in S408, reception of the video data stream is started under the transmission condition corresponding to the condition of the maximum resolution 3840 pixels x 2160 pixels. Here, it is assumed that the transmission rate of 8.1 Gbps and the number of transmission lanes 4 are determined. If it is determined in 2S401 and S402 that the clock recovery has succeeded, the control unit 101 resumes the processing from S109 of FIG.

  On the other hand, when it is determined that the clock recovery has failed, the control unit 101 has not tried among the transmission conditions corresponding to the video format of 3840 pixels x 2160 pixels, vertical frequency 60 Hz, color depth 8 bits / pixel in S404. Select the transmission condition of. Then, the DPCD is rewritten so that link training is performed under the selected transmission condition, and the external device is notified using the HPD signal.

  Note that, in S404, the control unit 101 may try any of the transmission rate of 5.4 Gbps, the number of transmission lanes 4, the transmission rate of 8.1 Gbps, and the number of transmission lanes 2, which are untried transmission conditions. However, in this case, the transmission condition is tried with a large number of transmission lanes. This is because there is a possibility that the display device can not notice when the external device transmits the video data stream in more lanes than the number determined by the link training.

  Thereafter, as described above, the control unit 101 sequentially changes the transmission condition to the untried transmission condition and repeatedly executes the processing after S404 until the success of the clock recovery is determined in S402.

  As described above, according to the present embodiment, when the clock recovery fails after link training, the display device side urges the external device to start (redo) link training. At this time, by lowering the transmission capacity on the display device side and notifying the external device, it is possible to increase the possibility of determining a stably receivable transmission condition in which the bandwidth is reduced in link training to be performed next. Can. As described above, by substantially controlling the transmission conditions on the display device side, even if the video data stream can not be received correctly due to, for example, the external device or the transmission path quality, the disordered display is continuously performed. It becomes possible to prevent and to return to a normal display promptly.

  If clock recovery does not succeed even if the transmission conditions are changed, when prompting the start of link training (re-doing) from the display device side to the external device, the EDID is changed to lower the display capability of the display device. Notify external devices. Therefore, in link training to be performed next, the possibility of determining a stable receivable transmission condition with a reduced bandwidth can be increased.

  In the present embodiment, the configuration for monitoring a failure in clock recovery has been described. However, as in the first embodiment, a failure in symbol lock or channel equalization may be monitored.

(Other embodiments)
The present invention supplies a program that implements one or more functions of the above-described embodiments to a system or apparatus via a network or storage medium, and one or more processors in a computer of the system or apparatus read and execute the program. Can also be realized. It can also be implemented by a circuit (eg, an ASIC) that implements one or more functions.

DESCRIPTION OF SYMBOLS 100 ... Projector, 101 ... Control part, 104 ... Liquid crystal part, 105 ... Liquid crystal drive part, 106 ... Light source, 107 ... Projection optical system, 110 ... Video input part, 111 ... EDID memory part, 116 ... Image processing part

Claims (14)

Generation means for generating a clock from a data stream received from an external device;
Extracting means for extracting symbol data from the data stream at a timing based on the clock;
An output unit that outputs a display image based on the data stream;
A detection unit that detects any failure of the bit lock of the clock by the generation unit, the symbol lock by the extraction unit, and the channel equalization for the data stream received from the external device;
Instructing means for instructing the output means to change the display image into a predetermined image in response to the detection;
A display device characterized by having.   The display according to claim 1, characterized in that the detection means detects the failure by referring to information indicating a result of the bit lock, the symbol lock, and the channel equalization. apparatus.   The display device according to claim 2, wherein the information is accessible from the external device.   The said information is DPCD (DisplayPort Configuration Data), The display apparatus of Claim 2 or Claim 3 characterized by the above-mentioned.   It is determined that the symbol lock has failed if the data stream is encoded using a symbol having a polarity, and the change in the polarity of the symbol obtained from the data stream does not satisfy a predetermined condition. The display device according to any one of claims 1 to 4, characterized in that:   The symbol lock is determined to have failed when the symbol obtained from the data stream is not a symbol used for encoding the data stream. The display device according to item 1.   The apparatus further comprises changing means for changing the transmission condition of the data stream by notifying the external device of a transmission capability lower than the current transmission condition when the failure is detected. The display apparatus of any one of Claims 1-6.   8. The apparatus according to claim 7, wherein the changing unit notifies the external device of a transmission capability lower than a current transmission condition by changing information on the display device accessible by the external device. Display device.   The display device according to claim 8, wherein the information on the display device is a Display Port Configuration Data (DPCD).   When the failure is detected, the transmission condition of the data stream is notified by notifying the external device of a video format in which the transmission band is smaller than the current one as a video format supported by the display device. The display device according to any one of claims 1 to 6, further comprising changing means for changing.   11. The apparatus according to claim 10, wherein the changing unit notifies the external device of a transmission capability lower than a current transmission condition by changing information on the display device accessible by the external device. Display device.   The display device according to claim 11, wherein the information on the display device is extended display identification data (EDID).   The display according to any one of claims 1 to 12, wherein it is determined that the channel equalization has succeeded if the bit locking for the training pattern transmitted at the adjusted level is successful. apparatus. It is a control method of a display device, and
A generation step of generating a clock from a data stream received from an external device;
Extracting symbol data from the data stream at a timing based on the clock;
An output step of outputting a display image based on the data stream;
A detection step of detecting any failure in bit lock of the clock in the generation step, symbol lock in the extraction step, and channel equalization for the data stream received from the external device;
A changing step of changing the display image output in the output step into a predetermined image in response to the detection;
A control method of a display device characterized by having.

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