CN116437070B - Terminal state detection system, method, computer equipment and storage medium - Google Patents
Terminal state detection system, method, computer equipment and storage medium Download PDFInfo
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- 206010048669 Terminal state Diseases 0.000 title claims abstract description 14
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
- H04N17/002—Diagnosis, testing or measuring for television systems or their details for television cameras
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides a terminal state detection system, a terminal state detection method, computer equipment and a storage medium, wherein the system comprises an upper computer, an image tester and a terminal to be detected; the upper computer is used for carrying out Pulse Code Modulation (PCM) on the reference image to obtain reference source code data, and sending the reference source code data to the image tester; the image tester is used for carrying out PCM pulse code modulation decoding on the reference source code data to obtain a reference image, and sending the reference image to a terminal to be detected; the terminal to be detected is used for carrying out coding processing on the reference image by utilizing a preset coding rule to obtain test source code data, and returning the test source code data to the upper computer; the upper computer is used for comparing the test source code data with the reference source code data and determining the equipment state of the terminal to be detected according to the obtained comparison result. The system is adopted to detect and determine the equipment state of the terminal.
Description
Technical Field
The present invention relates to the field of device detection, and in particular, to a system, a method, a computer device, and a storage medium for detecting a terminal state.
Background
With the development of space technology in China, high-resolution images are required to be acquired through an aerospace digital camera in the task of the aerospace field, and acquired image information is required to be processed by an intelligent image information processing terminal and then sent to a ground command post for analysis by related staff.
The inventor finds that when the intelligent image information processing terminal processes the image, when the equipment state of the terminal is abnormal, for example, equipment hardware is failed or a script of running software is abnormal, the processing terminal can not normally realize image processing; after the image is processed by the processing terminals which can not normally realize image processing, the obtained image data is wrong or is inconsistent with the actual data, so that a user or a related worker can not know the accurate image data and can not successfully finish the related aerospace task. Therefore, how to detect and determine the device status of the terminal becomes a problem to be solved.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a system, a method, a computer device and a storage medium for detecting and determining a device status of a terminal.
In a first aspect, an embodiment of the present application provides a terminal status detection system, where the system includes an upper computer, an image tester, and a terminal to be detected, where each of the image tester, the upper computer, and the terminal to be detected can perform data transmission;
the upper computer is used for carrying out Pulse Code Modulation (PCM) on the reference image to obtain reference source code data, and sending the reference source code data to the image tester;
the image tester is used for carrying out PCM pulse code modulation decoding on the reference source code data to obtain the reference image, and sending the reference image to the terminal to be detected;
the terminal to be detected is used for carrying out coding processing on the reference image by utilizing a preset coding rule to obtain test source code data, and returning the test source code data to the upper computer;
and the upper computer is used for comparing the test source code data with the reference source code data and determining the equipment state of the terminal to be detected according to the obtained comparison result.
Optionally, the image tester includes an FPGA field programmable gate array main control board, a Camera Link image output board and a PCM communication board, where the image tester is configured to perform PCM pulse code modulation decoding on the reference source code data to obtain the reference image, and when sending the reference image to the terminal to be detected, the image tester includes:
The FPGA field programmable gate array main control board is used for receiving the reference source code data sent by the upper computer and sending the reference source code data to the Camera Link image output board;
the Camera Link image output board is used for sending the reference source code data to the PCM communication board according to a Camera Link transmission protocol;
the PCM communication board is used for decoding the reference source code data according to a PCM pulse code modulation decoding rule to obtain the reference image, and transmitting the reference image to the terminal to be detected.
Optionally, the FPGA field programmable gate array main control board includes an FPGA chip, a DDR3 memory chip, and a PCIE transmission interface, where the FPGA field programmable gate array main control board is configured to receive the reference source code data sent by the upper computer, and send the reference source code data to the Camera Link image output board, and includes:
the PCIE transmission interface is configured to transmit the reference source code data from the upper computer to the FPGA chip;
the FPGA chip is used for sending the reference source code data to the DDR3 memory chip;
the DDR3 memory chip is used for storing the reference source code data and sending the reference source code data to the Camera Link image output board.
Optionally, the Camera Link image output board includes a Camera Link driving chip and an FMC connector, and the Camera Link image output board is configured to send the reference source code data to the PCM communication board according to a Camera Link transmission protocol, including:
the Camera Link driving chip is used for sending the reference source code data to the FMC connector according to a Camera Link transmission protocol;
the FMC connector is configured to send the reference source code data to the PCM communication board.
Optionally, when the upper computer is configured to compare the test source code data with the reference source code data, and determine the device state of the terminal to be detected according to the obtained comparison result, the upper computer is specifically configured to:
judging whether the test source code data and the reference source code data are the same or not;
and if the test source code data and the reference source code data are the same, determining the equipment state of the terminal to be detected as normal.
Optionally, after the upper computer is configured to determine whether the test source code data and the reference source code data are the same, the upper computer is further configured to:
if the test source code data and the reference source code data are different, determining the equipment state of the terminal to be detected as abnormal.
Optionally, after the upper computer is configured to compare the test source code data with the reference source code data, and determine the device state of the terminal to be detected according to the obtained comparison result, the upper computer is further configured to:
and displaying the reference image and/or the equipment state of the terminal to be detected in a display screen of the terminal to be detected.
In a second aspect, an embodiment of the present application provides a terminal status detection method, applied to a terminal status detection system, where the system includes an upper computer, an image tester, and a terminal to be detected, where each of the image tester, the upper computer, and the terminal to be detected is capable of performing data transmission, and the method includes;
the upper computer carries out Pulse Code Modulation (PCM) on the reference image to obtain reference source code data, and sends the reference source code data to the image tester;
the image tester carries out PCM pulse code modulation decoding on the reference source code data to obtain the reference image, and sends the reference image to the terminal to be detected;
the terminal to be detected utilizes a pre-configured coding rule to code the reference image to obtain test source code data, and returns the test source code data to the upper computer;
And the upper computer compares the test source code data with the reference source code data, and determines the equipment state of the terminal to be detected according to the obtained comparison result.
Optionally, the image tester includes an FPGA field programmable gate array main control board, a Camera Link image output board and a PCM communication board, and the image tester performs PCM pulse code modulation decoding on the reference source code data to obtain the reference image, and sends the reference image to the terminal to be detected, including:
the FPGA field programmable gate array main control board receives the reference source code data sent by the upper computer and sends the reference source code data to the Camera Link image output board;
the Camera Link image output board sends the reference source code data to the PCM communication board according to a Camera Link transmission protocol;
and the PCM communication board decodes the reference source code data according to a PCM pulse code modulation decoding rule to obtain the reference image, and sends the reference image to the terminal to be detected.
Optionally, the FPGA field programmable gate array main control board includes an FPGA chip, a DDR3 memory chip, and a PCIE transmission interface, where the FPGA field programmable gate array main control board receives the reference source code data sent by the upper computer, and sends the reference source code data to the Camera Link image output board, and includes:
The PCIE transmission interface transmits the reference source code data from the upper computer to the FPGA chip;
the FPGA chip sends the reference source code data to the DDR3 memory chip;
and the DDR3 memory chip stores the reference source code data and sends the reference source code data to the Camera Link image output board.
Optionally, the Camera Link image output board includes a Camera Link driving chip and an FMC connector, and the Camera Link image output board sends the reference source code data to the PCM communication board according to a Camera Link transmission protocol, including:
the Camera Link driving chip sends the reference source code data to the FMC connector according to a Camera Link transmission protocol;
the FMC connector sends the reference source code data to the PCM communication board.
Optionally, the upper computer compares the test source code data with the reference source code data, and determines the device state of the terminal to be detected according to the obtained comparison result, including:
the upper computer judges whether the test source code data and the reference source code data are the same or not;
and if the test source code data and the reference source code data are the same, the upper computer determines the equipment state of the terminal to be detected as normal.
Optionally, after the upper computer determines whether the test source code data and the reference source code data are the same, the method further includes:
if the test source code data and the reference source code data are different, the upper computer determines the equipment state of the terminal to be detected as abnormal.
Optionally, after the upper computer compares the test source code data with the reference source code data and determines the device state of the terminal to be detected according to the obtained comparison result, the method further includes:
and the upper computer displays the reference image and/or the equipment state of the terminal to be detected in a display screen of the upper computer.
In a third aspect, embodiments of the present application provide a computer device, including: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating over the bus when the computer device is running, the machine-readable instructions when executed by the processor performing the steps of the terminal state detection method of any of the alternative embodiments of the second aspect described above.
In a fourth aspect, embodiments of the present application provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method for detecting a terminal status described in any of the optional embodiments of the second aspect.
The technical scheme provided by the application comprises the following beneficial effects:
the upper computer is used for carrying out Pulse Code Modulation (PCM) on the reference image to obtain reference source code data, and sending the reference source code data to the image tester; by the device, the source code data used for reference when the state of the terminal to be detected is detected can be obtained.
The image tester is used for carrying out PCM pulse code modulation decoding on the reference source code data to obtain the reference image, and sending the reference image to the terminal to be detected; the terminal to be detected is used for carrying out coding processing on the reference image by utilizing a preset coding rule to obtain test source code data, and returning the test source code data to the upper computer; through the two devices, the test source code data for judging the device state of the terminal to be detected after the terminal to be detected performs image processing can be obtained.
The upper computer is used for comparing the test source code data with the reference source code data and determining the equipment state of the terminal to be detected according to the obtained comparison result; by the device, the device state of the terminal to be detected can be determined according to the comparison result of the actual source code data of the reference image and the test source code data obtained after the reference image is processed by the terminal to be detected.
By adopting the system, the test source code data obtained after the reference image is processed by the terminal to be detected is compared with the reference source code data serving as the detection basis in the upper computer through the mutual matching of the upper computer, the image tester and the terminal to be detected, and the equipment state of the terminal to be detected is determined according to the comparison result, so that the equipment state of the terminal is detected and determined.
In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a terminal status detection system according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a second terminal status detection system according to a first embodiment of the present invention;
Fig. 3 is a schematic structural diagram of a third terminal status detection system according to a first embodiment of the present invention;
fig. 4 is a schematic structural diagram of a fourth terminal status detection system according to a first embodiment of the present invention;
fig. 5 shows a flowchart of a method for detecting a terminal status according to a second embodiment of the present invention;
fig. 6 shows a schematic structural diagram of a computer device according to a third embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
Example 1
For the convenience of understanding the present application, the following describes the first embodiment of the present application in detail with reference to the schematic structural diagram of the first embodiment of the present invention shown in fig. 1.
Referring to fig. 1, fig. 1 shows a schematic structural diagram of a terminal status detection system according to an embodiment of the present invention, where the system includes an upper computer 100, an image tester 200, and a terminal to be detected 300, and each of the image tester, the upper computer, and the terminal to be detected can perform data transmission.
Specifically, the terminal to be detected is arranged in the spacecraft, the upper computer and the image tester are arranged in the ground detection station, and any two of the upper computer, the image tester and the terminal to be detected realize communication connection.
The upper computer is used for carrying out Pulse Code Modulation (PCM) on the reference image to obtain reference source code data, and sending the reference source code data to the image tester.
Specifically, PCM (Pulse Code Modulation ) codes are capable of sampling analog signals such as voice and image signals at regular intervals to discretize them, rounding and quantizing the sampled values in hierarchical units, and representing the amplitudes of the sampled pulses in a set of binary codes.
The upper computer can obtain the reference source code data by the following two methods:
the method comprises the following steps: and carrying out Pulse Code Modulation (PCM) coding on the reference image to obtain reference source code data.
The second method is as follows: the reference source code data is received from a third party device or system or is directly entered by the user.
The image tester is used for carrying out PCM pulse code modulation decoding on the reference source code data to obtain the reference image, and sending the reference image to the terminal to be detected.
Specifically, the image tester performs PCM decoding and restoring on the reference source code data to obtain a reference image, and sends the reference image to the terminal to be detected.
And the terminal to be detected is used for carrying out coding processing on the reference image by utilizing a preset coding rule to obtain test source code data, and returning the test source code data to the upper computer.
Specifically, a coding rule is pre-configured in the terminal to be detected, and after the terminal to be detected receives the reference image, the terminal to be detected encodes the reference image by utilizing the pre-configured coding rule to obtain test source code data.
And the upper computer is used for comparing the test source code data with the reference source code data and determining the equipment state of the terminal to be detected according to the obtained comparison result.
Specifically, the upper computer performs data comparison on the test source code data and the reference source code data, and because the reference source code data is the real source code data of the reference image, the test source code data is the source code data obtained after the terminal to be detected encodes the reference image, and whether the encoding rule contained in the terminal to be detected is correct or effective can be determined according to the comparison result of the data comparison between the test source code data and the reference source code data.
In a possible implementation manner, referring to fig. 2, fig. 2 shows a schematic structural diagram of a second terminal status detection system according to an embodiment of the present invention, where the image tester 200 includes an FPGA field programmable gate array main control board 210, a Camera Link image output board 220, and a PCM communication board 230, and the image tester is configured to perform PCM pulse code modulation decoding on the reference source code data to obtain the reference image, and send the reference image to the terminal to be detected, where the method includes:
the FPGA field programmable gate array main control board is used for receiving the reference source code data sent by the upper computer and sending the reference source code data to the Camera Link image output board.
Specifically, an FPGA (Field Programmable Gate Array ) main control board is used as a data transmission medium to receive reference source code data sent by an upper computer, and then the reference source code data is sent to a Camera Link image output board.
The Camera Link image output board is used for sending the reference source code data to the PCM communication board according to a Camera Link transmission protocol.
Specifically, the Camera Link is an interface between a digital Camera and an image acquisition card, and adopts uniform physical connector and cable definition, so that the Camera and the image card which meet the Camera Link standard can be physically interconnected; the Camera Link image output board sends the reference source code data to the PCM communication board through a Camera Link transmission protocol.
The PCM communication board is used for decoding the reference source code data according to a PCM pulse code modulation decoding rule to obtain the reference image, and transmitting the reference image to the terminal to be detected.
Specifically, the PCM communication board decodes the reference source code data according to PCM pulse code modulation decoding rules to obtain the reference image, and then sends the reference image to the terminal to be detected.
In the design of a PCM communication unit, a test board needs to receive PCM data sent by an intelligent terminal and record working condition information thereof, and interfaces all adopt an RS485 (serial communication standard) standard. The RS485 interface is a preferred serial interface because of the advantages of strong noise interference resistance, long transmission distance, multi-station capability and the like. The RS485 interface is composed of a half-duplex network, only two connecting wires are needed, and the RS485 interface adopts shielding twisted pair transmission. The MAX3062 chip is used for connecting with the intelligent terminal. MAX3062 is used for RS485 communication, and a hot plug circuit is added at the AB terminal of the MAX3062 chip according to the chip manual example circuit to eliminate data failures generated during insertion. The MAX3062 driver has no slew rate limit and allows transmission speeds up to 20Mbps. RO is the output interface, DI is the input interface, VCC is 5V power supply voltage, with 100nF condenser bypass ground, send circuit RE, send circuit DE add pull-up resistance, receive circuit RE, receive circuit DE add pull-down resistance, prevent that random data that send will influence the bus.
In a possible implementation manner, referring to fig. 3, fig. 3 shows a schematic structural diagram of a third terminal status detection system according to an embodiment of the present invention, where the FPGA field programmable gate array main control board 210 includes an FPGA chip 211, a DDR3 memory chip 212, and a PCIE transmission interface 213, and the FPGA field programmable gate array main control board is configured to receive the reference source code data sent by the upper computer and send the reference source code data to the Camera Link image output board, and includes:
And the PCIE transmission interface is used for transmitting the reference source code data from the upper computer to the FPGA chip.
Specifically, a PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) transmission interface is used as a data outgoing interface to transmit the reference source code data from the upper computer to the FPGA chip.
The FPGA chip is used for sending the reference source code Data to the DDR3 (Double-Data-Rate 3Synchronous Dynamic RAM, third generation Double-Rate synchronous dynamic random access memory) memory chip.
Specifically, the FPGA chip sends the reference source code data to the DDR3 memory chip.
The DDR3 memory chip is used for storing the reference source code data and sending the reference source code data to the Camera Link image output board.
Specifically, the DDR3 memory chip stores the reference source code data, and then sends the reference source code data to the Camera Link image output board.
In a possible implementation manner, referring to fig. 4, fig. 4 shows a schematic structural diagram of a fourth terminal status detection system according to an embodiment of the present invention, where the Camera Link image output board 220 includes a Camera Link driving chip 221 and an FMC connector 222, and the Camera Link image output board is configured to send the reference source code data to the PCM communication board according to a Camera Link transmission protocol, and includes:
The Camera Link driving chip is used for sending the reference source code data to the FMC connector according to a Camera Link transmission protocol.
Specifically, an FMC (FPGA Mezzanine Card, FPGA intermediate laminate card) connector is an important component of the FMC, which connects pins provided by the FPGA with an I/O (Input/Output) interface of the FMC daughter board, enabling data transfer.
The FMC connector is configured to send the reference source code data to the PCM communication board.
The circuit part of the Camera Link image output board mainly comprises a serial communication unit, a control signal unit and an image data driving unit, wherein in order to protect an FPGA chip, a voltage logic isolation unit is added in the Camera Link video image signal output board (DS 90CR287 chip in an analog source system is directly connected with an I/O pin of the FPGA through an FMC connector in the Camera Link video image signal output board).
In the circuit design of the serial communication unit, the serial communication unit is mainly responsible for serial communication between the industrial camera and the image acquisition system, and the unit is designed by the analog source system design of the present time. The serial communication signal SerTFG is a communication signal output to the image acquisition system end by the tester system end, the SerTC is a communication signal output to the tester system by the image acquisition card, the serial communication signal is transmitted by adopting an LVDS ((Low-Voltage Differential Signaling, low-voltage differential signal) differential pair mode, and is transmitted by an SDR26 connector, a control signal unit circuit is designed, an industrial Camera of a Camera Link interface can be provided with 4 Camera control signals which are respectively CC1, CC2, CC3 and CC4, in order to ensure the accuracy of remote transmission and reduce electronic interference, the 4 control signals are also transmitted in an LVDS differential pair mode and are also connected to an SDR26 connector, so that the 4 Camera control signals are also reserved in the design of the tester system, and the LVDS control signals are only input to the tester in an LVDS mode, so that the LVDS is required to be converted into a drive chip of the TTL signal, the 3.3V power supply is adopted, and the power supply pins are required to be additionally provided with three parallel capacitors which are respectively provided with LVDS 90LV032, LVDS 0.001, uF 0.0.001, and uF 0.0.0 ohm can be converted into a differential signal, and a full LVDS signal can be input to each of the LVDS terminals.
In the circuit design of the image data driving unit, the video output interface of the Camera Link standard outputs the image data in the form of LVDS low voltage differential signals, and the IO pin of the FPGA chip outputs TTL signals, so the system adopts the image data driving circuit to convert the TTL signals into LVDS signals; the design introduced above, this section would use DS90CR287 chip as the Camera Link drive transmitter; the 0CR287 chip can serialize 28-bit single-ended parallel image data and 1-bit single-ended clock signals and then divide the data into 4 LVDS data streams and 1 LVDS clock stream. The DS90CR287 chip can be powered by a 3.3V power supply, has lower power consumption, and has a working frequency range of 20MHz to 85MHz and a maximum throughput of 2.38Gbps. In DS90CR287 circuit design, each power pin of a chip is according to its chip manual: VCC, PLLVCC, LVDS VCC all need have three decoupling capacitance of parallelly connected, and the capacitance is respectively: 0.1uF, 0.01uF, 0.001uF. The PCB is designed with a power plane for both power and ground, and each decoupling capacitor has an independent via to the substrate. Meanwhile, each LVDS differential pair of the DS90CR287 output end is connected with a 100 ohm matching resistor in a bridging mode, and matching processing is carried out on LVDS signal lines. As the operating frequency of DS90CR287 can reach 85MHz, the input TTL signal frequency is 85MHz, the LVDS differential pair frequency of the output end reaches 595MHz, and the chip set is an ideal method for solving the problems of EMI and cable size related to a wide high-speed TTL interface.
In the circuit design of the voltage logic isolation unit, a DS90CR287 chip in an analog source system is directly connected with an I/O pin of an FPGA through an FMC connector in a Camera Link video image signal output board, in order to protect the FPGA chip, the voltage logic isolation unit is added in the Camera Link video image signal output board, and an I/O input/output signal of the FPGA is connected with the DS90CR287 chip through the unit. The design of the unit adopts an SN74AVC16T245 and a 16-bit bidirectional transmission level converter, the working voltage range is 1.2V to 3.6V, and the maximum working frequency reaches 380MHz.
In a possible implementation manner, when the upper computer is configured to compare the test source code data with the reference source code data, and determine the device state of the terminal to be detected according to the obtained comparison result, the upper computer is specifically configured to:
and judging whether the test source code data and the reference source code data are the same or not.
And if the test source code data and the reference source code data are the same, determining the equipment state of the terminal to be detected as normal.
Specifically, since the reference source code data is actual source code data of the reference image, and the test source code data is source code data obtained by encoding the reference image by the terminal to be detected, after comparison, if the test source code data is the same as the reference source code data, it indicates that the encoding process of the terminal to be detected is normal, and the built-in encoding rule and the like are also normal, and then the device state of the terminal to be detected can be determined to be normal.
In a possible implementation manner, after the host computer is used for judging whether the test source code data and the reference source code data are the same, the host computer is further used for:
if the test source code data and the reference source code data are different, determining the equipment state of the terminal to be detected as abnormal.
Specifically, if the test source code data and the reference source code data are different, it is indicated that the coding process of the terminal to be detected may be abnormal, and the built-in coding rule may be invalid, and the device state of the terminal to be detected may be determined to be abnormal.
In a possible implementation manner, after the upper computer is configured to compare the test source code data with the reference source code data, and determine the device state of the terminal to be detected according to the obtained comparison result, the upper computer is further configured to:
and displaying the reference image and/or the equipment state of the terminal to be detected in a display screen of the terminal to be detected.
Specifically, the upper computer displays the reference image and/or the device state of the terminal to be detected in the display screen thereof, so that a user can know the device state of the terminal to be detected from the display screen of the upper computer.
The effective pixels of the reference image are 2560 x 720, and the acquired picture is 40 frames/second, and 24-bit image data.
Example two
Referring to fig. 5, fig. 5 shows a flowchart of a terminal status detection method provided by a second embodiment of the present invention, where the method is applied to a terminal status detection system, where the system includes an upper computer, an image tester, and a terminal to be detected, and each of the image tester, the upper computer, and the terminal to be detected is capable of performing data transmission, and the method includes steps S501 to S504:
s501: the upper computer carries out Pulse Code Modulation (PCM) on the reference image to obtain reference source code data, and sends the reference source code data to the image tester;
s502: the image tester carries out PCM pulse code modulation decoding on the reference source code data to obtain the reference image, and sends the reference image to the terminal to be detected;
s503: the terminal to be detected utilizes a pre-configured coding rule to code the reference image to obtain test source code data, and returns the test source code data to the upper computer;
s504: and the upper computer compares the test source code data with the reference source code data, and determines the equipment state of the terminal to be detected according to the obtained comparison result.
In a possible implementation manner, the image tester includes an FPGA field programmable gate array main control board, a Camera Link image output board and a PCM communication board, performs PCM pulse code modulation decoding on the reference source code data to obtain the reference image, and sends the reference image to the terminal to be detected, including:
the FPGA field programmable gate array main control board receives the reference source code data sent by the upper computer and sends the reference source code data to the Camera Link image output board;
the Camera Link image output board sends the reference source code data to the PCM communication board according to a Camera Link transmission protocol;
and the PCM communication board decodes the reference source code data according to a PCM pulse code modulation decoding rule to obtain the reference image, and sends the reference image to the terminal to be detected.
In a possible implementation manner, the FPGA field programmable gate array main control board includes an FPGA chip, a DDR3 memory chip and a PCIE transmission interface, and the FPGA field programmable gate array main control board receives the reference source code data sent by the upper computer and sends the reference source code data to the Camera Link image output board, including:
The PCIE transmission interface transmits the reference source code data from the upper computer to the FPGA chip;
the FPGA chip sends the reference source code data to the DDR3 memory chip;
and the DDR3 memory chip stores the reference source code data and sends the reference source code data to the Camera Link image output board.
In one possible embodiment, the Camera Link image output board includes a Camera Link driver chip and an FMC connector, and the Camera Link image output board transmits the reference source code data to the PCM communication board according to a Camera Link transmission protocol, including:
the Camera Link driving chip sends the reference source code data to the FMC connector according to a Camera Link transmission protocol;
the FMC connector sends the reference source code data to the PCM communication board.
In a possible implementation manner, the upper computer compares the test source code data with the reference source code data, and determines the device state of the terminal to be detected according to the obtained comparison result, including:
the upper computer judges whether the test source code data and the reference source code data are the same or not;
And if the test source code data and the reference source code data are the same, the upper computer determines the equipment state of the terminal to be detected as normal.
In a possible implementation manner, after the upper computer determines whether the test source code data and the reference source code data are the same, the method further includes:
if the test source code data and the reference source code data are different, the upper computer determines the equipment state of the terminal to be detected as abnormal.
In a possible implementation manner, after the host computer compares the test source code data with the reference source code data and determines the device state of the terminal to be detected according to the obtained comparison result, the method further includes:
and the upper computer displays the reference image and/or the equipment state of the terminal to be detected in a display screen of the upper computer.
Example III
Based on the same application concept, referring to fig. 6, fig. 6 shows a schematic structural diagram of a computer device provided in a third embodiment of the present invention, where, as shown in fig. 6, a computer device 600 provided in the third embodiment of the present invention includes:
the terminal state detection method comprises a processor 601, a memory 602 and a bus 603, wherein the memory 602 stores machine-readable instructions executable by the processor 601, when the computer device 600 is running, the processor 601 and the memory 602 communicate through the bus 603, and the machine-readable instructions are executed by the processor 601 to perform the steps of the terminal state detection method described in the second embodiment.
Example IV
Based on the same application concept, the embodiment of the present invention further provides a computer readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the terminal state detection method in any one of the above embodiments are performed.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again.
The computer program product for detecting the terminal state provided by the embodiment of the invention comprises a computer readable storage medium storing program codes, wherein the instructions included in the program codes can be used for executing the method described in the foregoing method embodiment, and specific implementation can be referred to the method embodiment and will not be repeated here.
The terminal state detection system provided by the embodiment of the invention can be specific hardware on equipment or software or firmware installed on the equipment. The system provided by the embodiment of the present invention has the same implementation principle and technical effects as those of the foregoing method embodiment, and for the sake of brevity, reference may be made to the corresponding content in the foregoing method embodiment where the system embodiment is not mentioned. It will be clear to those skilled in the art that, for convenience and brevity, the specific operation of the system, apparatus and unit described above may refer to the corresponding process in the above method embodiment, which is not described in detail herein.
In the embodiments provided herein, it should be understood that the disclosed systems and methods may be implemented in other ways. The system embodiments described above are merely illustrative, e.g., the division of the elements is merely a logical functional division, and there may be additional divisions in actual implementation, and e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments provided in the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
It should be noted that: like reference numerals and letters in the following figures denote like items, and thus once an item is defined in one figure, no further definition or explanation of it is required in the following figures, and furthermore, the terms "first," "second," "third," etc. are used merely to distinguish one description from another and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above examples are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, but it should be understood by those skilled in the art that the present invention is not limited thereto, and that the present invention is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the corresponding technical solutions. Are intended to be encompassed within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. The system is characterized by comprising an upper computer, an image tester and a terminal to be detected, wherein each of the image tester, the upper computer and the terminal to be detected can perform data transmission;
The upper computer is used for carrying out Pulse Code Modulation (PCM) on the reference image to obtain reference source code data, and sending the reference source code data to the image tester;
the image tester is used for carrying out PCM pulse code modulation decoding on the reference source code data to obtain the reference image, and sending the reference image to the terminal to be detected;
the terminal to be detected is used for carrying out coding processing on the reference image by utilizing a preset coding rule to obtain test source code data, and returning the test source code data to the upper computer;
the upper computer is used for comparing the test source code data with the reference source code data and determining the equipment state of the terminal to be detected according to the obtained comparison result;
the image tester comprises an FPGA field programmable gate array main control board, a Camera Link image output board and a PCM communication board, and is used for carrying out PCM pulse code modulation and decoding on the reference source code data to obtain the reference image, and when the reference image is sent to the terminal to be detected, the image tester comprises:
the FPGA field programmable gate array main control board is used for receiving the reference source code data sent by the upper computer and sending the reference source code data to the Camera Link image output board;
The Camera Link image output board is used for sending the reference source code data to the PCM communication board according to a Camera Link transmission protocol;
the PCM communication board is used for decoding the reference source code data according to a PCM pulse code modulation decoding rule to obtain the reference image, and transmitting the reference image to the terminal to be detected.
2. The system of claim 1, wherein the FPGA field programmable gate array master control board comprises an FPGA chip, a DDR3 memory chip, and a PCIE transmission interface, the FPGA field programmable gate array master control board is configured to receive the reference source code data sent by the upper computer, and send the reference source code data to the Camera Link image output board, and comprises:
the PCIE transmission interface is configured to transmit the reference source code data from the upper computer to the FPGA chip;
the FPGA chip is used for sending the reference source code data to the DDR3 memory chip;
the DDR3 memory chip is used for storing the reference source code data and sending the reference source code data to the Camera Link image output board.
3. The system of claim 1, wherein the Camera Link image output board includes a Camera Link driver chip and an FMC connector, the Camera Link image output board for transmitting the reference source code data to the PCM communication board according to a Camera Link transmission protocol, comprising:
The Camera Link driving chip is used for sending the reference source code data to the FMC connector according to a Camera Link transmission protocol;
the FMC connector is configured to send the reference source code data to the PCM communication board.
4. The system of claim 1, wherein the upper computer is configured to, when comparing the test source code data with the reference source code data, determine the device state of the terminal to be detected according to the obtained comparison result, specifically:
judging whether the test source code data and the reference source code data are the same or not;
and if the test source code data and the reference source code data are the same, determining the equipment state of the terminal to be detected as normal.
5. The system of claim 4, wherein the upper computer, after being configured to determine whether the test source code data and the reference source code data are identical, is further configured to:
if the test source code data and the reference source code data are different, determining the equipment state of the terminal to be detected as abnormal.
6. The system of claim 1, wherein the upper computer is further configured to, after comparing the test source code data with the reference source code data and determining the device state of the terminal to be detected according to the obtained comparison result:
And displaying the reference image and/or the equipment state of the terminal to be detected in a display screen of the terminal to be detected.
7. The terminal state detection method is characterized by being applied to a terminal state detection system, wherein the system comprises an upper computer, an image tester and a terminal to be detected, and each two of the image tester, the upper computer and the terminal to be detected can carry out data transmission;
the upper computer carries out Pulse Code Modulation (PCM) on the reference image to obtain reference source code data, and sends the reference source code data to the image tester;
the image tester carries out PCM pulse code modulation decoding on the reference source code data to obtain the reference image, and sends the reference image to the terminal to be detected;
the terminal to be detected utilizes a pre-configured coding rule to code the reference image to obtain test source code data, and returns the test source code data to the upper computer;
the upper computer compares the test source code data with the reference source code data, and determines the equipment state of the terminal to be detected according to the obtained comparison result;
The image tester comprises an FPGA field programmable gate array main control board, a Camera Link image output board and a PCM communication board, the image tester carries out PCM pulse code modulation and decoding on the reference source code data to obtain the reference image, and sends the reference image to the terminal to be detected, and the image tester comprises:
the FPGA field programmable gate array main control board receives the reference source code data sent by the upper computer and sends the reference source code data to the Camera Link image output board;
the Camera Link image output board sends the reference source code data to the PCM communication board according to a Camera Link transmission protocol;
and the PCM communication board decodes the reference source code data according to a PCM pulse code modulation decoding rule to obtain the reference image, and sends the reference image to the terminal to be detected.
8. A computer device, comprising: a processor, a memory and a bus, said memory storing machine-readable instructions executable by said processor, said processor and said memory communicating over the bus when the computer device is running, said machine-readable instructions when executed by said processor performing the steps of the terminal state detection method according to claim 7.
9. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps of the terminal status detection method according to claim 7.
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