CN117060916A - Programmable gate array based on three-dimensional writable memory - Google Patents
Programmable gate array based on three-dimensional writable memory Download PDFInfo
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- 238000007620 mathematical function Methods 0.000 claims abstract description 42
- 238000004364 calculation method Methods 0.000 claims abstract description 9
- 238000003860 storage Methods 0.000 claims description 10
- 230000006870 function Effects 0.000 claims description 9
- 239000000758 substrate Substances 0.000 description 22
- 238000003491 array Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- -1 tiO 2 ) Diodes Chemical class 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
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- Logic Circuits (AREA)
Abstract
The application provides a programmable gate array, and the chips in the same batch can realize different mathematical functions. The programmable gate array contains a plurality of programmable connections and a plurality of programmable compute units. Each programmable compute unit contains at least one memory array that stores a look-up table (LUT) of mathematical functions. In the setting stage, the LUT of the mathematical function is loaded into the memory array according to the requirement of a user; in the calculation phase, the values of the mathematical function are obtained by looking up the LUT.
Description
The application relates to a division application of Chinese patent application with application number of 201710126067.3, application date of 2017, 3, 6 and the name of 'programmable gate array based on three-dimensional writable memory'.
Technical Field
The present application relates to the field of integrated circuits, and more particularly to programmable gate arrays.
Background
The programmable gate array belongs to a semi-custom integrated circuit, namely, the customization of a logic circuit is realized through a back-end process or field programming. U.S. Pat. No. 4,870,302 discloses a programmable gate array. It contains a plurality of programmable logic units (configurable logic element, or configurable logic block) and programmable connections (configurable interconnect, or programmable interconnect). The programmable logic unit can selectively realize functions of shift, logical negation, AND (logical AND), OR (logical AND), NOR (AND), NAND (NAND), XOR (exclusive OR), plus (arithmetic addition), minus (arithmetic subtraction) AND the like under the control of a setting signal; the programmable connection can selectively realize the functions of connection, disconnection and the like between the two interconnection lines under the control of the setting signal.
Currently, many applications involve the computation of complex mathematical functions. To guarantee execution speed, high performance applications require hardware to implement complex mathematical functions. In existing programmable gate arrays, complex mathematical functions are implemented by solidifying the computational units. These cure computation units are part of a hard core (hard block) whose circuitry has been cured and cannot be reconfigured. It is clear that the curing calculation unit will limit further applications of the programmable gate array. To overcome this difficulty, the present application generalizes the concept of programmable gates to make the solidification computation unit programmable. Specifically, the programmable gate circuit includes a programmable computing unit in addition to the programmable logic unit. The programmable computing unit may selectively implement any of a variety of mathematical functions.
Disclosure of Invention
The application mainly aims to popularize the application of the programmable gate circuit in the field of complex mathematical computation.
It is a further object of the application to provide a programmable gate whose logic functions can be customized as well as whose computing functions.
It is a further object of this application to provide a programmable gate array that is more computationally flexible and powerful.
It is another object of the present application to provide a programmable gate array with a smaller chip area and lower cost.
To achieve these and other objects, the present application proposes a programmable gate array based on a three-dimensional writable memory (three-dimensional writable memory, abbreviated as 3D-W). It comprises a programmable computing unit array, a programmable logic unit array and a plurality of programmable connections. Each programmable computing unit contains at least one 3D-W array that stores a look-up table (LUT) of mathematical functions. The use of programmable computing units is divided into two phases: a setup phase and a calculation phase. In the setting stage, the LUT of the needed mathematical function is loaded into the 3D-W array according to the user requirement; in the calculation phase, the values of the basic mathematical functions are obtained by looking up the LUT. Due to the adoption of the 3D-W array, different mathematical functions can be realized even for the same batch of chips. Moreover, for a programmable gate array based on a three-dimensional multiple-time-to-multiple-program memory (3D-MTP) array, the programmable gate array can implement reconfigurable computation because LUTs of different mathematical functions can be loaded to the 3D-MTP array at different time periods. In the present application, complex mathematical functions refer to mathematical functions other than arithmetic addition (+) and arithmetic subtraction (-) including transcendental functions, multivariate functions, and the like.
In addition to programmable compute units, a programmable gate array also contains a plurality of programmable logic units and programmable connections. In an implementation, a complex mathematical function is first decomposed into a plurality of basic mathematical functions. Then, a corresponding programmable computing unit is set for each basic mathematical function to realize the corresponding basic mathematical function. Finally, by setting programmable logic units and programmable connections, the required complex mathematical functions are realized.
There are many advantages to using 3D-W to implement a programmable gate array. First, since 3D-W has a large memory capacity, it can store a large LUT. Secondly, three-dimensional integration can be realized between the 3D-W arrays, so that the 3D-W arrays belonging to different programmable computing units can be mutually stacked to reduce the substrate area required by the programmable gate array. Finally, since the 3D-W array does not substantially occupy substrate area, programmable logic units and/or programmable connections can be integrated under the 3D-W array, which can further reduce the substrate area required by the programmable gate array.
Accordingly, the application proposes a programmable computing unit (100) characterized by comprising: a semiconductor substrate (0) containing transistors; a three-dimensional writable memory (3D-W) array (110) stacked on the semiconductor substrate (0), the 3D-W array (110) storing at least part of a look-up table (LUT) of a mathematical function; a set signal (125) for writing a value of a mathematical function to the 3D-W array (110) when the set signal (125) is "write"; when the set signal (125) is "read", the value of the mathematical function is read from the 3D-W array (110).
The application also proposes a programmable gate array (400) implementing a complex mathematical function, characterized by comprising: a programmable computing unit array (100 AA-100 AD) comprising at least one programmable computing unit (100), the programmable computing unit (100) comprising a three-dimensional writable memory (3D-W) array (110) and storing at least part of a look-up table (LUT) of a basic mathematical function; a programmable logic cell array (200 AA-200 AD) comprising at least one programmable logic cell (200) that selectively implements a logic operation from a logic operation library; a plurality of programmable connections (300) coupling the array of programmable compute units and the array of programmable logic units; the programmable gate array (400) implements the complex mathematical function, which is a combination of the basic mathematical functions, by programming the programmable computational units (100 AA-100 AD), the programmable logic units (200 AA-200 AD), and the programmable connections (300).
Drawings
FIG. 1 is a cross-sectional view of a three-dimensional writable memory (3D-W).
Fig. 2 is a symbol of a programmable computing unit.
Fig. 3 is a substrate circuit layout diagram of a first programmable computing unit.
Fig. 4 is a layout diagram of a programmable gate array.
Fig. 5 shows two periods of use of a reconfigurable gate array.
FIG. 6A discloses a connection library for a programmable connection implementation; fig. 6B discloses a logic operation library of a programmable logic cell implementation.
FIG. 7A is a substrate circuit layout of a second programmable computing unit; fig. 7B is a cross-sectional view of the programmable computing units 100AA-100AD of fig. 4.
Fig. 8 is a layout diagram of a programmable gate array implementation.
It is noted that these figures are merely schematic and they are not drawn to scale. Some of the dimensions and structures in the figures may be exaggerated or reduced for clarity and convenience. The same reference numerals generally designate corresponding or similar structures in different embodiments.
Description of the embodiments
FIG. 1 is a cross-sectional view of a three-dimensional writable memory (3D-W). 3D-W is one of three-dimensional memories (3D-M), and the stored information is recorded in an electrical programming mode. The 3D-W is further classified into a three-dimensional one-time programmable memory (3D-OTP) and a three-dimensional multiple-time programmable memory (3D-MTP) according to the number of times it can be programmed. Wherein, 3D-OTP can be programmed once, and 3D-MTP can be reprogrammed. Common 3D-Ws include 3D-XPoint (three-dimensional cross point array memory), 3D-RRAM (three-dimensional impedance memory), 3D-memristor, 3D-OTP (three-dimensional one time programmable memory), and the like.
3D-W10 contains a substrate circuit layer 0K formed on substrate 0. The memory layer 16A is stacked over the substrate circuit 0K, and the memory layer 16B is stacked over the memory layer 16A. The substrate circuit layer 0K contains the peripheral circuitry of the memory layers 16A, 16B, including the transistor 0t and its interconnect lines 0i (including 0M1-0M 2). Wherein the transistor 0t is formed in a semiconductor substrate 0; interconnect line 0i contains interconnect line layers 0M1-0M3. Each memory layer (e.g., 16A) contains a plurality of first address lines (e.g., 2a, along the y-direction), a plurality of second address lines (e.g., 1a, along the x-direction), and a plurality of 3D-P memory cells (e.g., 1 aa). The memory layers 16A, 16B are coupled to the substrate 0 through the contact via holes 1av, 3av, respectively.
In one 3D-W, each storage layer contains multiple 3D-W arrays. A 3D-W array is a set of all memory cells in one memory layer that share at least one address line. In one 3D-W array, all address lines are contiguous and do not share any address lines with a different 3D-W array. In addition, one 3D-W chip contains a plurality of 3D-W modules. Each 3D-W module comprises all the memory layers in the 3D-W, the top memory layer of which contains only one 3D-W array, and the projection of this 3D-W array onto the substrate determines the boundaries of the 3D-W module.
The 3D-W memory cell 1aa contains a programming film 12 and a diode film 14. The programming film 12 may be an antifuse film for 3D-OTP; other multiple programming films are also possible for 3D-MTP. The diode film 14 has the following broad features: at the read voltage, its resistance is small; when the applied voltage is smaller than the read voltage or opposite to the read voltage, the resistance is larger. The diode film may be a P-i-N diode, or a metal oxide (e.g., tiO 2 ) Diodes, etc.
Fig. 2 is a symbol of a programmable computing unit 100. The input terminal IN thereof includes input data 115, the output terminal OUT includes output data 135, and the set terminal CFG includes a set signal 125. When the setting signal 125 is "write", the LUT of the required basic mathematical function is written in the programmable computing unit 100. When the set signal 125 is "read", the values in the LUT are read out from the programmable computing unit 100.
Fig. 3 is a layout diagram of a substrate circuit 0K of the first programmable computing unit 100. Since the 3D-W array is stacked above the substrate circuit 0K, not in the substrate, only the projection of the 3D-W array onto the substrate 0 is indicated by a dotted line. In this embodiment, the LUT is stored in at least one 3D-W array 110. Substrate circuitry 0K includes peripheral circuitry for 3D-W array 110: an X decoder 15, a Y decoder (including a readout circuit) 17, a Z decoder 19, and the like.
Fig. 4 shows a programmable gate array 400. It contains a regular arrangement of programmable modules 400A and 400B, etc. Each programmable module (e.g., 400A) contains a plurality of programmable computing units (e.g., 100AA-100 AD) and programmable logic units (e.g., 200AA-200 AD). A programmable channel 320, 340 is included between the programmable computational unit (e.g., 100AA-100 AD) and the programmable logic unit (e.g., 200AA-200 AD); between the programmable modules 400A and 400B, programmable channels 310, 330, 350 are also included. The programmable channels 310-350 contain a plurality of programmable connections 300. It will be apparent to those skilled in the art that a sea-of-gates design or the like may be used in addition to the programmable channels.
Fig. 5 shows two usage periods 620 and 660 of the reconfigurable gate array 400. The first usage period 620 is divided into two phases: a setup phase 610 and a calculation phase 630. In the setup phase 610, a first lookup table associated with a first mathematical function is loaded into the 3D-MTP array 110 according to user needs; in the calculation stage 630, the corresponding LUT is looked up in the 3D-MTP array 110 to obtain the value of the first mathematical function. Similarly, the second usage period 660 also contains the same setup phase 650 and calculation phase 670. Reconfigurable computing is particularly suited for data processing in SIMD (single instruction multiple data stream). Once the LUT is loaded into the 3D-MTP array 110 at the setup stage 610, a large amount of data can be fed into the programmable computing unit 100 for processing and a higher processing speed is achieved. The SIMD has many applications such as the same operation or vector operation for a plurality of pixels in image processing, large-scale parallel computation used in scientific computation, and the like. In addition, the programmable gate array can streamline the computation in its programmable compute units to further increase throughput.
Fig. 6A discloses a connection library that can be implemented by the programmable connection 300. The programmable connection 300 is similar to the programmable connection disclosed in U.S. Pat. No. 4,870,302. It adopts a connection mode of the following connection library: a) Interconnect lines 302/304 are connected, interconnect lines 306/308 are connected, but 302/304 is disconnected from 306/308; b) Interconnect lines 302/304/306/308 are all connected; c) Interconnect lines 306/308 are connected, and interconnect lines 302, 304 are not connected nor are interconnect lines 306/308 connected; d) Interconnect lines 302/304 are connected, and interconnect lines 306, 306 are not connected nor are interconnect lines 302/304 connected; e) None of the interconnect lines 302, 304, 306 are connected. In this specification, a symbol "/" between two interconnect lines indicates that the two interconnect lines are connected, and a symbol "/" between two interconnect lines indicates that the two interconnect lines are disconnected.
Fig. 6B discloses a logic operation library that can be implemented by the programmable logic unit 200. Inputs a and B are input data 210, 220 and output C is output data 230. The programmable logic unit 200 is similar to the programmable logic unit disclosed in U.S. Pat. No. 4,870,302. It may implement at least one of the following logical operation libraries: c= A, A logical negation, a shift, AND (a, B), OR (a, B), NAND (a, B), NOR (a, B), XOR (a, B), arithmetic addition a+b, arithmetic subtraction a-B, AND the like. The programmable logic unit 200 may also contain circuit elements such as registers, flip-flops, etc. to implement pipeline operations.
Fig. 7A is a layout diagram of a second programmable computing unit 100. Since the 3D-W array 110 does not occupy a substrate area, the programmable logic unit 200 may be integrated under the 3D-W array 110 and at least partially covered by the 3D-W array 110. In addition, programmable connections may also be integrated under the 3D-W array 110 and at least partially covered by the 3D-W array 110. All of these measures can reduce the chip area of the programmable gate array 400.
Fig. 7B is a cross-sectional view of the programmable computing units 100AA-100AD of fig. 4. To further reduce the chip area of the programmable gate array 400, three-dimensional integration may be performed on the 3D-W array, the 3D-W array 110AA (LUT a storing the first basic mathematical function, located at the storage layer 16A) in the programmable computing unit 100AA is stacked on the substrate circuit 0K (+z direction), the 3D-W array 110AB (LUT B storing the second basic mathematical function, located at the storage layer 16B) in the programmable computing unit 100AB is stacked on the 3D-W array 110AA (+z direction), the 3D-W array 110AC (LUT C storing the third basic mathematical function, located at the storage layer 16C) in the programmable computing unit 100AC is stacked on the 3D-W array 110AB (+z direction), and the 3D-W array 110AD (LUT D storing the fourth basic mathematical function, located at the storage layer 16D) in the programmable computing unit 100AD is stacked on the 3D-W array 110 AC. At the same time, programmable logic units or programmable connections may also be integrated in the substrate circuit 0K, at least partially covered by the 3D-W arrays 110AA-210 AD.
FIG. 8 is a specific implementation of a programmable gate array 400 for implementing a complex mathematical function：e=a . sin(b)+c . cos (d). The programmable connection 300 in the programmable channels 310-350 takes the form represented in fig. 6A: a programmable connection with dots at the cross-point indicates that the cross-lines are connected, a programmable connection without dots at the cross-point indicates that the cross-lines are disconnected, and a broken programmable connection indicates that the broken interconnect line is divided into two interconnect segments that are disconnected from each other. In this embodiment, the programmable computing unit 100AA is set to log (), the result of which log (a) is sent to a first input of the programmable logic unit 200 AA. The programmable computing unit 100AB is set to log [ sin ()]The calculation result log [ sin (b) ]]Is provided to a second input of programmable logic unit 200 AA. The programmable logic unit 200AA is set to "arithmetic addition" and calculates the result log (a) +log [ sin (b) ]]Is sent to the programmable computing unit 100BA. The programmable computing unit 100BA is set to exp (), the result exp { log (a) +log [ sin (b)]}=a . sin (b) is supplied to a first input of programmable logic unit 200 BA. Similarly, with appropriate settings, programmable computing units 100AC, 100AD, programmable logic unit 200AC, result c of programmable computing unit 100BC . cos (d) is supplied to a second input of programmable logic unit 200 BA. The programmable logic unit 200BA is set to "arithmetic addition," a . sin (b) and c . cos (d) is added here and the final result is sent to output e. It is apparent that other complex mathematical functions can be implemented by the programmable gate array 400 by changing the settings.
The present description takes Field Programmable Gate Arrays (FPGAs) as examples. In an FPGA, the wafer will complete all the process steps (including all the programmable compute units, programmable logic units and programmable connections). In the programming field, the functions of the FPGA can be defined by setting programmable connections. The above examples of FPGAs can be easily generalized to conventional programmable gate arrays. In a conventional programmable gate array, the wafer is only semi-finished, i.e., the wafer production only completes the programmable compute units and programmable logic units, but does not complete the programmable connections. After the functionality of the chip is determined, the programmable channels 310-350 are customized by back-end processing.
It will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the application as defined by the appended claims. Accordingly, the application should not be limited except as by the appended claims.
Claims (12)
1. A programmable gate array (400), comprising:
a plurality of programmable connections, each of said programmable connections selectively effecting a connection from a connection library;
a plurality of programmable computing units, each of the programmable computing units comprising: at least one memory array (110), said memory array (110) storing a look-up table LUT of mathematical functions, said mathematical functions being other than arithmetic plus '+' and arithmetic minus '-'; in a setup phase, loading a look-up table LUT of the mathematical function into the memory array (110) according to user needs; in the calculation phase, obtaining the value of the mathematical function by looking up the look-up table LUT;
wherein the programmable gate array (400) implements programmable computation by programming the plurality of programmable connections and the plurality of programmable compute units.
2. The programmable gate array (400) of claim 1, further characterized by: the mathematical function includes an override function and/or a multivariate function.
3. The programmable gate array (400) of claim 2, further characterized by: the memory array (110) is a three-dimensional writable storage 3D-W array (110 AA).
4. A programmable gate array (400) according to claim 3, further characterized by: the memory array (110) is reprogrammable.
5. The programmable gate array (400) of claim 2, further characterized by: the memory array (110) is reprogrammable.
6. The programmable gate array (400) of claim 1, further characterized by: the memory array (110) is a three-dimensional writable storage 3D-W array (110 AA).
7. The programmable gate array (400) of claim 6, further characterized by: the memory array (110) is reprogrammable.
8. The programmable gate array (400) of claim 1, further characterized by: the memory array (110) is reprogrammable.
9. The programmable gate array (400) of claim 3 or 6, further characterized by: the memory array (110) contains at least another three-dimensional writable storage 3D-W array (110 AB), the another three-dimensional writable storage 3D-W array (110 AB) being stacked over the one three-dimensional writable storage 3D-W array (110 AA).
10. The programmable gate array (400) of any of claims 4, 5, 7, 8, further characterized by: the programmable computing unit implements different mathematical functions at different time periods.
11. The programmable gate array (400) of any of claims 1-8, further characterized by: the memory array (110) covers at least part of the programmable connections.
12. The programmable gate array (400) of any of claims 1-8, further characterized by: and a plurality of programmable logic units, each of which selectively implements a logic operation from a logic operation library.
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| CN201710126067.3A CN107154798B (en) | 2016-03-05 | 2017-03-06 | Programmable gate array based on three-dimensional writable memory |
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| CN109698690A (en) * | 2017-10-20 | 2019-04-30 | 成都海存艾匹科技有限公司 | Programmable gate array based on three-dimensional longitudinal writeable storage array |
| CN109698694A (en) * | 2017-10-23 | 2019-04-30 | 杭州海存信息技术有限公司 | Programmable computing array |
| CN109687864A (en) * | 2017-10-19 | 2019-04-26 | 成都海存艾匹科技有限公司 | Programmable gate array containing programmable computing unit |
| CN109684653B (en) * | 2017-10-19 | 2023-12-22 | 成都海存艾匹科技有限公司 | Programmable gate array package containing programmable computing units |
| CN109698692A (en) * | 2017-10-20 | 2019-04-30 | 成都海存艾匹科技有限公司 | Using two-sided integrated programmable gate array |
| CN109545783A (en) * | 2017-09-22 | 2019-03-29 | 成都海存艾匹科技有限公司 | Three-dimensional computations chip containing three-dimensional memory array |
| CN108053848A (en) * | 2018-01-02 | 2018-05-18 | 清华大学 | Circuit structure and neural network chip |
| CN116049093A (en) * | 2018-12-10 | 2023-05-02 | 杭州海存信息技术有限公司 | Separated three-dimensional processor |
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| CN101266463A (en) * | 2008-04-29 | 2008-09-17 | 江南大学 | Fuzzy controller based on FPGA |
| US8669780B2 (en) * | 2011-10-31 | 2014-03-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three dimensional integrated circuit connection structure and method |
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