CN117056120A

CN117056120A - Method for quickly recovering data flow in radar system

Info

Publication number: CN117056120A
Application number: CN202310868849.XA
Authority: CN
Inventors: 吴彬; 檀毛琴; 张新刚
Original assignee: Leihua Electronic Technology Research Institute Aviation Industry Corp of China
Current assignee: Leihua Electronic Technology Research Institute Aviation Industry Corp of China
Priority date: 2023-07-13
Filing date: 2023-07-13
Publication date: 2023-11-14

Abstract

The application provides a rapid recovery method of data flow in a radar system, which belongs to the technical field of communication, and particularly relates to a method for notifying a main control module of an interrupt pin signal of an SRIO exchange chip in an interrupt mode when the SRIO exchange chip detects that a port is abnormal; the master control module informs a preprocessing module of the radar system to close the SRIO data forwarding function through a switch signal; after receiving the interrupt, the main control module actively acquires an abnormal port of the SRIO exchange chip through the BIT system, configures a register corresponding to the abnormal port of the SRIO exchange chip through the BIT bus to reset the current abnormal port, and sends a reset request to a port of the opposite terminal node through the current reset port so as to remove the error of the current SRIO node; the main control module is timely notified through interruption, and the registers at the two ends of the error port are operated to clear errors, so that the time consumption is in the millisecond level, and the recovery time is greatly shortened.

Description

Method for quickly recovering data flow in radar system

Technical Field

The application relates to the field of communication, in particular to a method for quickly recovering data flow in a radar system.

Background

Serial Rapid IO is a high-performance, low-pin-count, packet-switching-based interconnect architecture, and is an open interconnect technology standard designed to meet the requirements of high-performance embedded systems. The SRIO is mainly applied to the internal interconnection of the embedded system, supports the communication between chips and between boards, and can be used as the backboard connection of the embedded equipment.

The prior airborne radar processing system mainly comprises a data processing module, a signal processing module, a data exchange module and the like, and the large-bandwidth and high-reliability transmission of data is realized by adopting an SRIO interconnection bus protocol between chips and boards. The method is characterized in that a full-switching network based on an SRIO bus is designed in a radar processing unit according to the requirement of high-bandwidth communication of big data, and a method for flexibly communicating among a plurality of modules and among a plurality of chips such as FPGA, CPU, DSP and the like in the modules is realized. However, in the data transmission process, abnormal communication of a certain level of SRIO node can cause data flow blockage of the whole radar processing system, so that the whole radar processing system works abnormally. The traditional recovery method is to reset the whole radar processing system, the restarting time of each module is longer, and the avionic system has no picture in the resetting process, so that the pilot's observation and the continuity of the whole system are affected.

Disclosure of Invention

In view of the above, the application provides a method for quickly recovering data flow in a radar system, which solves the problems of overlong recovery time of data flow and disappearance of avionic pictures caused by abnormal communication of SRIO nodes in the current radar processing system, timely informs a main control module through interruption, clears errors through operating registers at two ends of an error port, consumes time in millisecond level, and greatly shortens recovery time.

The application provides a rapid recovery method of data flow in a radar system, which adopts the following technical scheme:

the radar system comprises a radar processing unit, wherein the radar processing unit comprises a preprocessing module, a signal processing module and a main control module, the signal processing module and the main control module are communicated through an SRIO bus, the signal processing module and the preprocessing module are communicated through the SRIO bus, the signal processing module and the main control module are interconnected through a BIT bus, the main control module and the preprocessing module are interconnected through a BIT bus, and the BIT bus is independent of the SRIO communication bus;

the method comprises the following steps:

when the SRIO exchange chip detects that the port is abnormal, an interrupt pin signal of the SRIO exchange chip informs the main control module in an interrupt mode;

the master control module informs a preprocessing module of the radar system to close the SRIO data forwarding function through a switch signal;

after receiving the interrupt, the main control module actively acquires an abnormal port of the SRIO exchange chip through the BIT system, configures a register corresponding to the abnormal port of the SRIO exchange chip through the BIT bus to reset the current abnormal port, and sends a reset request to a port of the opposite terminal node through the current reset port so as to remove the error of the current SRIO node;

after the main control module detects the error clearance, the preprocessing module is informed to start the forwarding function through a switch signal, and the radar system data flow is recovered to be normal.

Optionally, when the SRIO data transmission is started on a node of the SRIO switching chip, a time stamp is preset, and if the data transmission is not completed within a preset time, the SRIO data transmission is stopped.

Optionally, the preprocessing module, the signal processing module and the main control module all comprise an SRIO exchange chip and an FPGA, and interrupt pins IRQ_N of the SRIO exchange chip in the preprocessing module, the signal processing module and the main control module are connected to the respective FPGA. .

Optionally, the preprocessing module and the signal processing module further comprise a DSP, the main control module further comprises a CPU, and the preprocessing module, the signal processing module and the main control module all comprise an ARM;

the CPU of the main control module is connected to the FPGA through a local bus, the FPGA and the ARM are interconnected on the main control module to finish control command issuing, the FPGA and the ARM are interconnected on the preprocessing module and the signal processing module to finish BIT data reporting of the DSP, the ARM of each module periodically reads a port state register in the SRIO switch, the ARM of the preprocessing module and the signal processing module integrates and transmits all BIT information to the ARM chip in the main control module, the ARM on the main control module transmits all BIT information of the radar processing unit to the CPU through a low-speed interface, and the CPU reports the avionics system through the FC bus.

Optionally, the FPGA is interconnected with the ARM via an I2C bus.

Optionally, the ARM periodically reads the port status register in the SRIO switch through the I2C interface.

Optionally, the ARM integrates all BIT information and transmits the BIT information to an ARM chip in the main control module through an RS485 bus, and the main control module accesses the ARM of the preprocessing module and the signal processing module through the RS485 bus.

In summary, the application has the following beneficial technical effects:

according to the application, the main control module is timely notified through interruption, and the error is cleared through the registers at the two ends of the operation error port, so that the time-consuming millisecond level is shortened, and the recovery time is greatly shortened.

When errors are recovered, the main control module is still in a normal state, and can respond to partial functions of the avionics system, so that the avionics system is not in a picture-free state. The other node processing modules can still continue SRIO communication after error recovery.

According to the application, the main control module is informed in an interrupt mode, the data source of the radar processing system is rapidly closed, and the processing module at the front end of the fault node is prevented from being totally blocked due to data back pressure. And the method can also prevent the SRIO port recovery effect from being influenced by data transmission on the SRIO bus when the system is recovered.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a block diagram of a part of bus connection of a radar processing unit according to an embodiment of the present application.

Fig. 2 is a block diagram of a radar processing unit BIT system connection according to an embodiment of the present application.

Fig. 3 is a schematic diagram of radar data flow according to an embodiment of the present application.

Fig. 4 is a flow chart of data processing when an abnormality occurs in an SRIO node according to an embodiment of the present application.

FIG. 5 is a flowchart of a port recovery operation according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.

In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.

The embodiment of the application provides a rapid recovery method for a data stream in a radar system.

The radar system comprises a radar processing unit, the radar processing unit comprises a preprocessing module, a signal processing module and a main control module, the signal processing module and the main control module are communicated through an SRIO bus, the signal processing module and the preprocessing module are communicated through the SRIO bus, the signal processing module and the main control module are interconnected through a BIT bus, the main control module and the preprocessing module are interconnected through the BIT bus, and the BIT bus is independent of the SRIO communication bus. The SRIO is called as a Serial Rapid IO, and the Chinese name is connected with the high-speed bus.

A rapid recovery method for data flow in radar system includes the following steps:

when the SRIO exchange chip detects that the port is abnormal, an interrupt pin signal of the SRIO exchange chip informs the main control module in an interrupt mode.

The main control module informs the preprocessing module of the radar system to close the SRIO data forwarding function through a switch signal.

After receiving the interrupt, the main control module actively acquires an abnormal port of the SRIO exchange chip through the BIT system, configures a register corresponding to the abnormal port of the SRIO exchange chip through the BIT bus to reset the current abnormal port, and sends a reset request to a port of the opposite terminal node through the current reset port, so that the error of the current SRIO node is cleared. When communication of a certain level of SRIO node is abnormal, the master control module is informed of the interrupt pin signal of the SRIO exchange chip in an interrupt mode, and the master control module informs the preprocessing module of closing the forwarding function through the switch signal. After receiving the interrupt, the main control module actively acquires an error port of the SRIO exchange chip through the BIT system, configures a corresponding register of the SRIO exchange chip through a BIT system bus to reset the current error port, and sends a reset request to the opposite port through the current port, and the SRIO modules at the two ends are reset to enable the current SRIO node error to be cleared.

When the SRIO data transmission is started on the node of the SRIO exchange chip, presetting a time stamp, and stopping the SRIO data transmission if the data transmission is not completed within preset time. The problem that data transmission cannot be normally withdrawn due to errors in the data transmission process, and the operation of other tasks of the system is affected is avoided, so that avionics pictures cannot be normally displayed. Each processing module is a node in the radar data stream, reads the current SRIO error state flag bit before SRIO transmission, and transmits the current SRIO error state flag bit when no error is detected, and pauses the transmission when the error is detected, and waits for the error to be cleared. And each processing module sets a timeout mechanism when carrying out SRIO transmission, so that the problem that the data cannot be withdrawn due to errors in the data transmission process is avoided.

The method and the device recover radar data flow in a traditional mode of resetting the whole system, the duration is not less than 10 seconds, the main control module is timely notified through interruption, and the error is cleared through the registers at the two ends of the operation error port, so that the recovery time is greatly shortened in a time-consuming millisecond level.

The pretreatment module, the signal processing module and the main control module all comprise SRIO exchange chips and FPGAs, and interrupt pins IRQ_N of the SRIO exchange chips in the pretreatment module, the signal processing module and the main control module are connected to the respective FPGAs. Wherein, the FPGA is named Field Programmable Gate Array and the Chinese name is field programmable gate array; the IRQ is collectively called "Interrupt ReQuest", and the Chinese name is interrupt requirement.

The preprocessing module and the signal processing module further comprise a DSP, the main control module further comprises a CPU, and the preprocessing module, the signal processing module and the main control module all comprise ARM; the CPU of the main control module is connected to the FPGA through a local bus, the FPGA and the ARM on the main control module are interconnected to finish control command issuing, and the FPGA and the ARM on the preprocessing module and the signal processing module are interconnected to finish BIT data reporting of the DSP, wherein the FPGA is interconnected with the ARM through an I2C bus. ARM of each module periodically reads the status register of the internal port of the SRIO switch through the I2C interface, ARM of the preprocessing module and the signal processing module integrates all BIT information and transmits the BIT information to an ARM chip in the main control module through the RS485 bus, the main control module accesses the ARM of the preprocessing module and the signal processing module through the RS485 bus, ARM on the main control module transmits all BIT information of the radar processing unit to the CPU through the low-speed interface, and the CPU reports the information to the avionics system through the FC bus. Wherein, DSP is named Digital Signal Processor, chinese name is digital signal processing; the CPU is named as Central Processing Unit, and the Chinese name is named as a central processing unit; ARM is known as Acorn RISC Machine; I2C is known as Inter-Integrated Circuit; RS485 is called as Recommended Standard abbreviation, meaning of recommended standard, 485 is identification number.

In one embodiment, as shown in fig. 1, the radar processing unit is composed of a preprocessing module, a signal processing module 1, a signal processing module 2, a signal processing module 3 and a main control module. Processors inside each module are all interconnected through an SRIO exchange chip, and each module is cascaded through the SRIO exchange chip and used for high-speed data interaction, and the SRIO exchange chip comprises but is not limited to CPS1848, NRS1800 and the like. The interrupt pins IRQ_N of the SRIO exchange chips of the modules are all connected into the FPGA of the board. And the other modules are respectively provided with two GPIOs connected with the FPGA of the main control module.

As shown in fig. 2, the DSP of the signal processing module and the preprocessing module are connected to the FPGA through a low-speed bus, the FPGA is interconnected with the ARM through the I2C, so as to complete BIT data reporting and control command issuing of the DSP on the single module, the ARM periodically reads the port status register in the SRIO switch through the I2C interface, and the ARM integrates all BIT information of the module and transmits the integrated BIT information to the ARM chip in the main control module through the RS485 bus. The ARM on the main control module transmits all BIT information of the radar unit to the CPU through the low-speed interface, and the CPU reports the BIT information to the avionics system through the FC bus. The BIT system of the system mainly relies on a low-speed bus for communication, such as I2C, UART, RS485 and the like, has high reliability and is simple in uploading and issuing commands. The master control can access ARM of all modules through RS485, and then access all SRIO switching chips through I2C on the ARM.

As shown in fig. 3, the radar data stream is generally sent from the AD module to the preprocessing module, where the FPGA performs preprocessing on the data and forwards the data, and the data stream enters the DSP array to perform signal processing, such as channel calibration, pulse compression, FFT, clutter tracking, and the like. After the signal processing, the data flow enters the main control module through the SRIO bus, and the main control module uploads the result to the avionics system through the FC bus. And the AD module and the preprocessing module are communicated by adopting an AURORA protocol, so that the uploading of a main control command and the issuing of radar echo data are completed. The radar data is mainly transmitted among the FPGA, the DSP array and the main control module of the preprocessing module through SRIO. And setting a data stream switch signal in the preprocessing module through the GPIO, and stopping receiving the AD data when the GPIO is high and the preprocessing module normally forwards the data issued by the AD and when the GPIO is low.

As shown in fig. 4 and 5, in one embodiment, the workflow carried out by the method of the present application is:

1) Firstly, ARM of the module configures an SRIO switching chip through I2C, configures an IRQ_N trigger register and a port error detection related register, and ensures that the module has an error reporting function.

2) During SRIO communication, the processing module firstly inquires the SRIO link state marks such as OUTPUT_ERR_STOP, INPUT_ERR_STOP and PORT_ERR, and the state normally carries out SRIO sending or reading operation.

3) When a certain SRIO node of the radar data flow is blocked and the port state of the SRIO switching chip is wrong, the IRQ_N pin can generate a low level for informing the FPGA of the board.

4) Each module is provided with GPIO connected to the main control module, and when the FPGA detects that the IRQ_N is effective, the FPGA generates GPIO interrupt to inform the main control CPU, and reports SRIO link faults.

5) And the CPU of the main control module immediately generates a switch signal through the other GPIO after receiving the notification, and the switch signal is used for notifying the FPGA on the preprocessing module and stopping issuing the data transmitted by the AD.

6) And the main control module actively initiates inquiry operation through the BIT bus, reads all port state registers of the switching chip and determines the ports with errors. Any position of output_err_stop, input_err_stop and port_err of a certain PORT is 1, which indicates that the current SRIO PORT is abnormal in communication.

7) The main control module issues an error clearing instruction through the BIT system, firstly issues a command to the ARM of the current module through the RS485, the ARM configures a corresponding register of the SRIO switching chip through the I2C interface to reset the current error port, and sends a reset request to the opposite port through the current port, and the SRIO modules at the two ends are reset to clear the error of the current SRIO node and restore communication.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims

1. The rapid recovery method for the data stream in the radar system is characterized in that the radar system comprises a radar processing unit, the radar processing unit comprises a preprocessing module, a signal processing module and a main control module, the signal processing module and the main control module are communicated through an SRIO bus, the signal processing module and the preprocessing module are communicated through the SRIO bus, the signal processing module and the main control module are interconnected through a BIT bus, the main control module and the preprocessing module are interconnected through a BIT bus, and the BIT bus is independent of the SRIO communication bus;

the method comprises the following steps:

2. The method for quickly recovering data flow in a radar system according to claim 1, wherein when the SRIO data transmission is started on a node of the SRIO switching chip, a time stamp is preset, and when the data transmission is not completed within a preset time, the SRIO data transmission is stopped.

3. The method for quickly recovering data flow in a radar system according to claim 1, wherein the preprocessing module, the signal processing module and the main control module all comprise an SRIO switching chip and an FPGA, and interrupt pins IRQ_N of the SRIO switching chips in the preprocessing module, the signal processing module and the main control module are connected to the respective FPGAs.

4. The method for quickly recovering data flow in radar system according to claim 3, wherein the preprocessing module and the signal processing module further comprise a DSP, the main control module further comprises a CPU, and the preprocessing module, the signal processing module and the main control module all comprise an ARM;

5. The method for rapid recovery of data streams in a radar system of claim 4, wherein the FPGA is interconnected with the ARM via an I2C bus.

6. The method for fast recovery of data streams in a radar system according to claim 4, wherein the ARM periodically reads the port status register in the SRIO switch through the I2C interface.

7. The method for rapid recovery of data stream in radar system according to claim 4, wherein ARM integrates all BIT information and transmits the integrated BIT information to ARM chip in main control module through RS485 bus, main control module accesses ARM of preprocessing module and signal processing module through RS 485.