CN112540918A - Redundancy flight pipe computer synchronous debugging method based on ARINC659 bus - Google Patents
Redundancy flight pipe computer synchronous debugging method based on ARINC659 bus Download PDFInfo
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- 238000011084 recovery Methods 0.000 claims description 4
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
Abstract
The invention relates to a synchronous debugging method of a redundancy flight management computer based on an ARINC659 bus, which is characterized in that a special synchronous debugging device is constructed to debug the onboard software of the redundancy flight management computer based on the ARINC659 bus, the operation of each redundancy channel of the redundancy flight management computer is mutually independent and synchronous, the real-time tasks are scheduled according to a time triggering protocol of a unified clock, and no independent clock exists; in the development and debugging process of the onboard software of the redundancy flight management computer, synchronous operation and stop among redundancy channels must be ensured. The technology of the invention is already applied to the research and development process of the flight management system of a plurality of unmanned aerial vehicle models, and has good effect. Meanwhile, the technology can also be generally applied to the field of other redundancy computers using ARINC659 backboard buses.
Description
Technical Field
The invention belongs to the design technology of a redundancy flight management computer and an embedded system.
Background
The ARINC659 bus specification is a specification standard developed for the transmission of digital data information between field replaceable modules within an integrated modular avionics equipment cabinet. The ARINC659 bus improves reliability with minimal logic and minimal bus count, and fault tolerance with extremely high fault detection coverage and fault redundancy. ARINC659 is one of the best known time trigger protocols, and the time trigger protocol ensures the certainty of the system and greatly improves the stability, testability and functional verification of the system; the time trigger protocol has a global clock, each communication event and calculation event are predefined in a static table, the clock synchronization is realized through the protocol, the time trigger protocol has time certainty, high bandwidth of the event trigger protocol is not needed, and the interface characteristic and the testability are stable and reliable. The system behavior is planned in advance, and has predictability, determinism and system stability. The system of the time-triggered protocol is very suitable for engineering projects with strict requirements on safety.
The high-end unmanned aerial vehicle flight management computer generally adopts a redundancy flight management computer based on an ARINC659 backplane bus architecture, and the operation of each channel of the redundancy flight management computer is mutually independent and synchronous. In the process of developing and debugging airborne software of the flight management computer, synchronous operation and stop among all channels of the redundant flight management computer must be ensured, once the synchronous operation relation among the redundant flight management computers is lost, the out-of-step flight management computer channel is cut off, so that the crash of a flight management system can be caused, and disastrous results are brought. Therefore, maintaining synchronous operation relationship among the channels of the redundant flight management computer is one of the basic conditions for ensuring the normal operation of the flight management system.
Disclosure of Invention
Object of the Invention
The invention designs a synchronous debugging method of a redundancy computer based on an ARINC659 backboard bus, which is used for ensuring that the synchronous running and stopping of all channels of the redundancy flight tube computer can be realized in the synchronous debugging process, and the ground integration and comprehensive test of a flight tube system are powerfully ensured.
Technical solution
A synchronous debugging method of a redundancy flight management computer based on an ARINC659 bus is characterized in that a special synchronous debugging device is constructed to debug airborne software of the redundancy flight management computer based on the ARINC659 bus, each redundancy channel of the redundancy flight management computer runs independently and synchronously, real-time tasks are scheduled according to a time trigger protocol of a unified clock, and no independent clock exists; in the development and debugging process of the onboard software of the redundancy flight management computer, synchronous operation and stop among redundancy channels must be ensured. The special synchronous debugging device comprises a PC (personal computer), a corresponding discrete control card and a multi-channel serial port communication card, and is connected with the redundancy flight tube computer through a special cable so as to transmit debugging signals, wherein the debugging signals comprise discrete signals and character string signals. The computer is provided with a PCI or PCIe slot. The discrete signal comprises a reset signal and a stop signal, and the character string signal is a synchronous operation signal.
The method for synchronously debugging the redundancy flight tube computer based on the ARINC659 bus is characterized by comprising the steps of 1) respectively connecting a discrete control card of synchronous debugging equipment to a non-shielding interrupt inlet of the flight tube computer through a discrete signal wire to be used as input of stop and reset signals, and simultaneously connecting the discrete signals on a cable with N channels of the flight tube computer in a one-to-N mode at an equipment end to enable the N operating channels to receive the stop signals. And 2) connecting the multi-path serial port communication card of the synchronous debugging equipment to the debugging serial port of each channel of the flight tube computer through a serial port line. And 3) when the synchronous stop is carried out, the synchronous debugging equipment simultaneously sends a discrete stop signal to the flight control computer through the discrete control card, the flight control computer responds as a non-shielding interrupt signal after receiving the stop signal, controls all channels of the flight control computer to simultaneously stop, and also needs to close a watchdog signal and close an interrupt response triggered by an ARINC659 backboard 15ms timer when sending the stop signal. The method comprises the following steps of 4) when synchronous recovery operation is carried out, synchronous operation commands are simultaneously sent to a flight control computer by synchronous debugging equipment through a multi-channel serial port communication card in a character string mode, after the flight control computer receives the synchronous operation commands, in order to eliminate time difference of the synchronous operation commands received by each channel, a mode of multiplexing a signal line for synchronous stop is needed, after the synchronous operation commands are sent by the synchronous debugging equipment, stop signals are sent by delaying for 3 seconds, interruption is started after bottom layer target machine agent software receives the stop signals, and operation is started when the interruption of a timing clock of 15ms for the third time sent by an ARINC659 back plate is waited.
Advantageous effects
The technology of the invention is already applied to the research and development process of the flight management system of a plurality of unmanned aerial vehicle models, and has good effect. Meanwhile, the technology can also be generally applied to the field of other redundancy computers using ARINC659 backboard buses.
Drawings
FIG. 1 shows the connection relationship between the synchronous debugging device and the multi-redundancy flight management computer
FIG. 2 flow chart of a synchronous stop operation
FIG. 3 is a flow chart of synchronous operation
Detailed Description
Because the redundancy computer based on the ARINC659 backplane bus is scheduled according to the time-triggered protocol of the unified clock, compared with the general redundancy computer, the key solution mainly lies in the following two points:
a) how to perform synchronous stop operation of the multi-channel airborne software based on the unified clock;
b) how to carry out synchronous recovery operation of multi-channel airborne software based on a unified clock.
A redundancy computer based on an ARINC659 back panel bus is used for debugging airborne software by means of a special synchronous debugging device. The main principle of the structure is shown in fig. 1 (taking typical three redundancies as an example), the mechanism of synchronous stop is shown in the flow of fig. 2, and the mechanism of synchronous operation is shown in the flow of fig. 3:
firstly, respectively connecting a discrete control card of synchronous debugging equipment to a non-shielding interrupt inlet of a flight tube computer through discrete signal wires to be used as input of stop and reset signals, and simultaneously, designing a circuit at an equipment end in a one-to-three mode so that three operation channels can receive low-level stop signals;
connecting a multi-channel serial port communication card of the synchronous debugging equipment to a debugging serial port of each channel of the flight tube computer through a serial port line;
when the synchronous stop is carried out, the synchronous debugging equipment simultaneously sends a discrete stop signal to the flight management computer through the discrete control card, the flight management computer responds as a non-shielding interrupt signal after receiving the stop signal, controls all channels of the flight management computer to stop simultaneously, and also needs to close a watchdog signal and close an interrupt response triggered by an ARINC659 backboard 15ms timer when the stop signal is sent;
when the synchronous operation is recovered, the synchronous debugging equipment simultaneously sends a synchronous operation command to the flight management computer in a character string mode through a multi-channel serial port communication card, after the flight management computer receives the synchronous operation command, in order to eliminate the time difference of the synchronous operation command received by each channel, a mode of multiplexing a signal line for synchronous stop is needed, after the synchronous operation command is sent by the synchronous debugging equipment, a stop signal is sent by delaying for 3 seconds, after the bottom layer target machine agent software receives the stop signal, interruption is opened, and from this time, the operation is started after the interruption of the third 15ms timing clock sent by an ARINC659 back plate arrives. The reason for ignoring the first 15ms tick interrupt is because it is the last posted interrupt held on the interrupt controller, and the reason for ignoring the second 15ms tick interrupt is because the uncontrollable nature of the unified clock may cause the interrupt program to recover at a random location, which may cause the program running time of the beat to be less than 15ms, which may cause the onboard software to fail to complete the specified task, resulting in a task timeout.
Examples
The technical scheme of the redundancy computer synchronous debugging equipment based on the ARINC659 backplane bus takes a three-channel (three-redundancy) flight management computer based on the ARINC659 backplane bus as an example, three channels A/B/C of the flight management computer (VMC) are all arranged on the ARINC659 bus, and a communication protocol is defined as RS422 (baud rate is 115200bps) and two discrete control signals (reset signal and stop signal) during hardware design. The hardware scheme design adopts a PC machine to install a control card PCI7250 based on a standard PCI slot and a multi-serial port card MOXA CP114, and the control card PCI7250 and the multi-serial port card MOXA CP114 are used for respectively transmitting discrete control signals and RS422 serial communication signals with the flight management computer.
Taking the CPU of the PPC755 model as an example, according to its manual, the response of the CPU to an external interrupt is a low-level trigger mode. Therefore, the synchronous stop signal is designed to be an SMI interface (non-shielding interrupt) connected to each channel board, the stop signal sent by the DIF device is a low-level signal, and a circuit design is performed on the device side in a three-in-one manner, so that three running channels can receive the low-level stop signal and guarantee simultaneous stop, and the stop signal is sent while the "watchdog" signal is turned off, and the interrupt response triggered by the 15ms timer of the ARINC659 backplane is turned off.
Once the synchronous operation relationship between each redundancy channel is lost, the corresponding redundancy channel which is out of step is cut off, so that the crash of the fly pipe system can be caused, and a catastrophic result is brought.
The main problems of synchronous recovery operation of multi-channel airborne software based on a unified clock are as follows:
a) the receiving of the operation command among the channels inevitably has time difference, and a synchronization mechanism is necessary to ensure that all the channels operate synchronously;
b) the ARINC659 backboard 15ms timing clock based on the unified clock is uncontrollable;
c) the inter-channel synchronization signal line cannot be utilized.
Under the condition, in order to eliminate the time difference of synchronous running commands (character strings) received by each channel, a mode of multiplexing signal lines for synchronous stop is adopted, after the DIF equipment sends the synchronous running commands, stop signals are sent after 3 seconds of delay, interrupt is opened after bottom layer target machine agent software receives the stop signals, and the operation is started after the third 15ms of timing clock interrupt sent by an ARINC659 backboard arrives. The reason for ignoring the first 15ms tick interrupt is because it is the last posted interrupt held on the interrupt controller, and the reason for ignoring the second 15ms tick interrupt is because the uncontrollable nature of the unified clock may cause the interrupt program to recover at a random location, which may cause the program running time of the beat to be less than 15ms, which may cause the onboard software to fail to complete the specified task, resulting in a task timeout.
Claims (8)
1. A multi-redundancy flight management computer synchronous debugging method based on an ARINC659 bus is characterized in that a special synchronous debugging device is constructed to debug the onboard software of the multi-redundancy flight management computer based on the ARINC659 bus, each redundancy channel of the multi-redundancy flight management computer runs independently and synchronously, real-time tasks are scheduled according to a time trigger protocol of a unified clock, and no independent clock exists; in the development and debugging process of the onboard software of the redundancy flight management computer, synchronous operation and stop among redundancy channels must be ensured.
2. The ARINC659 bus-based synchronous debugging method for the multi-redundancy flight tube computer as claimed in claim 1, wherein the special synchronous debugging device comprises a PC and corresponding discrete control card, multi-channel serial port communication card, and is connected with the multi-redundancy flight tube computer through a special cable to transmit debugging signals, and the debugging signals comprise discrete signals and character string signals.
3. The ARINC659 bus-based synchronous debugging method for a multi-redundancy flypipe computer according to claim 2, wherein the computer is provided with a PCI or PCIe slot.
4. The ARINC659 bus-based synchronous debugging method for multi-redundancy flight tube computers according to claim 2, characterized in that the discrete signals comprise a reset signal and a stop signal, and the character string signal is a synchronous operation signal.
5. The ARINC659 bus-based synchronous debugging method for the multi-redundancy flight tube computer according to claim 2, comprising the steps of 1) connecting the discrete control card of the synchronous debugging device to the non-shielding interrupt inlet of the flight tube computer through discrete signal lines as the input of stop and reset signals, and connecting the discrete signals on the cable to N channels of the flight tube computer in a one-to-N manner at the device end, so that the N operating channels can receive the stop signals.
6. The ARINC659 bus-based synchronous debugging method for multi-redundancy flight tube computer as claimed in claim 5, comprising the step 2) of connecting the multi-channel serial port communication card of the synchronous debugging device to the debugging serial port of each channel of the flight tube computer through a serial port line.
7. The ARINC659 bus-based synchronous debugging method for the multi-redundancy flight pipe computer according to claim 6, comprising the step 3) that when the synchronous debugging device synchronously sends a discrete stop signal to the flight pipe computer through the discrete control card when the synchronous debugging device synchronously stops, the flight pipe computer responds to the non-shielding interrupt signal after receiving the stop signal, and controls the channels of the flight pipe computer to simultaneously stop, and the 'watchdog' signal needs to be closed while the stop signal is sent, and the interrupt response triggered by the 15ms timer of the ARINC659 backboard is closed.
8. The ARINC659 bus-based synchronous debugging method for multi-redundancy flight tube computers according to claim 7, comprising the step 4) during synchronous recovery operation, the synchronous debugging device sends synchronous operation commands to the flight tube computers in a character string manner through the multi-channel serial port communication card, after the flight tube computers receive the synchronous operation commands, in order to eliminate the time difference of the synchronous operation commands received by each channel, a signal line for synchronous stop needs to be multiplexed, after the synchronous debugging device sends the synchronous operation commands, the synchronous debugging device sends stop signals with a delay of 3 seconds, after receiving the stop signals, the bottom layer target machine agent software opens interrupts, and from this time, the operation is started to wait for the third 15ms timing clock interrupt sent by the ARINC659 backplane.
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