CN117042292A - Circuit board structure, chip system and electronic equipment - Google Patents
Circuit board structure, chip system and electronic equipment Download PDFInfo
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- CN117042292A CN117042292A CN202310920981.0A CN202310920981A CN117042292A CN 117042292 A CN117042292 A CN 117042292A CN 202310920981 A CN202310920981 A CN 202310920981A CN 117042292 A CN117042292 A CN 117042292A
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- 238000004806 packaging method and process Methods 0.000 claims abstract 2
- 230000001133 acceleration Effects 0.000 claims description 77
- 230000005484 gravity Effects 0.000 claims description 46
- 230000006870 function Effects 0.000 claims description 32
- 239000000446 fuel Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 28
- 238000013461 design Methods 0.000 description 19
- 238000012545 processing Methods 0.000 description 4
- 230000003190 augmentative effect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000013528 artificial neural network Methods 0.000 description 2
- 230000001174 ascending effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
Abstract
A circuit board structure, a chip system and electronic equipment relate to the technical field of chip packaging. Each interface in the first group of interfaces of the circuit board is directly connected with one corresponding circuit board wiring; each interface in the second group of interfaces is connected with a chip resistor area; each interface in the third group of interfaces is connected with two chip resistor areas; each patch resistor area is directly connected with one corresponding circuit board wiring; the at least two chip resistor areas comprise a first group of chip resistor areas and a second group of chip resistor areas, when the circuit board is assembled with the first type of chip package, each chip resistor area in the first group of chip resistor areas is provided with a chip resistor, and the second group of chip resistor areas are vacant; when the circuit board is assembled with the second type chip package body, each chip resistor area in the second group of chip resistor areas is provided with a chip resistor, and the first group of chip resistor areas are vacant. This scheme is convenient for carry out effective utilization to the area of circuit board.
Description
The application provides a divisional application for Chinese patent application with application number 202210310923.1 and application date 2022, 03 and 28, and the application creates a circuit board structure, a chip system and electronic equipment.
Technical Field
The present application relates to the field of chip packaging technologies, and in particular, to a circuit board structure, a chip system, and an electronic device.
Background
With the continuous richness of electronic equipment functions, a plurality of sensors are generally arranged on the electronic equipment at present. Among them, the more widely used sensors include Gravity sensors (G-sensors) and acceleration sensors (Accelerometer sensor, a-sensors).
Wherein the gravity sensor can determine the inclination angle of the electronic device relative to the horizontal plane by measuring the acceleration due to gravity. By analyzing the dynamic acceleration, the movement mode of the electronic equipment can be analyzed. Various moving modes such as shaking, falling, ascending, descending and the like can be converted into electric signals by the gravity sensor. The acceleration sensor can detect the magnitude of acceleration of the electronic device in various directions. The gravity and the direction can be detected when the electronic equipment is static; the electronic equipment gesture recognition method can also be used for recognizing the gesture of the electronic equipment, and is applied to horizontal and vertical screen switching, pedometers and other applications. With the advancement of technology, gravity/acceleration sensors are also presented, i.e. the functions of gravity sensor and acceleration sensor are integrated in one sensor at the same time.
However, the existing gravity/acceleration sensor and acceleration sensor have different specifications, so that in order to enable the motherboard of the electronic device to be compatible with the gravity/acceleration sensor and the acceleration sensor at the same time, the layout area of the gravity/acceleration sensor and the layout area of the acceleration sensor need to be reserved on the motherboard, and when the sensor is assembled later, the electronic device is installed according to the actual requirement of the electronic device, but the area of the circuit board is wasted, so that the area of the circuit board is not effectively utilized.
Disclosure of Invention
In order to solve the above problems, the present application provides a circuit board structure, a chip system and an electronic device, which can reduce the area of the circuit board occupied by the chip system, so as to effectively utilize the area of the circuit board.
In a first aspect, the present application provides a circuit board structure comprising a circuit board, the circuit board comprising: the first group of interfaces, the second group of interfaces, the third group of interfaces and at least two chip resistor areas. The first group of interfaces comprises at least two interfaces, and each of the second group of interfaces and the third group of interfaces at least comprises one interface. Each interface in the first group of interfaces is directly connected with one corresponding circuit board wiring; each interface in the second group of interfaces is connected with a chip resistor area; each interface in the third group of interfaces is connected with two chip resistor areas; each patch resistor area is connected with a corresponding interface and directly connected with one corresponding circuit board wiring; the at least two chip resistor areas comprise a first group of chip resistor areas and a second group of chip resistor areas, when the circuit board is assembled with the first type of chip package, each chip resistor area in the first group of chip resistor areas is used for setting one chip resistor, and each chip resistor area in the second group of chip resistor areas is used for being vacant; when the circuit board is assembled with the second chip package, each chip resistor area in the second group of chip resistor areas is used for setting one chip resistor, and each chip resistor area in the first group of chip resistor areas is used for being free.
In one possible implementation, each interface of the second set of interfaces connects a chip resistor area, including a first pad and a second pad; the first bonding pad is connected with one path of corresponding circuit board wiring, and the second bonding pad is connected with one corresponding interface; the first bonding pad is used for connecting the first end of the chip resistor when the chip resistor is assembled; the second bonding pad is used for connecting the second end of the chip resistor when the chip resistor is assembled.
In one possible implementation manner, the two chip resistor areas connected by each interface in the third set of interfaces are a first chip resistor area and a second chip resistor area; the first chip resistor area is adjacent to the second chip resistor area; the first chip resistor area comprises a first bonding pad and a second bonding pad; the second chip resistor area comprises a third bonding pad and a fourth bonding pad; the first bonding pad and the third bonding pad are respectively connected with one path of corresponding circuit board wiring, and the second bonding pad and the fourth bonding pad are jointly connected with one corresponding interface; the first bonding pad is used for connecting the first end of the chip resistor when the chip resistor is assembled in the first chip resistor area and suspending when the chip resistor is assembled in the second chip resistor area; the second bonding pad is used for connecting the second end of the chip resistor when the chip resistor is assembled in the first chip resistor area and suspending when the chip resistor is assembled in the second chip resistor area; the third bonding pad is used for connecting the first end of the chip resistor when the chip resistor is assembled in the second chip resistor area and suspending when the chip resistor is assembled in the first chip resistor area; the fourth bonding pad is used for connecting the second end of the chip resistor when the chip resistor is assembled in the second chip resistor area and suspending when the chip resistor is assembled in the first chip resistor area.
In one possible implementation manner, the two chip resistor areas connected by each interface in the third set of interfaces are a first chip resistor area and a second chip resistor area; the first chip resistor area and the second chip resistor area are adjacent and share a common bonding pad; the first chip resistor area further comprises a first bonding pad, and the second chip resistor area further comprises a second bonding pad; the first bonding pad and the second bonding pad are respectively connected with one path of corresponding circuit board wiring, and the common bonding pad is connected with one corresponding interface; the first bonding pad is used for connecting the first end of the chip resistor when the chip resistor is assembled in the first chip resistor area and suspending when the chip resistor is assembled in the second chip resistor area; the second bonding pad is used for connecting the first end of the chip resistor when the chip resistor is assembled in the second chip resistor area and suspending when the chip resistor is assembled in the first chip resistor area; and the common bonding pad is used for connecting the second end of the chip resistor when the chip resistor is assembled in the first chip resistor area and connecting the second end of the chip resistor when the chip resistor is assembled in the second chip resistor area. The realization mode can reduce the number of the bonding pads arranged on the circuit board, reduce the hardware cost and further reduce the layout occupying the circuit board.
In one possible implementation, the chip resistor is a zero ohm chip resistor.
In one possible implementation, the first type of chip package acceleration sensor and the second type of chip package integrate sensors with the function of a gravity sensor and the function of an acceleration sensor.
In one possible implementation, the first type of chip package is a universal flash memory UFS, and the second type of chip package is an embedded multimedia card eMMC.
In one possible implementation, the first type of chip package and the second type of chip package are each different types of fuel gauge chips.
In a second aspect, the present application further provides a chip system, where the chip system includes the circuit board structure of any of the above implementations, and further includes a chip package. The chip package is a first type chip package or a second type chip package.
The circuit board structure of the chip system can compatibly support two different chip packages, and the assembly positions do not need to be reserved for the two types of chip packages at the same time. Specifically, for the pin with the same functions of the two types of chip packages, the first group of interfaces is utilized to realize compatible design, for the pin with different functions, the second group of interfaces and the third group of interfaces are utilized to realize compatible design, and the strobe is realized through the chip resistor, so that the layout area of the circuit board is occupied, the feasibility of the compatibility of the two types of chips is improved, the area of the circuit board is effectively utilized, and the area occupied by a chip system is reduced.
In a third aspect, the present application also provides an electronic device, which includes the chip system provided in the above implementation manner.
The circuit board structure of the chip system can compatibly support two different chip packages, and the assembly positions do not need to be reserved for the two types of chip packages at the same time. Specifically, for the pins with the same functions of the two types of chip packages, the first group of interfaces are utilized to realize compatible design, for the pins with different functions, the second group of interfaces and the third group of interfaces are utilized to realize compatible design, and the strobe is realized through the chip resistor, so that the layout area of the circuit board is occupied, the feasibility of the compatibility of the two types of chips is improved, the area of the circuit board is effectively utilized, and the electronic equipment is convenient to realize the high-density layout of devices.
Drawings
FIG. 1 is a schematic diagram of an electronic device;
FIG. 2 is a schematic diagram of a sensor layout;
fig. 3 is a schematic diagram of a circuit board structure according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a first pin interface according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a pin interface of a rotated first region according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a pin interface of a rotated second region according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a pin interface of a circuit board structure according to an embodiment of the present application;
fig. 8 is a schematic diagram of a circuit board structure provided with an acceleration sensor according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a circuit board structure provided with a gravity/acceleration sensor according to an embodiment of the present application;
FIG. 10 is a schematic diagram of an equivalent circuit provided in an embodiment of the present application;
FIG. 11 is a second equivalent circuit diagram according to an embodiment of the present application;
FIG. 12A is a schematic diagram of a chip system according to an embodiment of the present application;
FIG. 12B is a schematic diagram of another system-on-chip provided by an embodiment of the present application;
fig. 13 is a schematic diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the technical personnel in the technical field more clearly understand the scheme of the application, the application scenario of the technical scheme of the application is first described below.
The solution provided by the embodiment of the application is applied to electronic equipment, which can be mobile phones, notebook computers, wearable electronic equipment (such as smart watches), tablet computers, augmented reality (augmented reality, AR) equipment, virtual Reality (VR) equipment, vehicle-mounted equipment and the like, and the application is not limited in particular.
Referring to fig. 1, a schematic diagram of an electronic device is shown.
The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charge management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, keys 190, a motor 191, an indicator 192, a camera 193, a display 194, and a subscriber identity module (subscriber identification module, SIM) card interface 195, etc.
It should be understood that the illustrated structure of the embodiment of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the application, electronic device 100 may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
The processor 110 may include one or more processing units, such as: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and/or a neural network processor (neural-network processing unit, NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors. The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution.
A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may hold instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to reuse the instruction or data, it can be called directly from the memory. Repeated accesses are avoided and the latency of the processor 110 is reduced, thereby improving the efficiency of the system.
The processor 110 can process the data collected by each sensor in the sensor module 180 to achieve a particular function.
The sensor module 180 may include at least one of an acceleration sensor and a gravity/acceleration sensor, and may also include other types of sensors, such as a temperature sensor, a pressure sensor, and the like.
Wherein the gravity sensor can determine an inclination angle of the electronic device 100 with respect to the horizontal plane by measuring acceleration due to gravity. By analyzing the dynamic acceleration, the movement pattern of the electronic device 100 can be analyzed. Various moving modes such as shaking, falling, rising, falling and the like can be converted into electric signals by the gravity sensor, and then the electric signals are calculated and analyzed by the processor 110, so that the designed functions can be realized.
The acceleration sensor may detect the magnitude of acceleration of the electronic device 100 in various directions (typically three axes). The magnitude and direction of gravity may be detected when the electronic device 100 is stationary. The electronic equipment gesture recognition method can also be used for recognizing the gesture of the electronic equipment, and is applied to horizontal and vertical screen switching, pedometers and other applications.
The gravity/acceleration sensor integrates the functions of a gravity sensor and an acceleration sensor.
The existing gravity/acceleration sensor and gravity sensor have different specifications, so that in order to enable the main board of the electronic device to be compatible with the gravity/acceleration sensor and the acceleration sensor at the same time, the layout area of the gravity/acceleration sensor and the layout area of the acceleration sensor are reserved on the main board at the same time, and when the sensor is assembled later, the electronic device is installed according to the actual requirement of the electronic device. The following is a detailed description with reference to the accompanying drawings.
Referring to fig. 2, a schematic diagram of a sensor layout is shown.
A first area 11 for laying out the acceleration sensor and a second area 12 for laying out the gravity/acceleration sensor are reserved on the circuit board 10 at the same time. When the acceleration sensor is needed on the electronic equipment, the acceleration sensor is arranged on the first area 11, and the second area 12 is left; when a gravity/acceleration sensor is required on the electronic device, the gravity/acceleration sensor is laid out on the second area 12, while the first area 11 is left empty.
Under the condition of high-density layout of the circuit board, the area of the circuit board is wasted in the above manner, and the area of the circuit board (i.e. the area of the first area 11) with at least about 9 square millimeters is wasted, so that the effective utilization of the area of the circuit board is not facilitated.
In order to solve the technical problems, the application provides a circuit board structure, a chip system and electronic equipment, pins with the same functions of a chip are directly compatible, pins with different functions of the chip are gated by using zero European resistance, and the occupied area of the circuit board can be reduced, so that the area of the circuit board can be effectively utilized.
Furthermore, in the present application, directional terms "upper", "lower", etc. may be defined as including, but not limited to, the orientation in which the components are schematically disposed with respect to each other in the drawings, and it should be understood that these directional terms may be relative concepts, which are used for the description and clarity with respect thereto, and which may be correspondingly varied depending upon the orientation in which the components are disposed with respect to the drawings in the drawings.
The words "first," "second," and the like in the description of the application are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of features in the art
In the present application, unless explicitly specified and limited otherwise, the term "connected" is to be construed broadly, and for example, "connected" may be either fixedly connected, detachably connected, or integrally formed; may be directly connected or indirectly connected through an intermediate medium.
In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs.
Referring to fig. 3, a schematic diagram of a circuit board structure according to an embodiment of the application is shown.
The circuit board structure 30 includes a circuit board 301, the circuit board 301 including: a first set of interfaces, a second set of interfaces, a third set of interfaces, and at least two chip resistor areas 302.
The first set of interfaces includes at least two interfaces, and the first set of interfaces includes 11 interfaces such as interfaces 5-9, 11-16, etc. for illustration, in practical application, the first set of interfaces may also include other numbers of interfaces, and embodiments of the present application are not limited specifically.
Each interface in the first group of interfaces is directly connected with a corresponding circuit board wiring.
Each of the second set of interfaces and the third set of interfaces includes at least one interface.
Each interface in the second set of interfaces is connected to a chip resistor area 302, and in the embodiment of the present application, the second set of interfaces includes an interface 1 and an interface 10 as an example. In practical applications, the second set of interfaces may further include other numbers of interfaces, and embodiments of the present application are not limited in particular.
Each interface in the third set of interfaces connects two chip resistor areas 302. In the embodiment of the present application, the third set of interfaces including interface 2, interface 3 and interface 4 is described as an example. In practical applications, the third set of interfaces may further include other numbers of interfaces, and embodiments of the present application are not limited in particular.
Each patch resistor area is connected with a corresponding interface and directly connected with one corresponding circuit board wiring;
the at least two chip resistor areas comprise a first group of chip resistor areas and a second group of chip resistor areas, wherein the first group of chip resistor areas comprises chip resistor areas corresponding to an interface 1 and an interface 10, and comprises one chip resistor area respectively connected with an interface 2, an interface 3 and an interface 4; the illustrated second set of chip resistor areas includes another chip resistor area to which interface 2, interface 3 and interface 4 are respectively connected.
When the circuit board 301 is assembled with the first chip package, each chip resistor area in the first set of chip resistor areas is used for setting one chip resistor, and each chip resistor area in the second set of chip resistor areas is used for being left; when the circuit board is assembled with the second chip package, each chip resistor area in the second group of chip resistor areas is used for setting one chip resistor, and each chip resistor area in the first group of chip resistor areas is used for being free.
The implementation of the circuit board 301 when assembled with a first type of chip package is illustrated.
In the embodiment of the application, the circuit board is taken as an example to be compatible with two types of chip packages at the same time, wherein when the circuit board is assembled with a first type of chip package, the pin interfaces 1-10, 15 and 16 of the circuit board are connected with the pins of the first type of chip package, and the pin interfaces 1-14 of the circuit board are connected with the pins of a second type of chip package. Namely, the pin interfaces 5, 6, 7, 8 and 9 in the first group of pin interfaces in the figure are pins which can be directly compatible with two types of chip packages, the pin interfaces 15 and 16 in the first group of pin interfaces are pins required for assembling the first type of chip packages, and the pin interfaces 11-14 in the first group of pin interfaces are pins required for assembling the second type of chip packages; the second group of pin interfaces 1 and 10 are non-NC (not connect) pins of the first group of pin interfaces and are NC pins of the second type chip package; the third group of pin interfaces 2, 3 and 4 are pins which cannot be directly compatible with the two types of chip packages, and function selection needs to be realized through chip resistors.
The description of fig. 3 is only one possible implementation, and in practical application, specific pins and functional distributions of two compatible chip packages may be implemented according to needs to perform design layout, and specific principles are similar to those described above, and the embodiments of the present application are not described here again.
In summary, by using the scheme provided by the embodiment of the application, the circuit board structure can compatibly support two different chip packages, and the assembly positions do not need to be reserved for the two types of chip packages at the same time. The pin with the same functions of the two types of chip packages is subjected to compatible design by utilizing the first group of interfaces, the pin with different functions is subjected to compatible design by utilizing the second group of interfaces and the third group of interfaces, and gating is realized by using the chip resistor, so that the layout area of the circuit board is occupied, and the feasibility of compatibility of the two types of chips is improved, so that the area of the circuit board is effectively utilized.
The following description is made in connection with specific implementations.
In the following description, the first type of chip package is taken as an acceleration sensor, and the second type of chip package is taken as a gravity/acceleration sensor as an example. The principle is similar when the circuit board is compatible with other types of chip packages and will not be described in detail.
Referring to fig. 4, a schematic diagram of a pin interface according to an embodiment of the present application is shown.
The figure shows a prior art layout in which a first area 11 of the circuit board 10 is used for laying out the acceleration sensor and a second area 12 of the circuit board 10 is used for laying out the gravity/acceleration sensor.
The interface (pin) distribution of the acceleration sensor corresponding to the pin interface in the first area 11 is sequentially as follows:
1-GND;2-Data; 3-power supply; 4-GND; 5-power supply; 6-GND;7-GND; 8-a power supply; 9-NC;10-CLK;11-NC; 12-enable.
GND is the ground pin.
The I2C (Inter-Integrated Circuit, integrated circuit) bus is a simple, efficient bus and requires only 2 pins of the chip and only 2 wires on the circuit board.
Wherein the Data pin is SDA (serial Data line) of the I2C bus.
CLK is SCL of the I2C bus (serial clock line ).
NC is not connected, i.e. pins do not need to be connected to external circuitry.
The pin (pin) distribution of the gravity/acceleration sensor corresponding to the pin interface in the second area 12 is as follows:
1-NC; 2-a power supply; 3-CLK;4-Data; 5-power supply; 6-GND;7-GND; 8-a power supply; 9-NC;10-NC;11-GND; 12-power supply; 13-a power supply; 14-Enable.
After rotating the pin interface layout of the first region 11 in fig. 4 by 180 ° counterclockwise (or by 180 ° clockwise) as a whole, the pin interface schematic diagram shown in fig. 5 is obtained.
The pin interface layout of the second region 12 in fig. 5 is rotated generally 90 ° clockwise (or 270 ° clockwise) to obtain the pin interface schematic diagram shown in fig. 6.
Referring to fig. 5 and 6 together, it can be seen that the pin interfaces 5, 6, 7, 8 and 9 in the two regions are functionally identical and are directly compatible.
The application designs the overlapped circuit boards of fig. 5 and 6, and the schematic diagram of the pin interface of the circuit board structure obtained by the overlapped circuit boards can be shown in fig. 7.
Therefore, for the acceleration sensor and the layout gravity/acceleration sensor, 10 pins can share a bonding pad in total, in order to realize the electrical performance of the acceleration sensor, the 10 pins need to be respectively subjected to function differentiation design, and the analysis on the pins of the chip proves that 5 pins in total have performance differences in the 10 pins; there are 5 pins for realizing compatible functions, corresponding to 5 pins, 6 pins, 7 pins, 8 pins and 9 pins in the above figures. Wherein 5pin and 8pin are 1.8V power supply of two devices, 6pin and 7pin are chip ground signals, and 9pin is an NC interface.
For the remaining 5 pins of the different functions, namely 1pin, 2pin, 3pin, 4pin and 10pin, a scheme of increasing zero ohm resistance for gating is adopted, which is specifically described below with reference to the accompanying drawings.
See also fig. 8 and 9. Fig. 8 is a schematic diagram of a circuit board structure provided with an acceleration sensor according to an embodiment of the present application; fig. 9 is a schematic diagram of a circuit board structure provided with a gravity/acceleration sensor according to an embodiment of the present application.
As described above, wherein:
1pin is a GND interface of an acceleration sensor and an NC interface of a gravity/acceleration sensor;
2pin is the Data interface of the acceleration sensor and the power interface of the gravity/acceleration sensor;
3pin is a power interface of the acceleration sensor and is a CLK interface of the gravity/acceleration sensor;
4pin is GND interface of acceleration sensor, and Data interface of gravity/acceleration sensor;
10pin is the CLK interface of the acceleration sensor and NC interface of the gravity/acceleration sensor.
For the acceleration sensors 11pin and 12pin, and for the gravity/acceleration sensors 11pin to 14pin, they may be provided directly separately, since their positions do not coincide with each other.
The ellipses on the circuit board traces in fig. 8 and fig. 9 indicate that the circuit board traces are omitted, and other traces may exist on the circuit board traces in practical applications, for example, traces are further routed through vias, and in the following, only the circuit board traces are taken as surface traces for illustration, and the technical scheme of the present application is not limited.
A chip resistor area is reserved on the circuit board in advance for each of 1pin and 10 pin. Wherein, the patch resistor area corresponding to 1pin is connected with GND wiring, and the ellipses in the figure indicate that the circuit board wiring connected with the patch resistor area corresponding to 1pin is omitted; the patch resistor area corresponding to 10pin is connected with the wiring of CLK, and the circuit board wiring connected with the patch resistor area corresponding to 10pin is omitted in the figure by ellipses.
Two chip resistor areas are reserved on the circuit board in advance for 2pin, 3pin and 4pin respectively. One patch electronic area corresponding to the 2pin is connected with the Data wiring, the other patch resistor area corresponding to the 2pin is connected with the power wiring, and the circuit board wiring connected with the patch resistor area corresponding to the 2pin is omitted in the figure by using an ellipsis; one patch electronic area corresponding to 3pin is connected with a power supply wire, the other patch resistor area corresponding to 3pin is connected with a CLK wire, and the circuit board wire connected with the patch resistor area corresponding to 3pin is omitted in the figure by ellipses; one patch electronic area corresponding to 4pin is connected with the GND wiring, the other patch resistor area corresponding to 4pin is connected with the Data wiring, and the circuit board wiring connected with the patch resistor area corresponding to 4pin is omitted in the figure by using ellipses.
When it is necessary to mount the acceleration sensor on the circuit board 10, 1-10pin, 15pin and 16pin in fig. 8 are used for corresponding connection with the pins of the acceleration sensor. Wherein, 15pin is used as NC pin and 16pin is used as enable pin.
And a zero ohm chip resistor is assembled on the chip resistor area of the 1pin so that the 1pin is connected with GND; a zero ohm chip resistor is assembled on a chip resistor area corresponding to 10pin, so that the 10pin is connected into CLK; a zero ohm chip resistor is assembled on a chip resistor area of the 2pin connection Data so that the 2pin is connected with the Data; a zero ohm chip resistor is assembled on a chip resistor area of a 3pin connection power supply so that the 3pin is connected into the power supply; and a zero ohm chip resistor is assembled on a chip resistor area of the 4pin connection GND so that the 4pin is connected with the GND.
In some embodiments, the zero ohm chip resistor may be a 01005 model zero ohm resistor, and the size specification is 0.4mm by 0.2mm, which is equivalent to a circuit board connection line.
Referring to fig. 10, an equivalent circuit diagram provided in an embodiment of the present application is shown.
Fig. 10 shows specific circuit connection patterns of 1pin, 2pin, 3pin, 4pin, and 10pin corresponding to fig. 8 at this time.
Therefore, the scheme provided by the embodiment of the application can realize the compatibility of the acceleration sensor.
When it is necessary to mount the gravity/acceleration sensor on the circuit board 10, 1-14pin in fig. 8 is used for corresponding connection with the pin of the gravity/acceleration sensor.
In addition, a zero ohm chip resistor is not assembled on the chip resistor area of the 1pin, so that the 1pin is suspended as an NC interface; zero ohm chip resistors are not assembled on the chip resistor areas corresponding to the 10 pins, so that the 10 pins serve as NC interfaces to be suspended; a zero ohm chip resistor is assembled on a chip resistor area of a 2pin connection power supply so that the 2pin is connected into the power supply; a zero ohm chip resistor is assembled on a chip resistor area of the 3pin connection CLK so that the 3pin is connected with the CLK; and (3) assembling a zero ohm chip resistor on the chip resistor area of the 4pin connection Data so as to enable the 4pin to be connected with the Data.
Referring to fig. 11, a high equivalent circuit diagram is provided for a second embodiment of the present application.
Fig. 11 shows specific circuit connection patterns of 1pin, 2pin, 3pin, 4pin, and 10pin corresponding to fig. 9 at this time.
Therefore, the scheme provided by the embodiment of the application can realize the compatibility of the gravity/acceleration sensor.
It will be understood that, in fig. 8 and fig. 9, the circuit board routing between each chip resistor area and pin may not be preset, and the circuit board routing may be set after the type of the chip to be mounted is determined.
In the above description, the first set of interfaces comprises interfaces 5 to 9, 11 to 16; the second set of interfaces comprises interfaces 1 and 10; the third set of interfaces comprises interfaces 2 to 4.
In practical application, one chip resistor needs two bonding pads to realize connection with a circuit board.
For each interface-connected chip resistor area of the second set of interfaces, including a first pad and a second pad. The first bonding pad is connected with one corresponding circuit board wiring, and the second bonding pad is connected with one corresponding interface. The first bonding pad is used for connecting the first end of the chip resistor when the chip resistor is assembled; the second bonding pad is used for connecting the second end of the patch resistor when the resistor is assembled.
For the chip resistor areas corresponding to 2pin, 3pin and 4pin, since the positions are reserved for the two chip resistors, when the bonding pads of the chip resistors are set, in some embodiments, the two chip resistor areas connected by each interface are a first chip resistor area and a second chip resistor area. The first chip resistor area is adjacent to the second chip resistor area. The first chip resistor area comprises a first bonding pad and a second bonding pad; the second chip resistor area includes a third pad and a fourth pad. The first bonding pad and the third bonding pad are respectively connected with one path of corresponding circuit board wiring, and the second bonding pad and the fourth bonding pad are jointly connected with one corresponding interface. The first bonding pad is used for being connected with the first end of the chip resistor when the chip resistor is assembled in the first chip resistor area and suspended when the chip resistor is assembled in the second chip resistor area. The second bonding pad is used for connecting the second end of the chip resistor when the chip resistor is assembled in the first chip resistor area and suspending when the chip resistor is assembled in the second chip resistor area. The third bonding pad is used for being connected with the first end of the chip resistor when the chip resistor is assembled in the second chip resistor area and suspended when the chip resistor is assembled in the first chip resistor area. The fourth bonding pad is used for connecting the second end of the chip resistor when the chip resistor is assembled in the second chip resistor area and suspending when the chip resistor is assembled in the first chip resistor area.
In other embodiments, a bond pad implementation may be used, considering that the zero ohm chip resistor acts as a circuit board connection and reduces the circuit board area footprint. The two chip resistor areas connected with each interface in the third group of interfaces are a first chip resistor area and a second chip resistor area. The first chip resistor area and the second chip resistor area are adjacent and share a common bonding pad. The first chip resistor area further includes a first bonding pad, and the second chip resistor area further includes a second bonding pad. The first bonding pad and the second bonding pad are respectively connected with one corresponding circuit board wiring, and the common bonding pad is connected with one corresponding interface. The first bonding pad is used for connecting the first end of the chip resistor when the chip resistor is assembled in the first chip resistor area and suspending when the chip resistor is assembled in the second chip resistor area; the second bonding pad is used for connecting the first end of the chip resistor when the chip resistor is assembled in the second chip resistor area and suspending when the chip resistor is assembled in the first chip resistor area; the common bonding pad is used for connecting the second end of the chip resistor when the first chip resistor area is assembled with the chip resistor, and connecting the second end of the chip resistor when the second chip resistor area is assembled with the chip resistor.
Taking two chip resistor areas corresponding to 2 pins as an example for explanation, when an implementation mode of stacked bonding pads is adopted, the stacked bonding pads comprise a first bonding pad, a second bonding pad and a common bonding pad, the common bonding pad is connected with an interface corresponding to the 2 pins, the first bonding pad is connected with Data, and the second bonding pad is connected with a power supply. When the circuit board is assembled with the acceleration sensor, the first bonding pad and the common bonding pad are used for assembling a zero ohm chip resistor, and the second bonding pad is suspended; when the circuit board is assembled with the gravity/acceleration sensor, the second bonding pad and the common bonding pad are used for assembling the zero ohm chip resistor, and the first bonding pad is suspended. When the four-pad implementation mode is adopted, the four-pad implementation mode comprises a first pad, a second pad, a third pad and a fourth pad, the second pad and the fourth pad are connected with interfaces corresponding to 2 pins, the first pad is connected with Data, and the third pad is connected with a power supply. When the circuit board is assembled with the acceleration sensor, the first bonding pad and the second bonding pad are used for assembling a zero ohm chip resistor, and the third bonding pad and the fourth bonding pad are suspended; when the circuit board is assembled with the gravity/acceleration sensor, the third bonding pad and the fourth bonding pad are used for assembling the zero-ohm chip resistor, and the first bonding pad and the second bonding pad are suspended.
In summary, the solution provided by the embodiment of the present application enables the circuit board structure to support two different sensors in a compatible manner, and does not need to reserve assembly positions for two types of chip packages at the same time. The pin with the same functions of the two types of chip packages is subjected to compatible design by utilizing the first group of interfaces, the pin with different functions is subjected to compatible design by utilizing the second group of interfaces and the third group of interfaces, and gating is realized by using the chip resistor, so that the layout area of the circuit board is occupied, and the feasibility of compatibility of the two types of chips is improved, so that the area of the circuit board is effectively utilized.
It can be understood that the implementation manner that the circuit board can be compatible with the acceleration sensor and the gravity/acceleration sensor is only one application scenario of the technical scheme of the present application, and the scheme of the present application can also be applied in other scenarios, namely, scenarios that require that the circuit board can be compatible with a chip having a certain similarity between functions and hardware pins.
For example, in some embodiments, a compatible design between a universal flash memory (Universal Flash Storage, UFS) and an embedded multimedia card (Embedded Multimedia Card, eMMC) may be implemented; in other embodiments, fuel gauge chips that are compatible with different manufacturers may be used to determine the remaining power of the battery. When the technical scheme provided by the application is applied to different scenes, pins with the same functions are directly compatible, the pins with different functions are gated through zero European resistor, and the specific principle is the same as that described above and is not repeated here.
Based on the chip system provided by the above embodiment, the embodiment of the application further provides a chip system, and the following detailed description is given with reference to the accompanying drawings.
See also fig. 12A and 12B. Fig. 12A is a schematic diagram of a chip system according to an embodiment of the present application; fig. 12B is a schematic diagram of another chip system according to an embodiment of the present application.
The chip system 120 in fig. 12A includes a circuit board structure 30 and a first type of chip package 31.
Wherein, when the first type chip package 31 is assembled, the pin interfaces 1 to 10, 15 and 16 of the circuit board structure 30 are respectively connected with pins of the first type chip package 31.
The chip system 120 in fig. 12B includes a circuit board structure 30 and a second type of chip package 32.
When the first type chip package 32 is assembled on the circuit board structure 30, the pin interfaces 1 to 14 of the circuit board structure 30 are respectively connected with pins of the second type chip package 32.
For the specific implementation and design process of the circuit board structure 30, reference should be made to the description of the above embodiments, and the description of the embodiments of the present application is omitted here.
In fig. 12A and 12B, the first type chip package 31 is taken as an acceleration sensor, and the second type chip package 32 is taken as a gravity/acceleration sensor as an example. When the first type chip package 31 and the second type chip package 32 are of other types, the design layout of the chip system is adjusted accordingly, and the embodiments of the present application will not be described in detail.
In summary, the circuit board structure of the chip system can compatibly support two different chip packages, and the assembly positions do not need to be reserved for the two types of chip packages at the same time. Specifically, for the pin with the same functions of the two types of chip packages, the first group of interfaces is utilized to realize compatible design, for the pin with different functions, the second group of interfaces and the third group of interfaces are utilized to realize compatible design, and the strobe is realized through the chip resistor, so that the layout area of the circuit board is occupied, the feasibility of the compatibility of the two types of chips is improved, the area of the circuit board is effectively utilized, and the area occupied by a chip system is reduced.
Based on the chip system provided by the above embodiment, the embodiment of the application further provides an electronic device, and the following detailed description is given with reference to the accompanying drawings.
Referring to fig. 13, a schematic diagram of an electronic device according to an embodiment of the present application is shown.
The electronic device 130 provided in the embodiment of the present application includes the chip system 120 described in the above embodiment.
The chip system 120 includes a circuit board structure and a chip package.
The chip package is a first type chip package or a second type chip package. The embodiment of the application does not limit the specific types of the first type chip package and the second type chip package.
In one possible implementation, the first type of chip package acceleration sensor and the second type of chip package integrate sensors of the function of gravity sensor and of the function of acceleration sensor; in another possible implementation manner, the first type of chip package is a general flash memory, and the second type of chip package is an embedded multimedia card; in yet another possible implementation, the first type of chip package and the second type of chip package are each different types of fuel gauge chips.
For a specific implementation of the circuit board structure chip system, reference may be made to the related description in the above embodiments, and the embodiments of the present application are not described herein again.
The electronic device may be a mobile phone, a notebook computer, a wearable electronic device (such as a smart watch), a tablet computer, an augmented reality device, a virtual reality device, a vehicle-mounted device, and the like, which is not particularly limited.
In summary, the circuit board structure of the chip system can compatibly support two different chip packages, and the assembly positions do not need to be reserved for the two types of chip packages at the same time. Specifically, for the pins with the same functions of the two types of chip packages, the first group of interfaces are utilized to realize compatible design, for the pins with different functions, the second group of interfaces and the third group of interfaces are utilized to realize compatible design, and the strobe is realized through the chip resistor, so that the layout area of the circuit board is occupied, the feasibility of the compatibility of the two types of chips is improved, the area of the circuit board is effectively utilized, and the electronic equipment is convenient to realize the high-density layout of devices.
It should be understood that in the present application, "at least one (item)" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. The circuit board assembly is characterized by comprising a circuit board, a first group of interfaces, a second group of interfaces, a third group of interfaces and at least two chip resistor areas, wherein the first group of interfaces, the second group of interfaces, the third group of interfaces and the at least two chip resistor areas are arranged on the circuit board; wherein,
the first set of interfaces comprises at least two interfaces, and the at least two interfaces are respectively and directly connected with one corresponding circuit board wiring;
the second set of interfaces comprises at least one interface, and at least one interface in the second set of interfaces is respectively connected with one chip resistor area;
the third set of interfaces comprises at least one interface, and at least one interface in the third set of interfaces is connected with two patch resistor areas;
And the other end of each chip resistor area, which is not connected with the interface, is directly connected with one corresponding circuit board wiring.
2. The circuit board assembly of claim 1, wherein the at least two chip resistor areas comprise a first set of chip resistor areas and a second set of chip resistor areas,
when the circuit board assembly is used for assembling a first type of chip packaging body, each chip resistor area in the first group of chip resistor areas is used for setting one chip resistor, and each chip resistor area in the second group of chip resistor areas is used for being free;
when the circuit board assembly is used for assembling the second-type chip package, each chip resistor area in the second group of chip resistor areas is used for setting one chip resistor, and each chip resistor area in the first group of chip resistor areas is used for being free.
3. The circuit board assembly according to claim 1 or 2, wherein the chip resistor area to which at least one interface of the second set of interfaces is connected respectively comprises a first pad and a second pad;
the first bonding pad is connected with one path of corresponding circuit board wiring, and the second bonding pad is connected with one corresponding interface;
when the chip resistor is assembled by the circuit board assembly, the first bonding pad is used for being connected with the first end of the chip resistor;
The second bonding pad is used for being connected with the second end of the chip resistor.
4. The circuit board assembly of claim 1, wherein the two chip resistor areas to which at least one interface of the third set of interfaces is respectively connected include a first chip resistor area and a second chip resistor area;
the first chip resistor area comprises a first bonding pad and a second bonding pad;
the second chip resistor area comprises a third bonding pad and a fourth bonding pad;
the first bonding pad and the third bonding pad are respectively connected with one path of corresponding circuit board wiring, and the second bonding pad and the fourth bonding pad are jointly connected with one corresponding interface;
the first bonding pad is used for connecting the first end of the chip resistor when the first chip resistor area is assembled with the chip resistor, and suspending when the second chip resistor area is assembled with the chip resistor;
the second bonding pad is used for connecting the second end of the chip resistor when the first chip resistor area is assembled with the chip resistor, and suspending when the second chip resistor area is assembled with the chip resistor;
the third bonding pad is used for connecting the first end of the chip resistor when the second chip resistor area is assembled with the chip resistor, and suspending when the first chip resistor area is assembled with the chip resistor;
The fourth bonding pad is used for connecting the second end of the chip resistor when the second chip resistor area is assembled with the chip resistor, and suspending when the first chip resistor area is assembled with the chip resistor.
5. The circuit board assembly of claim 1, wherein the two chip resistor areas connected by each interface in the third set of interfaces are a first chip resistor area and a second chip resistor area;
the first chip resistor area and the second chip resistor area are adjacent and share a common bonding pad;
the first chip resistor area further comprises a first bonding pad, and the second chip resistor area further comprises a second bonding pad;
the first bonding pad and the second bonding pad are respectively connected with one path of corresponding circuit board wiring, and the common bonding pad is connected with one corresponding interface;
the first bonding pad is used for connecting the first end of the chip resistor when the first chip resistor area is assembled with the chip resistor, and suspending when the second chip resistor area is assembled with the chip resistor;
the second bonding pad is used for connecting the first end of the chip resistor when the second chip resistor area is assembled with the chip resistor, and suspending when the first chip resistor area is assembled with the chip resistor;
The common bonding pad is used for connecting the second end of the chip resistor when the first chip resistor area is assembled with the chip resistor, and connecting the second end of the chip resistor when the second chip resistor area is assembled with the chip resistor.
6. The circuit board assembly of any one of claims 1 to 5, wherein the chip resistor is a zero ohm chip resistor.
7. The circuit board assembly of claim 6, wherein the first type of chip package is an acceleration sensor and the second type of chip package is a sensor integrated with a function of a gravity sensor and a function of an acceleration sensor.
8. The circuit board assembly of claim 6, wherein the first type of chip package is a universal flash memory UFS and the second type of chip package is an embedded multimedia card eMMC.
9. The circuit board assembly of claim 5, wherein the first type of chip package and the second type of chip package are each different types of fuel gauge chips.
10. An electronic device comprising the circuit board assembly of any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202310920981.0A CN117042292A (en) | 2022-03-28 | 2022-03-28 | Circuit board structure, chip system and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210310923.1A CN115529724B (en) | 2022-03-28 | 2022-03-28 | Circuit board structure, chip system and electronic equipment |
| CN202310920981.0A CN117042292A (en) | 2022-03-28 | 2022-03-28 | Circuit board structure, chip system and electronic equipment |
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| CN202210310923.1A Division CN115529724B (en) | 2022-03-28 | 2022-03-28 | Circuit board structure, chip system and electronic equipment |
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| CN116933720B (en) * | 2023-09-18 | 2023-12-12 | 成都电科星拓科技有限公司 | Method and circuit compatible with different voltage chip designs packaged in same way |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5061825A (en) * | 1990-10-03 | 1991-10-29 | Chips And Technologies, Inc. | Printed circuit board design for multiple versions of integrated circuit device |
| JP2007317848A (en) * | 2006-05-25 | 2007-12-06 | Nec Corp | Component mounting board |
| CN201018713Y (en) * | 2007-03-28 | 2008-02-06 | 青岛海信电器股份有限公司 | Circuit composing structure for compatibility of multiple same types function chip |
| CN101460007B (en) * | 2007-12-12 | 2011-03-23 | 扬智科技股份有限公司 | Circuit board |
| JP5260271B2 (en) * | 2008-12-26 | 2013-08-14 | 東芝シュネデール・インバータ株式会社 | Circuit device using chip parts |
| CN201956344U (en) * | 2010-12-17 | 2011-08-31 | 厦门基德显示器件有限公司 | Compatible packaging structure of driving bare chip and patch |
| CN102076167B (en) * | 2011-01-11 | 2012-07-04 | 惠州Tcl移动通信有限公司 | Mobile phone circuit board |
| CN104092476B (en) * | 2014-05-27 | 2017-06-13 | 西安中兴新软件有限责任公司 | A kind of compatible circuit and terminal |
| CN106061109B (en) * | 2016-08-15 | 2018-09-11 | 深圳市明泰电讯有限公司 | A kind of circuit board and its circuit of crystal compatibility |
| CN107197595B (en) * | 2017-05-16 | 2021-09-07 | 晶晨半导体(上海)股份有限公司 | Printed circuit board and welding design thereof |
| CN108668434A (en) * | 2018-06-22 | 2018-10-16 | 晶晨半导体（深圳）有限公司 | Without branch's alternative resistance circuit plate and electronic device |
| CN210202180U (en) * | 2019-04-03 | 2020-03-27 | 厦门汉印电子技术有限公司 | PCB and electronic equipment |
| CN110933838B (en) * | 2019-12-05 | 2021-01-05 | 捷开通讯(深圳)有限公司 | Radio frequency circuit and circuit layout structure thereof |
| CN216057634U (en) * | 2021-09-14 | 2022-03-15 | 深圳微步信息股份有限公司 | PCB compatible with two data transmission interfaces |
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