CN1170396C - Network processor system for supporting QoS based on FPGA and data packages processing method - Google Patents
Network processor system for supporting QoS based on FPGA and data packages processing method Download PDFInfo
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Abstract
The present invention relates to a network processor system for supporting QoS based on FPGA and a data package processing method, which belongs to the technical field of IP. The present invention is characterized in that the network processor system is realized by FPGA; the network processor system contains link layer processing circuits mutually connected with a plurality of Ethernet controllers, a package head processing circuit connected with the link layer processing circuits at the input end, finding circuits simultaneously and mutually connected with the link layer processing circuits and the package head processing circuit, an input queue circuit, a dispatch circuit and a switching network interface which are orderly connected with the package head processing circuit, an output queue circuit, a package transmitting circuit orderly connected with the output end of the switching network interface, a universal CPU interface externally connected and respectively connected with the package head processing circuit, the finding circuits and the package transmitting circuit, an interface between each finding circuit and TCAM externally connected, and a plurality of queues of FIFO memory interfaces and switching network interfaces respectively arranged at the input queue circuit and the output queue circuit and between the memorizers externally connected with the input queue circuit and the output queue circuit. The network processor system can quickly process IP packages and simultaneously support IP QoS.
Description
Technical field
Support service quality (QoS) based on field programmable gate array (FPGA) belongs to IP service quality technical field with network processor system and data package processing method.
Background technology
Network processing unit combines the advantage of ASIC(Application Specific Integrated Circuit) (ASIC) and universal cpu, has construction cycle that can shorten router and the advantage that prolongs the life cycle of router, is the important composition unit of router.A lot of manufacturers have all released the network processing unit product, and they have all realized the basic function of network processing unit, comprising: the processing in IP packet header, and route querying, IP wraps buffer memory, scheduling etc.There are some network processing units can carry out the buffer memory and the scheduling of a plurality of formations, carry out the classification of IP bag, but the method that they are handled have following shortcoming:
1) efficient of sorting algorithm is not high, can not classify to each IP bag of high-speed interface:
2) queue management mode efficient is not high.
Summary of the invention
The objective of the invention is to from hardware point of view propose a kind of can carry out high speed processing based on the support service quality (QoS) of FPGA with network processor system and data package processing method.This network processing unit function comprises: link layer process, handle in IP packet header, route querying, IP wraps classification, the IP bag buffer memory of many formations, input queue and scheduling, output work queue and scheduling, the treatment circuit of light carrier level signal 48 (OC-48) interface or light carrier level signal 12 (OC-12) interface or light carrier level signal 3 (OC-3) interface is provided, the gigabit ethernet interface treatment circuit, a kind of or several combination arbitrarily in ten thousand mbit ethernet interface treatment circuits and the 100 m ethernet interface treatment circuit.The switching network interface is provided.
The network processor system that the present invention proposes is characterized in that: it contains the following circuit that all is made on a slice field programmable gate array (FPGA):
Link layer process circuit (1-1) with a plurality of ethernet controller interconnection;
Receive the packet header treatment circuit (1-2) of the IP bag after classification is handled from above-mentioned link layer process circuit (1-1);
Search circuit (1-3), it is protocol detection and route control circuit, receives the header packet information of packet header treatment circuit (1-2), carries out route querying and IP bag classification searching in view of the above, and returns lookup result; The ARP(Address Resolution Protocol) that receives link layer process circuit (1-1) transmission is searched and the ARP(Address Resolution Protocol) refresh requests, and return address analysis protocol (ARP) lookup result;
Input rank circuit (1-4), it is a kind of memorizer buffer and control circuit, receives the IP bag of packet header treatment circuit (1-2) transmission and is cached to external many formations first in first out (FIFO) memory one by many formations first in first out (FIFO) memory interface one (1-10); After the request that receives dispatch circuit, the IP bag is read from buffer memory;
Dispatch circuit (1-5), it is a kind of selector circuit, select specific I P bag according to the state that external exchange mechanism chip sends by the switching network interface, and to this IP bag of input rank circuit (1-4) request acquisition, after receiving the IP bag of input rank circuit (1-4), this IP bag is sent by switching network interface (1-12);
Switching network interface (1-12), it is a kind of bidirectional high speed parallel interface, send IP bag to external exchange mechanism chip, receives the IP bag from external exchange mechanism chip simultaneously, and this IP bag is sent to output queue circuit (1-6);
Output queue circuit (1-6), it is a kind of memorizer buffer and control circuit, and the IP bag of sending from switching network interface (1-12) is cached to external many formations first in first out (FIFO) memory two by many formations first in first out (FIFO) memory interface two (1-11); After the request that receives the bag transtation mission circuit, this IP bag is read from buffer memory, sent to bag transtation mission circuit (1-7);
Bag transtation mission circuit (1-7), it is selection and control circuit on the network processing unit sending direction, receives that the IP bag back that output queue circuit (1-6) sends sends to link layer process circuit (1-1) to it;
The cpu i/f of external universal cpu (1-8), it is a control circuit of being responsible for network processing unit and its outer CPU both-way communication, it and outside universal cpu communication, the IP bag is sent to bag transtation mission circuit (1-8), receive the IP bag from packet header treatment circuit (1-2), and send routing table and the order of classifying rules bank refresh to searching circuit (1-3);
Ternary Content Addressable Memory (TCAM) interface (1-9), it is the circuit that network processing unit connects outside Ternary Content Addressable Memory (TCAM) and realizes Ternary Content Addressable Memory (TCAM) is controlled, through Ternary Content Addressable Memory (TCAM) interface (1-9) with search circuit (1-3) interconnection, make and search circuit, realize route querying, IP classification and ARP(Address Resolution Protocol) locating function simultaneously by external Ternary Content Addressable Memory (TCAM) chip (4-2) and synchronous static memory (SSRAM) chip (4-3) of its visit; Wherein, external synchronous static memory (SSRAM) is linked to each other with network processing unit by the data wire of Ternary Content Addressable Memory (TCAM) control and synchronous static memory (SSRAM).
Described link layer process circuit (1-1) is a kind of or several combination arbitrarily in light carrier level signal 48 (OC-48) interface link layer treatment circuit, light carrier level signal 12 (OC-12) interface link layer treatment circuit, light carrier level signal 3 (OC-3) interface link layer treatment circuit, gigabit ethernet interface treatment circuit, ten thousand mbit ethernet interface treatment circuits, the 100 m ethernet interface treatment circuit.
Described exchange mechanism interface is any among chip VSC870, VSC871, the VSC872;
The described circuit of searching contains: control circuit module (4-1), with the two-way Ternary Content Addressable Memory that is connected of this control circuit module (TCAM) (4-2), and input is connected with Ternary Content Addressable Memory (TCAM) output and with the two-way synchronous static memory that is connected of this control circuit module (SSRAM) (4-3); Wherein control circuit module (4-1) contains: input respectively with packet packet header receiving interface, ARP(Address Resolution Protocol) is searched receiving interface, the function selector circuit that the ARP(Address Resolution Protocol) refresh interface links to each other and is used for dispatching, input termination routing table is with classifying rules bank refresh interface and output selects circuit to link to each other with aforesaid operations so that the refresh command that handle receives resolves into the instruction decomposition circuit of microcommand, be used for the aging request of ARP(Address Resolution Protocol) counting circuit to the aging request signal of above-mentioned instruction decomposition circuit OPADD analysis protocol (ARP) table, input links to each other with function selector circuit and the continuous ARP(Address Resolution Protocol) refresh control circuit of output and instruction decomposition circuit, input links to each other with the function selector circuit output and Ternary Content Addressable Memory (TCAM) control circuit that output links to each other with Ternary Content Addressable Memory (TCAM) input, I/O is connected and Ternary Content Addressable Memory (TCAM) output links to each other and output links to each other with function selector circuit searches data receiver circuit with synchronous static memory (SSRAM), input respectively with the above-mentioned data receiver circuit of searching, function selector circuit link to each other and output respectively with the ARP(Address Resolution Protocol) refresh control circuit, route querying and IP bag classification results transmission interface, ARP(Address Resolution Protocol) lookup result transmission interface links to each other searches data processing circuit.
The data package processing method that the present invention proposes is characterized in that:
The packet that described link layer process circuit (1-1) receives is an ethernet frame, distinguishes IP bag and ARP(Address Resolution Protocol) bag according to the type field value of ethernet frame format; If the IP bag then removes the frame head of the ethernet frame of packet and postamble, obtain the IP bag, send to the packet header treatment circuit; If the ARP(Address Resolution Protocol) request package after carrying out the ARP(Address Resolution Protocol) protocol processes, sends ARP(Address Resolution Protocol) and sends bag, and send the ARP(Address Resolution Protocol) updating message to searching circuit; If the ARP(Address Resolution Protocol) response packet sends the ARP(Address Resolution Protocol) updating message to searching circuit.
Described lookup method, it contains following steps successively:
(1) receive following data packet head information and buffer memory:
IP header packet information, TCP (transmission control protocol) header packet information or UDP (user datagram) header packet information;
The message in routing table and classifying rules storehouse is refreshed in the IP address that receiver address analysis protocol (ARP) (address resolution protocol) is searched, the ethernet address of refresh address analysis protocol (ARP) table and IP address to and buffer memory;
(2) make and search internal system and regularly produce the aging message of an ARP(Address Resolution Protocol) table;
(3) message and the aging message of above-mentioned ARP(Address Resolution Protocol) table that receive are done following combined treatment:
(3.1) the message that refreshes routing table and classifying rules storehouse, the message that above-mentioned ARP(Address Resolution Protocol) table is aging is decomposed into the microcommand message and the buffer memory of specific format separately;
(3.2) carry out different operating procedures respectively by following concrete condition:
When being in effective status searching the signal that internal system regularly is provided with, and when having specific format microcommand message to exist, just choose this specific format microcommand message correspondence search in the system Ternary Content Addressable Memory (TCAM) (4-2), and synchronous static memory (SSRAM) (4-3) is done read-write operation by Ternary Content Addressable Memory (TCAM);
When existing the packet header packet information when (comprising IP header packet information, TCP header packet information, UDP header packet information), choose the packet header packet information to do the search operation of route querying, the classification of IP bag by Ternary Content Addressable Memory (TCAM) and synchronous static memory (SSRAM);
When existence was used to carry out IP address that ARP(Address Resolution Protocol) searches, the ARP(Address Resolution Protocol) search operation was done by Ternary Content Addressable Memory (TCAM) and synchronous static memory (SSRAM) in the IP address of just choosing ARP(Address Resolution Protocol) to search;
When existence be used for the external ethernet address of refresh address analysis protocol (ARP) table and IP address to the time, just choose the ethernet address that is used for refresh address analysis protocol (ARP) table and IP address to do the search operation that refresh address analysis protocol (ARP) is shown by Ternary Content Addressable Memory (TCAM) and synchronous static memory (SSRAM).
Externally send the result that route querying, the classification of IP bag and ARP(Address Resolution Protocol) are searched;
Experimental results show that it can finish above-mentioned network processes function at a high speed.
Description of drawings:
Fig. 1. the block diagram of network processor system.
Fig. 2. the connection layout of network processor system and external chip.
Search the function diagram of circuit (1-3) among Fig. 3 network processor system Fig. 1.
Search the physical connection figure of circuit (1-3) among Fig. 4 network processor system Fig. 1.
The cut-away view of (4-1) among Fig. 5 Fig. 4.
Embodiment
Network processing unit architecture of the present invention mainly is made up of following several circuit and interface as shown in Figure 1:
1. link layer process circuit (1-1): this circuit is handled ethernet frame, realizes second layer control protocol (wherein the ARP(Address Resolution Protocol) matrix section is realized by searching circuit (1-3)).Because the outside can connect a plurality of gigabit ethernet interface controllers, this circuit also will be realized data multiplexing and shunt function.
2. packet header treatment circuit (1-2): the processing of carrying out IP packet header (is carried out the verification of IP packet header, check the time to live of IP bag and it is subtracted one), propose the request of route querying and IP bag classification simultaneously, according to the result IP bag is sent to cpu i/f (1-8) or sends to input rank circuit (1-4) and carry out buffer memory.
3. search circuit (1-3): search circuit and finish route querying, the classification of IP bag, ARP(Address Resolution Protocol) table function, for software provides the interface that refreshes routing table and classifying rules storehouse, search circuit and use Ternary Content Addressable Memory (TCAM) to realize route querying, the classification of IP bag and ARP(Address Resolution Protocol) locating function simultaneously.
4. input rank circuit (1-4): this circuit uses many formations first in first out (FIFO) memory that the IP bag is imported many formations buffer memory.
5. dispatch circuit (1-5): this circuit is realized multiqueue dispatching's function, realize the nearly scheduling of 64 formations, adopt the static priority of request-reply formula to support different service quality with the scheduling strategy (also can adopt other to support the scheduling strategy of QoS) that poll combines.
6. output queue circuit (1-6): this circuit uses many formations first in first out (FIFO) memory to carry out by output physical port to carry out IP bag output work queue's buffer memory and scheduling.
7. wrap transtation mission circuit (1-7): send IP and wrap the link layer process circuit, the IP bag that sends from this machine also sends by cpu i/f (1-8) bag transtation mission circuit.
8.CPU interface (1-8): the interface of network processing unit and other general processor communication, the IP that receives this machine by this interface wraps, and sends the IP bag from this machine, refreshes routing table and rule base.
9. Ternary Content Addressable Memory (TCAM) interface (1-9): the interface of Ternary Content Addressable Memory (TCAM) memory that network processing unit externally connects, search circuit by this interface accessing Ternary Content Addressable Memory (TCAM) memory and synchronous static memory (SSRAM) memory.
10. many formations first in first out (FIFO) memory interface one (1-10): one of memory interface that network processing unit is external, the input rank circuit is by this many formations of interface accessing first in first out (FIFO) memory.
11. many formations first in first out (FIFO) memory interface two (1-11): two of the memory interface that network processing unit is external, output queue circuit (1-6) is by this many formations of interface accessing first in first out (FIFO) memory.
12. switching network interface (1-12): the interface of network processing unit and switching network communication.
The annexation of above-mentioned each circuit is: link layer process circuit (1-1) receives the packet that the network processing unit external chip sends, send the IP bag to packet header treatment circuit (1-2), search the request that refreshes with ARP(Address Resolution Protocol) to searching circuit (1-3) transmission ARP(Address Resolution Protocol), and the ARP(Address Resolution Protocol) lookup result that circuit (1-3) returns is searched in reception.Packet header treatment circuit (1-2) sends route querying and the classification request of IP bag and receives route querying and the IP bag classification results that (1-3) returns to searching circuit (1-3), sends route querying and IP bag classification results and IP bag to input rank circuit (1-4).Search circuit (1-3) and finish route querying, the classification of IP bag and ARP(Address Resolution Protocol) table function by Ternary Content Addressable Memory (TCAM) interface circuit (1-9).What input rank circuit (1-4) control many formations first in first out (FIFO) memory interface one (1-10) finished the IP bag goes into formation and dequeue operation, sends the IP bag according to the request of dispatch circuit (1-5).The IP of switching network interface (1-12) receiving scheduling circuit (1-5) wraps, and they are sent to the exchange mechanism chip of network processing unit outside, receives the IP bag from the exchange mechanism chip and sends to output queue circuit (1-6).What output queue circuit (1-6) control many formations first in first out (FIFO) memory interface two (1-11) finished the IP bag goes into formation and dequeue operation, and sends the IP bag to bag transtation mission circuit (1-7).Bag transtation mission circuit (1-7) sends to link layer process circuit (1-1) with the IP bag.Data link layer deals circuit (1-1) sends to packet the ethernet controller chip of network processing unit outside.The outside universal cpu communication of cpu i/f and network processing unit sends to bag transtation mission circuit (1-7) with the IP bag, receives the IP bag from packet header treatment circuit (1-2), and sends routing table and the order of classifying rules bank refresh to searching circuit (1-3).
Network processing unit of the present invention need cooperate other chip to use, and it is connected as shown in Figure 2 with other chip, and wherein the name of each several part is called:
1. network processing unit (2-1): main contents of the present invention, can pass through field programmable gate array (FPGA) and realize.
2.TCAM chip (2-2): the memory of content addressable.
3.SSRAM chip (2-3): synchronous static memory.
4. many formations first in first out (FIFO) memory one (2-4): as the input rank buffer memory, use a kind of many formations first in first out (FIFO) memory, finish the function of first in first out (FIFO) in memory chip inside.
5. many formations first in first out (FIFO) memory two (2-5): as the output queue buffer memory, use a kind of many formations first in first out (FIFO) memory, finish the function of first in first out (FIFO) in memory chip inside.
6. exchange mechanism chip (2-6): the switching network chip, can adopt the VSC870/VSC871/VSC872 of Vitesse company chip.
7. universal cpu (2-7): with the CPU of network processing unit communication.
8. ethernet controller (2-8): to network processing unit transceive data bag, a network processing unit links to each other with two or more ethernet controllers.
The annexation of above-mentioned each chip is: ethernet controller (2-8) sends packet to network processing unit (2-1), receives the packet from network processing unit simultaneously, and a network processing unit links to each other with two ethernet controllers.Ternary Content Addressable Memory (TCAM) (2-2) is subjected to the control of network processing unit (2-1), finishes read-write and locating function.Synchronous static memory (SSRAM) (2-3) is subjected to Ternary Content Addressable Memory (TCAM) control (2-2), but data wire and network processing unit link.Many formations first in first out (FIFO) memory one (2-4) and many formations first in first out (FIFO) memory two (2-5) are subjected to the control of network processing unit.Exchange mechanism chip (2-6) links to each other with network processing unit, and bag can transmit and receive data mutually.Universal cpu (2-7) links to each other with network processing unit, and it sends packet to network processing unit, receives packet from network processing unit, sends routing table and classifying rules refresh command simultaneously.
The processing procedure that the present invention relates to comprises: to the processing procedure of IP bag, and to the processing procedure of address resolution protocol (ARP) bag, the refresh process of routing table and rule base, their detailed process is as follows.
1. the method for link layer process circuit region divided data bag
The packet that the link layer process circuit receives is an Ether frame, IP and ARP(Address Resolution Protocol) bag all are encapsulated in ethernet frame the inside, a type field by ethernet frame is distinguished, if planting, type field is 0X0800, this packet is exactly the IP bag so, be 0X0806 if type field is planted, this packet is exactly the ARP(Address Resolution Protocol) bag so.
2. to the processor process of IP bag
Deliver to the IP bag of network processing unit is handled by link layer process circuit (1-1) from ethernet controller (2-8), link layer process circuit (1-1) is disposed the head of ethernet frame, two paths of data is multiplexed into one the tunnel, gives packet header treatment circuit (1-2) with the IP packet format.Packet header treatment circuit (1-2) carries out IP verification, header packet information is sent to search circuit (1-3) simultaneously, and etc. the result of circuit to be found (1-3).Search circuit (1-3) by Ternary Content Addressable Memory (TCAM) interface (1-9) visit Ternary Content Addressable Memory (TCAM) chip (2-2) and synchronous static memory (SSRAM) chip (2-3), carry out the classification of IP bag earlier, carry out route querying then, route querying and IP bag sorting result are returned to packet header treatment circuit (1-2).After packet header treatment circuit (1-2) is received and searched sorting result,, the IP bag is passed to this machine or delivered to input rank circuit (1-4) by cpu i/f (1-8) the front that the result is attached to the IP bag.Input rank circuit (1-4) wraps IP by many formations FIFO memory interface one (1-10) circuit according to the priority of IP bag and output port and delivers to many formations FIFO memory one (2-4) and carry out buffer memory, dispatch circuit (1-5) is according to the situation of input rank and switching network, the scheduling strategy scheduling IP bag that adopts static priority to combine with poll, take out the IP bag from input rank circuit (1-4), send to exchange mechanism chip (2-6) through switching network interface (1-12).
IP bag from exchange mechanism chip (2-6) to network processing unit is sent to output queue circuit (1-6) through switching network interface (1-12).Output queue circuit (1-6) is delivered to many formation FIFO memory two (2-5) by many formations FIFO memory interface two (1-11) circuit with the IP bag according to the priority of IP bag and transmit port and is carried out buffer memory, and bag transtation mission circuit (1-7) sends to link layer process circuit (1-1) with the IP bag from output queue circuit (1-6) taking-up.Link layer process circuit (1-1) proposes the ARP(Address Resolution Protocol) search request to searching circuit (1-3), and waits for lookup result.Search circuit (1-3) by Ternary Content Addressable Memory (TCAM) interface (1-9) visit Ternary Content Addressable Memory (TCAM) chip (2-2) and synchronous static memory (SSRAM) chip (2-3) executive address analysis protocol (ARP) search operation, give link layer process circuit (1-1) lookup result.If search failure, link layer process circuit (1-1) abandons the IP bag, and sends the ARP(Address Resolution Protocol) request package; If search successfully, link layer process circuit (1-1) is sealed IP to install to and is sent to ethernet controller (2-8) in the ethernet frame.
3. to the processing procedure of address resolution protocol (ARP) bag
If ethernet controller (2-8) sends the ARP(Address Resolution Protocol) request package to network processing unit, link layer process circuit (1-1) receives this number pick bag, the ARP(Address Resolution Protocol) protocol processes of carrying out in link layer process circuit (1-1) inside, if the purpose of ARP(Address Resolution Protocol) request is the port address, then send the ARP(Address Resolution Protocol) response packet to ethernet controller (2-8), send the order of scheduler analysis protocol (ARP) table to searching circuit (1-3) simultaneously, search circuit (1-3) by Ternary Content Addressable Memory (TCAM) interface (1-9) visit Ternary Content Addressable Memory (TCAM) chip (2-2) and synchronous static memory (SSRAM) chip (2-3), scheduler analysis protocol (ARP) table.
If ethernet controller (2-8) sends the ARP(Address Resolution Protocol) response packet to network processing unit, link layer process circuit (1-1) calculated address analysis protocol (ARP) update command, search circuit (1-3) by Ternary Content Addressable Memory (TCAM) interface (1-9) visit Ternary Content Addressable Memory (TCAM) chip (2-2) and synchronous static memory (SSRAM) chip (2-3), scheduler analysis protocol (ARP) table.
4. the refresh process of routing table and rule base
Universal cpu (2-7) sends the refresh command of routing table and rule base to network processing unit, after cpu i/f in the network processing unit (1-8) receives refresh command, refresh command sent to search circuit (1-3), search circuit (1-3) and refresh routing table and classifying rules storehouse by Ternary Content Addressable Memory (TCAM) interface (1-9) visit Ternary Content Addressable Memory (TCAM) chip (2-2) and synchronous static memory (SSRAM) chip (2-3).
The present invention proposes a kind of system of network processing unit, can carry out IP bag processing fast, can support IP service quality (QoS) simultaneously, and this architecture needs finish above-mentioned function with other chips incorporate.Its advantage is: 1. finishes IP packet header by a network processor chip and handles, and route querying, IP wraps classification, the buffer memory of many formations and scheduling, the processing of link layer.2. network processing unit externally provides specific interface, comprise: gigabit ethernet interface, Ternary Content Addressable Memory (TCAM) and synchronous static memory (synchronous static memory (SSRAM)) interface, dual-ported memory interface, the switching network interface, cpu i/f.Link to each other with other chip by these interfaces, finish the function of network processing unit.3. adopt Ternary Content Addressable Memory (Ternary Content Addressable Memory (TCAM)) to realize route querying, the classification of IP bag and ARP(Address Resolution Protocol) (address resolution protocol) table function simultaneously.4. adopt many formations FIFO memory to carry out many queue managements at input side, implement multiqueue dispatching's algorithm; Adopt many formations FIFO memory to carry out go forward side by side line output scheduling of output work queue at outlet side.
Claims (6)
1. based on the support QoS network processor system of FPGA, it is characterized in that it contains the following circuit that all is made on the on-site programmable gate array FPGA:
Link layer process circuit with a plurality of ethernet controller interconnection;
Receive the packet header treatment circuit of the IP bag after classification is handled from above-mentioned link layer process circuit;
Search circuit, it is protocol detection and route control circuit, receives the header packet information of packet header treatment circuit, carries out route querying and IP bag classification searching in view of the above, and returns lookup result; The ARP that receives the transmission of link layer process circuit searches the refresh requests with ARP, and returns the ARP lookup result;
The input rank circuit, it is a kind of memorizer buffer and control circuit, receives the IP bag of packet header treatment circuit transmission and is cached to external many formations fifo fifo memory one by many formations fifo fifo memory interface one; After the request that receives dispatch circuit, the IP bag is read from buffer memory;
Dispatch circuit, it is a kind of selector circuit, select specific I P bag according to the state that external exchange mechanism chip sends by the switching network interface, and obtain this IP bag to the input rank circuit requests, after receiving the IP bag of input rank circuit, this IP bag is sent by the switching network interface;
The switching network interface, it is a kind of bidirectional high speed parallel interface, send IP bag to external exchange mechanism chip, receives the IP bag from external exchange mechanism chip simultaneously, and this IP bag is sent to the output queue circuit;
The output queue circuit, it is a kind of memorizer buffer and control circuit, and the IP bag of sending from the switching network interface is cached to external many formations fifo fifo memory two by many formations fifo fifo memory two; After the request that receives the bag transtation mission circuit, this IP bag is read from buffer memory, sent to the bag transtation mission circuit;
The bag transtation mission circuit, it is selection and control circuit on the network processing unit sending direction, receives that the IP bag back that the output queue circuit sends sends to the link layer process circuit to it;
The cpu i/f of external universal cpu, it and outside universal cpu communication send to the bag transtation mission circuit to the IP bag, receive the IP bag from the packet header treatment circuit, and send routing table and the order of classifying rules bank refresh to searching circuit;
The three-state content addressable memory TCAM interface, it is the circuit that network processing unit connects outside TCAM and realizes TCAM is controlled, through the TCAM interface with search circuit interconnection, make and search circuit, realize route querying, IP classification and ARP locating function simultaneously by external TCAM chip and the SSRAM chip of its visit; Wherein, external SSRAM is linked to each other with network processing unit by the data wire of TCAM control and SSRAM.
2. the support QoS network processor system based on FPGA according to claim 1 is characterized in that, described exchange mechanism interface is any among chip VSC870, VSC871, the VSC872.
3. the data package processing method that proposes with network processor system based on the support QoS of FPGA according to claim 1, it is characterized in that: the packet that described link layer process circuit receives is an ethernet frame, distinguishes IP bag and ARP bag according to the type field value of ethernet frame format; If the IP bag then removes the frame head of the ethernet frame of packet and postamble, obtain the IP bag, send to the packet header treatment circuit, search circuit and carry out route querying and IP bag classification searching in view of the above, and return lookup result; If the ARP request package after carrying out the ARP protocol processes, sends ARP and sends bag, and send the ARP updating message to searching circuit; If the arp reply bag sends the ARP updating message to searching circuit.
4. the support QoS network processor system based on FPGA according to claim 1, it is characterized in that: the described circuit of searching contains: control circuit module, with the two-way TCAM that is connected of this control circuit module, and input is connected with the TCAM output and with the two-way SSRAM that is connected of this control circuit module; Wherein control circuit module contains: input respectively with packet packet header receiving interface, ARP searches receiving interface, the function selector circuit that the ARP refresh interface links to each other and is used for dispatching, input termination routing table is with classifying rules bank refresh interface and output selects circuit to link to each other with aforesaid operations so that the refresh command that handle receives resolves into the instruction decomposition circuit of microcommand, be used for the aging request of ARP counting circuit to the aging request signal of above-mentioned instruction decomposition circuit output ARP table, input links to each other with function selector circuit and the continuous ARP refresh control circuit of output and instruction decomposition circuit, input links to each other with the function selector circuit output and TCAM control circuit that output links to each other with the TCAM input, I/O is connected and the TCAM output links to each other and output links to each other with function selector circuit searches data receiver circuit with SSRAM, input respectively with the above-mentioned data receiver circuit of searching, function selector circuit link to each other and output respectively with the ARP refresh control circuit, route querying and IP bag classification results transmission interface, ARP lookup result transmission interface links to each other searches data processing circuit.
5. data package processing method according to claim 3 is characterized in that: described lookup method, and it contains following steps successively:
(1) receive following data packet head information and buffer memory:
IP header packet information, TCP header packet information or UDP header packet information;
The message in routing table and classifying rules storehouse is refreshed in the IP address that receiver address analysis protocol ARP searches, refresh the ethernet address of ARP table and IP address to and buffer memory;
(2) make and search internal system and regularly produce the aging message of ARP table;
(3) message and the aging message of above-mentioned ARP table that receive are done following combined treatment:
(3.1) the message that refreshes routing table and classifying rules storehouse, the aging message of above-mentioned ARP table is decomposed into the microcommand message and the buffer memory of specific format separately;
(3.2) carry out different operating procedures respectively by following concrete condition:
When being in effective status searching the signal that internal system regularly is provided with, and when having specific format microcommand message to exist, just choose this specific format microcommand message correspondence to search three-state content addressable memory TCAM in the system, and synchronous static memory SSRAM is done read-write operation by TCAM;
When having the packet header packet information, choose the packet header packet information to do the search operation of route querying, the classification of IP bag by TCAM and SSRAM; Described packet header packet information comprises IP header packet information, TCP header packet information, UDP header packet information;
When existence was used to carry out IP address that ARP searches, the ARP search operation was done by TCAM and SSRAM in the IP address of just choosing ARP to search;
When existence be used for refreshing the external ethernet address of ARP table and IP address to the time, just choose the ethernet address that is used to refresh the ARP table and IP address to do the search operation that refreshes the ARP table by TCAM and SSRAM;
Externally send the result that route querying, the classification of IP bag and ARP search.
6. the support QoS network processor system based on FPGA according to claim 1, it is characterized in that: described link layer process circuit is the treatment circuit of light carrier level signal 48 (OC-48) interface or light carrier level signal 12 (OC-12) interface or light carrier level signal 3 (OC-3) interface, the gigabit ethernet interface treatment circuit, a kind of or several combination arbitrarily in ten thousand mbit ethernet interface treatment circuits and the 100 m ethernet interface treatment circuit.
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| CNB031026788A CN1170396C (en) | 2003-02-14 | 2003-02-14 | Network processor system for supporting QoS based on FPGA and data packages processing method |
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| CN100377019C (en) * | 2003-09-02 | 2008-03-26 | 华中科技大学 | Push-in type multishaft motion controller |
| CN1330159C (en) * | 2003-10-28 | 2007-08-01 | 华为技术有限公司 | Adaptive approach for IP networked devices to output though FC or GC interface |
| CN1330161C (en) * | 2003-10-28 | 2007-08-01 | 华为技术有限公司 | Adaptive approach for IP networked devices for output though FC or GC interface |
| JP2005136875A (en) * | 2003-10-31 | 2005-05-26 | Hitachi Ltd | Communication control apparatus |
| CN100420235C (en) * | 2005-03-21 | 2008-09-17 | 北京北方烽火科技有限公司 | Apparatus and method for high-speed recombination of IP wafer pack in SGSN |
| CN100433697C (en) * | 2006-06-01 | 2008-11-12 | 东南大学 | Multi-channel high-speed data processor and processing method |
| CN100394723C (en) * | 2006-08-14 | 2008-06-11 | 江苏中科龙梦科技有限公司 | Double reception FIFO method based on Ethernet receiving controller |
| CN101252536B (en) * | 2008-03-31 | 2010-06-02 | 清华大学 | Router multi-queue data pack buffer management and output queue scheduling system |
| CN101840374B (en) * | 2010-04-28 | 2012-06-27 | 福建星网锐捷网络有限公司 | Processing device, information searching system and information searching method |
| WO2012065301A1 (en) * | 2010-11-17 | 2012-05-24 | Telefonaktiebolaget L M Ericsson (Publ) | Field programmable gate array (fpga) and fast multi-protocol label switching (mpls) operation administration and maintenance (oam) protection switching method |
| CN102148764B (en) * | 2011-05-09 | 2013-12-11 | 杭州华三通信技术有限公司 | Data processing method and equipment based on QoS (Quality of Service) traffic |
| CN103067244B (en) * | 2012-12-25 | 2015-08-19 | 浙江大学 | A kind of virtual net quality of service realization method based on programmable switch |
| CN103683502B (en) * | 2013-11-30 | 2015-07-29 | 许继电气股份有限公司 | A kind of transformer station process bed device switching circuitry drived control method and device |
| CN107689931B (en) * | 2017-09-27 | 2021-05-14 | 广州海格通信集团股份有限公司 | System and method for realizing Ethernet switching function based on domestic FPGA |
| CN112825065A (en) * | 2019-11-21 | 2021-05-21 | 北京希姆计算科技有限公司 | Data processing circuit, apparatus and method |
| CN111526137B (en) * | 2020-04-15 | 2020-12-25 | 中科驭数（北京）科技有限公司 | Network accelerator compatible with server and client modes and data processing method |
| CN112769701A (en) * | 2020-12-30 | 2021-05-07 | 杭州迪普信息技术有限公司 | Method and device for forwarding message |
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